korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2024-12-01 08:04:22 +08:00
Code Issues Packages Projects Releases Wiki Activity

Staging driver changes for 6.4-rc1

Browse Source 
Here is the large set of staging driver updates for 6.4-rc1.  Once
 again, we removed more code than was added, a nice trend.
 
 It was a calm cycle, mostly all just small coding style cleanups,
 included in here are:
   - removal of the greybus loopback testing tools, userspace code that
     didn't belong in a driver subdirectory and was causing problems for
     some build systems
   - platform remove callback cleanups
   - rtl8192e huge cleanups
   - other small staging driver cleanups.
 
 All of these have been in linux-next for a while with no reported
 problems.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCZEp8GA8cZ3JlZ0Brcm9h
 aC5jb20ACgkQMUfUDdst+ynwpQCeLF95LYh09qG+H4uKNLfjkS/AHR0AnAkuaH/4
 4q0UhHX+jDeRFaat3qtN
 =VHqC
 -----END PGP SIGNATURE-----

Merge tag 'staging-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging

Pull staging driver updates from Greg KH:
 "Here is the large set of staging driver updates for 6.4-rc1. Once
  again, we removed more code than was added, a nice trend.

  It was a calm cycle, mostly all just small coding style cleanups,
  included in here are:

   - removal of the greybus loopback testing tools, userspace code that
     didn't belong in a driver subdirectory and was causing problems for
     some build systems

   - platform remove callback cleanups

   - rtl8192e huge cleanups

   - other small staging driver cleanups.

  All of these have been in linux-next for a while with no reported
  problems"

* tag 'staging-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (185 commits)
  staging: rtl8192e: Fix W_DISABLE# does not work after stop/start
  staging: rtl8192e: Remove unchanged variables bfsync_processing and more
  staging: rtl8192e: Remove unchanged variable frame_sync_monitor
  staging: rtl8192e: Remove unchanged variable chan_forced
  staging: rtl8192e: Remove set to true while true of bfirst_after_down
  staging: rtl8192e: Remove second initialization of bActuallySet
  staging: rtl8192e: Remove unused macro RT_SET_PS_LEVEL
  staging: rtl8192e: Remove unused function rtl92e_disable_nic
  staging: rtl8192e: Remove unchanged variable RegRfPsLevel
  staging: rtl8172: Add blank lines after declarations
  staging: rtl8192e: Remove unused variable RF_Type
  staging: rtl8192e: Remove one of two checks for hardware RTL8192SE
  staging: rtl8192e: Remove unused function _rtl92e_dm_init_wa_broadcom_iot
  staging: rtl8192e: Remove macro IS_HARDWARE_TYPE_8192SE
  staging: greybus: drop loopback test files
  staging: rtl8192e: Add blank lines after declarations
  staging: rtl8192e: avoid CamelCase <dot11RSNAStatsCCMPDecryptErrors>
  staging: rtl8192e: avoid CamelCase <dot11RSNAStatsCCMPReplays>
  staging: rtl8192e: avoid CamelCase <dot11RSNAStatsCCMPFormatErrors>
  staging: rtl8192e: fix alignment to match open parenthesis
  ...
This commit is contained in:
Linus Torvalds 2023-04-27 11:49:35 -07:00
commit 97b2ff2943
86 changed files with 890 additions and 3758 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
drivers/staging/axis-fifo/axis-fifo.c
View File

@ -103,17 +103,17 @@
* globals
* ----------------------------
*/
static int read_timeout = 1000; /* ms to wait before read() times out */
static int write_timeout = 1000; /* ms to wait before write() times out */
static long read_timeout = 1000; /* ms to wait before read() times out */
static long write_timeout = 1000; /* ms to wait before write() times out */
/* ----------------------------
* module command-line arguments
* ----------------------------
*/
module_param(read_timeout, int, 0444);
module_param(read_timeout, long, 0444);
MODULE_PARM_DESC(read_timeout, "ms to wait before blocking read() timing out; set to -1 for no timeout");
module_param(write_timeout, int, 0444);
module_param(write_timeout, long, 0444);
MODULE_PARM_DESC(write_timeout, "ms to wait before blocking write() timing out; set to -1 for no timeout");
/* ----------------------------
@ -384,9 +384,7 @@ static ssize_t axis_fifo_read(struct file *f, char __user *buf,
mutex_lock(&fifo->read_lock);
ret = wait_event_interruptible_timeout(fifo->read_queue,
ioread32(fifo->base_addr + XLLF_RDFO_OFFSET),
(read_timeout >= 0) ?
msecs_to_jiffies(read_timeout) :
MAX_SCHEDULE_TIMEOUT);
read_timeout);
if (ret <= 0) {
if (ret == 0) {
@ -528,9 +526,7 @@ static ssize_t axis_fifo_write(struct file *f, const char __user *buf,
ret = wait_event_interruptible_timeout(fifo->write_queue,
ioread32(fifo->base_addr + XLLF_TDFV_OFFSET)
>= words_to_write,
(write_timeout >= 0) ?
msecs_to_jiffies(write_timeout) :
MAX_SCHEDULE_TIMEOUT);
write_timeout);
if (ret <= 0) {
if (ret == 0) {
@ -920,15 +916,13 @@ err_initial:
return rc;
}
static int axis_fifo_remove(struct platform_device *pdev)
static void axis_fifo_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct axis_fifo *fifo = dev_get_drvdata(dev);
misc_deregister(&fifo->miscdev);
dev_set_drvdata(dev, NULL);
return 0;
}
static const struct of_device_id axis_fifo_of_match[] = {
@ -943,12 +937,22 @@ static struct platform_driver axis_fifo_driver = {
.of_match_table = axis_fifo_of_match,
},
.probe = axis_fifo_probe,
.remove = axis_fifo_remove,
.remove_new = axis_fifo_remove,
};
static int __init axis_fifo_init(void)
{
pr_info("axis-fifo driver loaded with parameters read_timeout = %i, write_timeout = %i\n",
if (read_timeout >= 0)
read_timeout = msecs_to_jiffies(read_timeout);
else
read_timeout = MAX_SCHEDULE_TIMEOUT;
if (write_timeout >= 0)
write_timeout = msecs_to_jiffies(write_timeout);
else
write_timeout = MAX_SCHEDULE_TIMEOUT;
pr_info("axis-fifo driver loaded with parameters read_timeout = %li, write_timeout = %li\n",
read_timeout, write_timeout);
return platform_driver_register(&axis_fifo_driver);
}

6
drivers/staging/emxx_udc/emxx_udc.c
View File

@ -3137,7 +3137,7 @@ static void nbu2ss_drv_shutdown(struct platform_device *pdev)
}
/*-------------------------------------------------------------------------*/
static int nbu2ss_drv_remove(struct platform_device *pdev)
static void nbu2ss_drv_remove(struct platform_device *pdev)
{
struct nbu2ss_udc *udc;
struct nbu2ss_ep *ep;
@ -3154,8 +3154,6 @@ static int nbu2ss_drv_remove(struct platform_device *pdev)
/* Interrupt Handler - Release */
free_irq(vbus_irq, udc);
return 0;
}
/*-------------------------------------------------------------------------*/
@ -3210,7 +3208,7 @@ static int nbu2ss_drv_resume(struct platform_device *pdev)
static struct platform_driver udc_driver = {
.probe = nbu2ss_drv_probe,
.shutdown = nbu2ss_drv_shutdown,
.remove = nbu2ss_drv_remove,
.remove_new = nbu2ss_drv_remove,
.suspend = nbu2ss_drv_suspend,
.resume = nbu2ss_drv_resume,
.driver = {

5
drivers/staging/fieldbus/anybuss/arcx-anybus.c
View File

@ -321,7 +321,7 @@ out_reset:
return err;
}
static int controller_remove(struct platform_device *pdev)
static void controller_remove(struct platform_device *pdev)
{
struct controller_priv *cd = platform_get_drvdata(pdev);
int id = cd->class_dev->id;
@ -329,7 +329,6 @@ static int controller_remove(struct platform_device *pdev)
device_unregister(cd->class_dev);
ida_simple_remove(&controller_index_ida, id);
gpiod_set_value_cansleep(cd->reset_gpiod, 1);
return 0;
}
static const struct of_device_id controller_of_match[] = {
@ -341,7 +340,7 @@ MODULE_DEVICE_TABLE(of, controller_of_match);
static struct platform_driver controller_driver = {
.probe = controller_probe,
.remove = controller_remove,
.remove_new = controller_remove,
.driver = {
.name = "arcx-anybus-controller",
.of_match_table = of_match_ptr(controller_of_match),

6
drivers/staging/greybus/arche-apb-ctrl.c
View File

@ -419,13 +419,11 @@ static int arche_apb_ctrl_probe(struct platform_device *pdev)
return 0;
}
static int arche_apb_ctrl_remove(struct platform_device *pdev)
static void arche_apb_ctrl_remove(struct platform_device *pdev)
{
device_remove_file(&pdev->dev, &dev_attr_state);
poweroff_seq(pdev);
platform_set_drvdata(pdev, NULL);
return 0;
}
static int __maybe_unused arche_apb_ctrl_suspend(struct device *dev)
@ -471,7 +469,7 @@ static const struct of_device_id arche_apb_ctrl_of_match[] = {
static struct platform_driver arche_apb_ctrl_device_driver = {
.probe = arche_apb_ctrl_probe,
.remove = arche_apb_ctrl_remove,
.remove_new = arche_apb_ctrl_remove,
.shutdown = arche_apb_ctrl_shutdown,
.driver = {
.name = "arche-apb-ctrl",

6
drivers/staging/greybus/arche-platform.c
View File

@ -559,7 +559,7 @@ static int arche_remove_child(struct device *dev, void *unused)
return 0;
}
static int arche_platform_remove(struct platform_device *pdev)
static void arche_platform_remove(struct platform_device *pdev)
{
struct arche_platform_drvdata *arche_pdata = platform_get_drvdata(pdev);
@ -570,8 +570,6 @@ static int arche_platform_remove(struct platform_device *pdev)
if (usb3613_hub_mode_ctrl(false))
dev_warn(arche_pdata->dev, "failed to control hub device\n");
/* TODO: Should we do anything more here ?? */
return 0;
}
static __maybe_unused int arche_platform_suspend(struct device *dev)
@ -631,7 +629,7 @@ MODULE_DEVICE_TABLE(of, arche_combined_id);
static struct platform_driver arche_platform_device_driver = {
.probe = arche_platform_probe,
.remove = arche_platform_remove,
.remove_new = arche_platform_remove,
.shutdown = arche_platform_shutdown,
.driver = {
.name = "arche-platform-ctrl",

47
drivers/staging/greybus/audio_manager_module.c
View File

@ -12,8 +12,11 @@
#define to_gb_audio_module_attr(x) \
container_of(x, struct gb_audio_manager_module_attribute, attr)
#define to_gb_audio_module(x) \
container_of(x, struct gb_audio_manager_module, kobj)
static inline struct gb_audio_manager_module *to_gb_audio_module(struct kobject *kobj)
{
return container_of(kobj, struct gb_audio_manager_module, kobj);
}
struct gb_audio_manager_module_attribute {
struct attribute attr;
@ -70,9 +73,8 @@ static void gb_audio_module_release(struct kobject *kobj)
kfree(module);
}
static ssize_t gb_audio_module_name_show(
struct gb_audio_manager_module *module,
struct gb_audio_manager_module_attribute *attr, char *buf)
static ssize_t gb_audio_module_name_show(struct gb_audio_manager_module *module,
struct gb_audio_manager_module_attribute *attr, char *buf)
{
return sprintf(buf, "%s", module->desc.name);
}
@ -80,9 +82,8 @@ static ssize_t gb_audio_module_name_show(
static struct gb_audio_manager_module_attribute gb_audio_module_name_attribute =
__ATTR(name, 0664, gb_audio_module_name_show, NULL);
static ssize_t gb_audio_module_vid_show(
struct gb_audio_manager_module *module,
struct gb_audio_manager_module_attribute *attr, char *buf)
static ssize_t gb_audio_module_vid_show(struct gb_audio_manager_module *module,
struct gb_audio_manager_module_attribute *attr, char *buf)
{
return sprintf(buf, "%d", module->desc.vid);
}
@ -90,9 +91,8 @@ static ssize_t gb_audio_module_vid_show(
static struct gb_audio_manager_module_attribute gb_audio_module_vid_attribute =
__ATTR(vid, 0664, gb_audio_module_vid_show, NULL);
static ssize_t gb_audio_module_pid_show(
struct gb_audio_manager_module *module,
struct gb_audio_manager_module_attribute *attr, char *buf)
static ssize_t gb_audio_module_pid_show(struct gb_audio_manager_module *module,
struct gb_audio_manager_module_attribute *attr, char *buf)
{
return sprintf(buf, "%d", module->desc.pid);
}
@ -100,9 +100,9 @@ static ssize_t gb_audio_module_pid_show(
static struct gb_audio_manager_module_attribute gb_audio_module_pid_attribute =
__ATTR(pid, 0664, gb_audio_module_pid_show, NULL);
static ssize_t gb_audio_module_intf_id_show(
struct gb_audio_manager_module *module,
struct gb_audio_manager_module_attribute *attr, char *buf)
static ssize_t gb_audio_module_intf_id_show(struct gb_audio_manager_module *module,
struct gb_audio_manager_module_attribute *attr,
char *buf)
{
return sprintf(buf, "%d", module->desc.intf_id);
}
@ -111,9 +111,9 @@ static struct gb_audio_manager_module_attribute
gb_audio_module_intf_id_attribute =
__ATTR(intf_id, 0664, gb_audio_module_intf_id_show, NULL);
static ssize_t gb_audio_module_ip_devices_show(
struct gb_audio_manager_module *module,
struct gb_audio_manager_module_attribute *attr, char *buf)
static ssize_t gb_audio_module_ip_devices_show(struct gb_audio_manager_module *module,
struct gb_audio_manager_module_attribute *attr,
char *buf)
{
return sprintf(buf, "0x%X", module->desc.ip_devices);
}
@ -122,9 +122,9 @@ static struct gb_audio_manager_module_attribute
gb_audio_module_ip_devices_attribute =
__ATTR(ip_devices, 0664, gb_audio_module_ip_devices_show, NULL);
static ssize_t gb_audio_module_op_devices_show(
struct gb_audio_manager_module *module,
struct gb_audio_manager_module_attribute *attr, char *buf)
static ssize_t gb_audio_module_op_devices_show(struct gb_audio_manager_module *module,
struct gb_audio_manager_module_attribute *attr,
char *buf)
{
return sprintf(buf, "0x%X", module->desc.op_devices);
}
@ -181,10 +181,9 @@ static void send_add_uevent(struct gb_audio_manager_module *module)
kobject_uevent_env(&module->kobj, KOBJ_ADD, envp);
}
int gb_audio_manager_module_create(
struct gb_audio_manager_module **module,
struct kset *manager_kset,
int id, struct gb_audio_manager_module_descriptor *desc)
int gb_audio_manager_module_create(struct gb_audio_manager_module **module,
struct kset *manager_kset,
int id, struct gb_audio_manager_module_descriptor *desc)
{
int err;
struct gb_audio_manager_module *m;

5
drivers/staging/greybus/audio_topology.c
View File

@ -24,9 +24,8 @@ struct gbaudio_ctl_pvt {
struct gb_audio_ctl_elem_info *info;
};
static struct gbaudio_module_info *find_gb_module(
struct gbaudio_codec_info *codec,
char const *name)
static struct gbaudio_module_info *find_gb_module(struct gbaudio_codec_info *codec,
char const *name)
{
int dev_id;
char begin[NAME_SIZE];

7
drivers/staging/greybus/gpio.c
View File

@ -41,8 +41,11 @@ struct gb_gpio_controller {
struct irq_chip irqc;
struct mutex irq_lock;
};
#define gpio_chip_to_gb_gpio_controller(chip) \
container_of(chip, struct gb_gpio_controller, chip)
static inline struct gb_gpio_controller *gpio_chip_to_gb_gpio_controller(struct gpio_chip *chip)
{
return container_of(chip, struct gb_gpio_controller, chip);
}
static struct gpio_chip *irq_data_to_gpio_chip(struct irq_data *d)
{

1
drivers/staging/greybus/greybus_authentication.h
View File

@ -41,7 +41,6 @@
#define CAP_AUTH_RESULT_CR_NO_KEY 0x03
#define CAP_AUTH_RESULT_CR_SIG_FAIL 0x04
/* IOCTL support */
struct cap_ioc_get_endpoint_uid {
__u8 uid[8];

6
drivers/staging/greybus/pwm.c
View File

@ -21,9 +21,11 @@ struct gb_pwm_chip {
struct pwm_chip chip;
struct pwm_chip *pwm;
};
#define pwm_chip_to_gb_pwm_chip(chip) \
container_of(chip, struct gb_pwm_chip, chip)
static inline struct gb_pwm_chip *pwm_chip_to_gb_pwm_chip(struct pwm_chip *chip)
{
return container_of(chip, struct gb_pwm_chip, chip);
}
static int gb_pwm_count_operation(struct gb_pwm_chip *pwmc)
{

2
drivers/staging/greybus/tools/.gitignore vendored
View File

@ -1,2 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
loopback_test

10
drivers/staging/greybus/tools/Android.mk
View File

@ -1,10 +0,0 @@
LOCAL_PATH:= $(call my-dir)
include $(CLEAR_VARS)
LOCAL_SRC_FILES:= loopback_test.c
LOCAL_MODULE_TAGS := optional
LOCAL_MODULE := gb_loopback_test
include $(BUILD_EXECUTABLE)

33
drivers/staging/greybus/tools/Makefile
View File

@ -1,33 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
ifeq ($(strip $(V)), 1)
Q =
else
Q = @
endif
CFLAGS += -std=gnu99 -Wall -Wextra -g \
-D_GNU_SOURCE \
-Wno-unused-parameter \
-Wmaybe-uninitialized \
-Wredundant-decls \
-Wcast-align \
-Wsign-compare \
-Wno-missing-field-initializers \
-Wno-shift-negative-value
CC := $(CROSS_COMPILE)gcc
TOOLS = loopback_test
all: $(TOOLS)
%.o: %.c ../greybus_protocols.h
@echo ' TARGET_CC $@'
$(Q)$(CC) $(CFLAGS) -c $< -o $@
loopback_%: loopback_%.o
@echo ' TARGET_LD $@'
$(Q)$(CC) $(CFLAGS) $(LDFLAGS) $^ -o $@
clean::
rm -f *.o $(TOOLS)

198
drivers/staging/greybus/tools/README.loopback
View File

@ -1,198 +0,0 @@
1 - LOOPBACK DRIVER
The driver implements the main logic of the loopback test and provides
sysfs files to configure the test and retrieve the results.
A user could run a test without the need of the test application given
that he understands the sysfs interface of the loopback driver.
The loopback kernel driver needs to be loaded and at least one module
with the loopback feature enabled must be present for the sysfs files to be
created and for the loopback test application to be able to run.
To load the module:
# modprobe gb-loopback
When the module is probed, New files are available on the sysfs
directory of the detected loopback device.
(typically under "/sys/bus/graybus/devices").
Here is a short summary of the sysfs interface files that should be visible:
* Loopback Configuration Files:
async - Use asynchronous operations.
iteration_max - Number of tests iterations to perform.
size - payload size of the transfer.
timeout - The number of microseconds to give an individual
asynchronous request before timing out.
us_wait - Time to wait between 2 messages
type - By writing the test type to this file, the test starts.
Valid tests are:
0 stop the test
2 - ping
3 - transfer
4 - sink
* Loopback feedback files:
error - number of errors that have occurred.
iteration_count - Number of iterations performed.
requests_completed - Number of requests successfully completed.
requests_timedout - Number of requests that have timed out.
timeout_max - Max allowed timeout
timeout_min - Min allowed timeout.
* Loopback result files:
apbridge_unipro_latency_avg
apbridge_unipro_latency_max
apbridge_unipro_latency_min
gpbridge_firmware_latency_avg
gpbridge_firmware_latency_max
gpbridge_firmware_latency_min
requests_per_second_avg
requests_per_second_max
requests_per_second_min
latency_avg
latency_max
latency_min
throughput_avg
throughput_max
throughput_min
2 - LOOPBACK TEST APPLICATION
The loopback test application manages and formats the results provided by
the loopback kernel module. The purpose of this application
is to:
- Start and manage multiple loopback device tests concurrently.
- Calculate the aggregate results for multiple devices.
- Gather and format test results (csv or human readable).
The best way to get up to date usage information for the application is
usually to pass the "-h" parameter.
Here is the summary of the available options:
Mandatory arguments
-t must be one of the test names - sink, transfer or ping
-i iteration count - the number of iterations to run the test over
Optional arguments
-S sysfs location - location for greybus 'endo' entries default /sys/bus/greybus/devices/
-D debugfs location - location for loopback debugfs entries default /sys/kernel/debug/gb_loopback/
-s size of data packet to send during test - defaults to zero
-m mask - a bit mask of connections to include example: -m 8 = 4th connection -m 9 = 1st and 4th connection etc
default is zero which means broadcast to all connections
-v verbose output
-d debug output
-r raw data output - when specified the full list of latency values are included in the output CSV
-p porcelain - when specified printout is in a user-friendly non-CSV format. This option suppresses writing to CSV file
-a aggregate - show aggregation of all enabled devies
-l list found loopback devices and exit.
-x Async - Enable async transfers.
-o Timeout - Timeout in microseconds for async operations.
3 - REAL WORLD EXAMPLE USAGES
3.1 - Using the driver sysfs files to run a test on a single device:
* Run a 1000 transfers of a 100 byte packet. Each transfer is started only
after the previous one finished successfully:
echo 0 > /sys/bus/greybus/devices/1-2.17/type
echo 0 > /sys/bus/greybus/devices/1-2.17/async
echo 2000 > /sys/bus/greybus/devices/1-2.17/us_wait
echo 100 > /sys/bus/greybus/devices/1-2.17/size
echo 1000 > /sys/bus/greybus/devices/1-2.17/iteration_max
echo 0 > /sys/bus/greybus/devices/1-2.17/mask
echo 200000 > /sys/bus/greybus/devices/1-2.17/timeout
echo 3 > /sys/bus/greybus/devices/1-2.17/type
* Run a 1000 transfers of a 100 byte packet. Transfers are started without
waiting for the previous one to finish:
echo 0 > /sys/bus/greybus/devices/1-2.17/type
echo 3 > /sys/bus/greybus/devices/1-2.17/async
echo 0 > /sys/bus/greybus/devices/1-2.17/us_wait
echo 100 > /sys/bus/greybus/devices/1-2.17/size
echo 1000 > /sys/bus/greybus/devices/1-2.17/iteration_max
echo 0 > /sys/bus/greybus/devices/1-2.17/mask
echo 200000 > /sys/bus/greybus/devices/1-2.17/timeout
echo 3 > /sys/bus/greybus/devices/1-2.17/type
* Read the results from sysfs:
cat /sys/bus/greybus/devices/1-2.17/requests_per_second_min
cat /sys/bus/greybus/devices/1-2.17/requests_per_second_max
cat /sys/bus/greybus/devices/1-2.17/requests_per_second_avg
cat /sys/bus/greybus/devices/1-2.17/latency_min
cat /sys/bus/greybus/devices/1-2.17/latency_max
cat /sys/bus/greybus/devices/1-2.17/latency_avg
cat /sys/bus/greybus/devices/1-2.17/apbridge_unipro_latency_min
cat /sys/bus/greybus/devices/1-2.17/apbridge_unipro_latency_max
cat /sys/bus/greybus/devices/1-2.17/apbridge_unipro_latency_avg
cat /sys/bus/greybus/devices/1-2.17/gpbridge_firmware_latency_min
cat /sys/bus/greybus/devices/1-2.17/gpbridge_firmware_latency_max
cat /sys/bus/greybus/devices/1-2.17/gpbridge_firmware_latency_avg
cat /sys/bus/greybus/devices/1-2.17/error
cat /sys/bus/greybus/devices/1-2.17/requests_completed
cat /sys/bus/greybus/devices/1-2.17/requests_timedout
3.2 - using the test application:
* Run a transfer test 10 iterations of size 100 bytes on all available devices
#/loopback_test -t transfer -i 10 -s 100
1970-1-1 0:10:7,transfer,1-4.17,100,10,0,443,509,471.700012,66,1963,2256,2124.600098,293,102776,118088,109318.898438,15312,1620,1998,1894.099976,378,56,57,56.799999,1
1970-1-1 0:10:7,transfer,1-5.17,100,10,0,399,542,463.399994,143,1845,2505,2175.800049,660,92568,125744,107393.296875,33176,1469,2305,1806.500000,836,56,57,56.799999,1
* Show the aggregate results of both devices. ("-a")
#/loopback_test -t transfer -i 10 -s 100 -a
1970-1-1 0:10:35,transfer,1-4.17,100,10,0,448,580,494.100006,132,1722,2230,2039.400024,508,103936,134560,114515.703125,30624,1513,1980,1806.900024,467,56,57,57.299999,1
1970-1-1 0:10:35,transfer,1-5.17,100,10,0,383,558,478.600006,175,1791,2606,2115.199951,815,88856,129456,110919.703125,40600,1457,2246,1773.599976,789,56,57,57.099998,1
1970-1-1 0:10:35,transfer,aggregate,100,10,0,383,580,486.000000,197,1722,2606,2077.000000,884,88856,134560,112717.000000,45704,1457,2246,1789.000000,789,56,57,57.000000,1
* Example usage of the mask option to select which devices will
run the test (1st, 2nd, or both devices):
# /loopback_test -t transfer -i 10 -s 100 -m 1
1970-1-1 0:11:56,transfer,1-4.17,100,10,0,514,558,544.900024,44,1791,1943,1836.599976,152,119248,129456,126301.296875,10208,1600,1001609,101613.601562,1000009,56,57,56.900002,1
# /loopback_test -t transfer -i 10 -s 100 -m 2
1970-1-1 0:12:0,transfer,1-5.17,100,10,0,468,554,539.000000,86,1804,2134,1859.500000,330,108576,128528,124932.500000,19952,1606,1626,1619.300049,20,56,57,57.400002,1
# /loopback_test -t transfer -i 10 -s 100 -m 3
1970-1-1 0:12:3,transfer,1-4.17,100,10,0,432,510,469.399994,78,1959,2313,2135.800049,354,100224,118320,108785.296875,18096,1610,2024,1893.500000,414,56,57,57.200001,1
1970-1-1 0:12:3,transfer,1-5.17,100,10,0,404,542,468.799988,138,1843,2472,2152.500000,629,93728,125744,108646.101562,32016,1504,2247,1853.099976,743,56,57,57.099998,1
* Show output in human readable format ("-p")
# /loopback_test -t transfer -i 10 -s 100 -m 3 -p
1970-1-1 0:12:37
test: transfer
path: 1-4.17
size: 100
iterations: 10
errors: 0
async: Disabled
requests per-sec: min=390, max=547, average=469.299988, jitter=157
ap-throughput B/s: min=90480 max=126904 average=108762.101562 jitter=36424
ap-latency usec: min=1826 max=2560 average=2146.000000 jitter=734
apbridge-latency usec: min=1620 max=1982 average=1882.099976 jitter=362
gpbridge-latency usec: min=56 max=57 average=57.099998 jitter=1
1970-1-1 0:12:37
test: transfer
path: 1-5.17
size: 100
iterations: 10
errors: 0
async: Disabled
requests per-sec: min=397, max=538, average=461.700012, jitter=141
ap-throughput B/s: min=92104 max=124816 average=106998.898438 jitter=32712
ap-latency usec: min=1856 max=2514 average=2185.699951 jitter=658
apbridge-latency usec: min=1460 max=2296 average=1828.599976 jitter=836
gpbridge-latency usec: min=56 max=57 average=57.099998 jitter=1

169
drivers/staging/greybus/tools/lbtest
View File

@ -1,169 +0,0 @@
#!/usr/bin/env python
# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2015 Google, Inc.
# Copyright (c) 2015 Linaro, Ltd.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from this
# software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from __future__ import print_function
import csv
import datetime
import sys
import time
dict = {'ping': '2', 'transfer': '3', 'sink': '4'}
verbose = 1
def abort():
sys.exit(1)
def usage():
print('Usage: looptest TEST SIZE ITERATIONS PATH\n\n'
' Run TEST for a number of ITERATIONS with operation data SIZE bytes\n'
' TEST may be \'ping\' \'transfer\' or \'sink\'\n'
' SIZE indicates the size of transfer <= greybus max payload bytes\n'
' ITERATIONS indicates the number of times to execute TEST at SIZE bytes\n'
' Note if ITERATIONS is set to zero then this utility will\n'
' initiate an infinite (non terminating) test and exit\n'
' without logging any metrics data\n'
' PATH indicates the sysfs path for the loopback greybus entries e.g.\n'
' /sys/bus/greybus/devices/endo0:1:1:1:1/\n'
'Examples:\n'
' looptest transfer 128 10000\n'
' looptest ping 0 128\n'
' looptest sink 2030 32768\n'
.format(sys.argv[0]), file=sys.stderr)
abort()
def read_sysfs_int(path):
try:
f = open(path, "r");
val = f.read();
f.close()
return int(val)
except IOError as e:
print("I/O error({0}): {1}".format(e.errno, e.strerror))
print("Invalid path %s" % path)
def write_sysfs_val(path, val):
try:
f = open(path, "r+")
f.write(val)
f.close()
except IOError as e:
print("I/O error({0}): {1}".format(e.errno, e.strerror))
print("Invalid path %s" % path)
def log_csv(test_name, size, iteration_max, sys_pfx):
# file name will test_name_size_iteration_max.csv
# every time the same test with the same parameters is run we will then
# append to the same CSV with datestamp - representing each test dataset
fname = test_name + '_' + size + '_' + str(iteration_max) + '.csv'
try:
# gather data set
date = str(datetime.datetime.now())
error = read_sysfs_int(sys_pfx + 'error')
request_min = read_sysfs_int(sys_pfx + 'requests_per_second_min')
request_max = read_sysfs_int(sys_pfx + 'requests_per_second_max')
request_avg = read_sysfs_int(sys_pfx + 'requests_per_second_avg')
latency_min = read_sysfs_int(sys_pfx + 'latency_min')
latency_max = read_sysfs_int(sys_pfx + 'latency_max')
latency_avg = read_sysfs_int(sys_pfx + 'latency_avg')
throughput_min = read_sysfs_int(sys_pfx + 'throughput_min')
throughput_max = read_sysfs_int(sys_pfx + 'throughput_max')
throughput_avg = read_sysfs_int(sys_pfx + 'throughput_avg')
# derive jitter
request_jitter = request_max - request_min
latency_jitter = latency_max - latency_min
throughput_jitter = throughput_max - throughput_min
# append data set to file
with open(fname, 'a') as csvf:
row = csv.writer(csvf, delimiter=",", quotechar="'",
quoting=csv.QUOTE_MINIMAL)
row.writerow([date, test_name, size, iteration_max, error,
request_min, request_max, request_avg, request_jitter,
latency_min, latency_max, latency_avg, latency_jitter,
throughput_min, throughput_max, throughput_avg, throughput_jitter])
except IOError as e:
print("I/O error({0}): {1}".format(e.errno, e.strerror))
def loopback_run(test_name, size, iteration_max, sys_pfx):
test_id = dict[test_name]
try:
# Terminate any currently running test
write_sysfs_val(sys_pfx + 'type', '0')
# Set parameter for no wait between messages
write_sysfs_val(sys_pfx + 'ms_wait', '0')
# Set operation size
write_sysfs_val(sys_pfx + 'size', size)
# Set iterations
write_sysfs_val(sys_pfx + 'iteration_max', str(iteration_max))
# Initiate by setting loopback operation type
write_sysfs_val(sys_pfx + 'type', test_id)
time.sleep(1)
if iteration_max == 0:
print ("Infinite test initiated CSV won't be logged\n")
return
previous = 0
err = 0
while True:
# get current count bail out if it hasn't changed
iteration_count = read_sysfs_int(sys_pfx + 'iteration_count')
if previous == iteration_count:
err = 1
break
elif iteration_count == iteration_max:
break
previous = iteration_count
if verbose:
print('%02d%% complete %d of %d ' %
(100 * iteration_count / iteration_max,
iteration_count, iteration_max))
time.sleep(1)
if err:
print ('\nError executing test\n')
else:
log_csv(test_name, size, iteration_max, sys_pfx)
except ValueError as ve:
print("Error: %s " % format(e.strerror), file=sys.stderr)
abort()
def main():
if len(sys.argv) < 5:
usage()
if sys.argv[1] in dict.keys():
loopback_run(sys.argv[1], sys.argv[2], int(sys.argv[3]), sys.argv[4])
else:
usage()
if __name__ == '__main__':
main()

979
drivers/staging/greybus/tools/loopback_test.c
View File

@ -1,979 +0,0 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Loopback test application
*
* Copyright 2015 Google Inc.
* Copyright 2015 Linaro Ltd.
*/
#include <errno.h>
#include <fcntl.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <stdint.h>
#include <poll.h>
#include <sys/types.h>
#include <time.h>
#include <unistd.h>
#include <dirent.h>
#include <signal.h>
#define MAX_NUM_DEVICES 10
#define MAX_SYSFS_PREFIX 0x80
#define MAX_SYSFS_PATH 0x200
#define CSV_MAX_LINE 0x1000
#define SYSFS_MAX_INT 0x20
#define MAX_STR_LEN 255
#define DEFAULT_ASYNC_TIMEOUT 200000
struct dict {
char *name;
int type;
};
static struct dict dict[] = {
{"ping", 2},
{"transfer", 3},
{"sink", 4},
{NULL,} /* list termination */
};
struct loopback_results {
float latency_avg;
uint32_t latency_max;
uint32_t latency_min;
uint32_t latency_jitter;
float request_avg;
uint32_t request_max;
uint32_t request_min;
uint32_t request_jitter;
float throughput_avg;
uint32_t throughput_max;
uint32_t throughput_min;
uint32_t throughput_jitter;
float apbridge_unipro_latency_avg;
uint32_t apbridge_unipro_latency_max;
uint32_t apbridge_unipro_latency_min;
uint32_t apbridge_unipro_latency_jitter;
float gbphy_firmware_latency_avg;
uint32_t gbphy_firmware_latency_max;
uint32_t gbphy_firmware_latency_min;
uint32_t gbphy_firmware_latency_jitter;
uint32_t error;
};
struct loopback_device {
char name[MAX_STR_LEN];
char sysfs_entry[MAX_SYSFS_PATH];
char debugfs_entry[MAX_SYSFS_PATH];
struct loopback_results results;
};
struct loopback_test {
int verbose;
int debug;
int raw_data_dump;
int porcelain;
int mask;
int size;
int iteration_max;
int aggregate_output;
int test_id;
int device_count;
int list_devices;
int use_async;
int async_timeout;
int async_outstanding_operations;
int us_wait;
int file_output;
int stop_all;
int poll_count;
char test_name[MAX_STR_LEN];
char sysfs_prefix[MAX_SYSFS_PREFIX];
char debugfs_prefix[MAX_SYSFS_PREFIX];
struct timespec poll_timeout;
struct loopback_device devices[MAX_NUM_DEVICES];
struct loopback_results aggregate_results;
struct pollfd fds[MAX_NUM_DEVICES];
};
struct loopback_test t;
/* Helper macros to calculate the aggregate results for all devices */
static inline int device_enabled(struct loopback_test *t, int dev_idx);
#define GET_MAX(field) \
static int get_##field##_aggregate(struct loopback_test *t) \
{ \
uint32_t max = 0; \
int i; \
for (i = 0; i < t->device_count; i++) { \
if (!device_enabled(t, i)) \
continue; \
if (t->devices[i].results.field > max) \
max = t->devices[i].results.field; \
} \
return max; \
} \
#define GET_MIN(field) \
static int get_##field##_aggregate(struct loopback_test *t) \
{ \
uint32_t min = ~0; \
int i; \
for (i = 0; i < t->device_count; i++) { \
if (!device_enabled(t, i)) \
continue; \
if (t->devices[i].results.field < min) \
min = t->devices[i].results.field; \
} \
return min; \
} \
#define GET_AVG(field) \
static int get_##field##_aggregate(struct loopback_test *t) \
{ \
uint32_t val = 0; \
uint32_t count = 0; \
int i; \
for (i = 0; i < t->device_count; i++) { \
if (!device_enabled(t, i)) \
continue; \
count++; \
val += t->devices[i].results.field; \
} \
if (count) \
val /= count; \
return val; \
} \
GET_MAX(throughput_max);
GET_MAX(request_max);
GET_MAX(latency_max);
GET_MAX(apbridge_unipro_latency_max);
GET_MAX(gbphy_firmware_latency_max);
GET_MIN(throughput_min);
GET_MIN(request_min);
GET_MIN(latency_min);
GET_MIN(apbridge_unipro_latency_min);
GET_MIN(gbphy_firmware_latency_min);
GET_AVG(throughput_avg);
GET_AVG(request_avg);
GET_AVG(latency_avg);
GET_AVG(apbridge_unipro_latency_avg);
GET_AVG(gbphy_firmware_latency_avg);
void abort(void)
{
_exit(1);
}
void usage(void)
{
fprintf(stderr, "Usage: loopback_test TEST [SIZE] ITERATIONS [SYSPATH] [DBGPATH]\n\n"
" Run TEST for a number of ITERATIONS with operation data SIZE bytes\n"
" TEST may be \'ping\' \'transfer\' or \'sink\'\n"
" SIZE indicates the size of transfer <= greybus max payload bytes\n"
" ITERATIONS indicates the number of times to execute TEST at SIZE bytes\n"
" Note if ITERATIONS is set to zero then this utility will\n"
" initiate an infinite (non terminating) test and exit\n"
" without logging any metrics data\n"
" SYSPATH indicates the sysfs path for the loopback greybus entries e.g.\n"
" /sys/bus/greybus/devices\n"
" DBGPATH indicates the debugfs path for the loopback greybus entries e.g.\n"
" /sys/kernel/debug/gb_loopback/\n"
" Mandatory arguments\n"
" -t must be one of the test names - sink, transfer or ping\n"
" -i iteration count - the number of iterations to run the test over\n"
" Optional arguments\n"
" -S sysfs location - location for greybus 'endo' entries default /sys/bus/greybus/devices/\n"
" -D debugfs location - location for loopback debugfs entries default /sys/kernel/debug/gb_loopback/\n"
" -s size of data packet to send during test - defaults to zero\n"
" -m mask - a bit mask of connections to include example: -m 8 = 4th connection -m 9 = 1st and 4th connection etc\n"
" default is zero which means broadcast to all connections\n"
" -v verbose output\n"
" -d debug output\n"
" -r raw data output - when specified the full list of latency values are included in the output CSV\n"
" -p porcelain - when specified printout is in a user-friendly non-CSV format. This option suppresses writing to CSV file\n"
" -a aggregate - show aggregation of all enabled devices\n"
" -l list found loopback devices and exit\n"
" -x Async - Enable async transfers\n"
" -o Async Timeout - Timeout in uSec for async operations\n"
" -O Poll loop time out in seconds(max time a test is expected to last, default: 30sec)\n"
" -c Max number of outstanding operations for async operations\n"
" -w Wait in uSec between operations\n"
" -z Enable output to a CSV file (incompatible with -p)\n"
" -f When starting new loopback test, stop currently running tests on all devices\n"
"Examples:\n"
" Send 10000 transfers with a packet size of 128 bytes to all active connections\n"
" loopback_test -t transfer -s 128 -i 10000 -S /sys/bus/greybus/devices/ -D /sys/kernel/debug/gb_loopback/\n"
" loopback_test -t transfer -s 128 -i 10000 -m 0\n"
" Send 10000 transfers with a packet size of 128 bytes to connection 1 and 4\n"
" loopback_test -t transfer -s 128 -i 10000 -m 9\n"
" loopback_test -t ping -s 0 128 -i -S /sys/bus/greybus/devices/ -D /sys/kernel/debug/gb_loopback/\n"
" loopback_test -t sink -s 2030 -i 32768 -S /sys/bus/greybus/devices/ -D /sys/kernel/debug/gb_loopback/\n");
abort();
}
static inline int device_enabled(struct loopback_test *t, int dev_idx)
{
if (!t->mask || (t->mask & (1 << dev_idx)))
return 1;
return 0;
}
static void show_loopback_devices(struct loopback_test *t)
{
int i;
if (t->device_count == 0) {
printf("No loopback devices.\n");
return;
}
for (i = 0; i < t->device_count; i++)
printf("device[%d] = %s\n", i, t->devices[i].name);
}
int open_sysfs(const char *sys_pfx, const char *node, int flags)
{
int fd;
char path[MAX_SYSFS_PATH];
snprintf(path, sizeof(path), "%s%s", sys_pfx, node);
fd = open(path, flags);
if (fd < 0) {
fprintf(stderr, "unable to open %s\n", path);
abort();
}
return fd;
}
int read_sysfs_int_fd(int fd, const char *sys_pfx, const char *node)
{
char buf[SYSFS_MAX_INT];
if (read(fd, buf, sizeof(buf)) < 0) {
fprintf(stderr, "unable to read from %s%s %s\n", sys_pfx, node,
strerror(errno));
close(fd);
abort();
}
return atoi(buf);
}
float read_sysfs_float_fd(int fd, const char *sys_pfx, const char *node)
{
char buf[SYSFS_MAX_INT];
if (read(fd, buf, sizeof(buf)) < 0) {
fprintf(stderr, "unable to read from %s%s %s\n", sys_pfx, node,
strerror(errno));
close(fd);
abort();
}
return atof(buf);
}
int read_sysfs_int(const char *sys_pfx, const char *node)
{
int fd, val;
fd = open_sysfs(sys_pfx, node, O_RDONLY);
val = read_sysfs_int_fd(fd, sys_pfx, node);
close(fd);
return val;
}
float read_sysfs_float(const char *sys_pfx, const char *node)
{
int fd;
float val;
fd = open_sysfs(sys_pfx, node, O_RDONLY);
val = read_sysfs_float_fd(fd, sys_pfx, node);
close(fd);
return val;
}
void write_sysfs_val(const char *sys_pfx, const char *node, int val)
{
int fd, len;
char buf[SYSFS_MAX_INT];
fd = open_sysfs(sys_pfx, node, O_RDWR);
len = snprintf(buf, sizeof(buf), "%d", val);
if (write(fd, buf, len) < 0) {
fprintf(stderr, "unable to write to %s%s %s\n", sys_pfx, node,
strerror(errno));
close(fd);
abort();
}
close(fd);
}
static int get_results(struct loopback_test *t)
{
struct loopback_device *d;
struct loopback_results *r;
int i;
for (i = 0; i < t->device_count; i++) {
if (!device_enabled(t, i))
continue;
d = &t->devices[i];
r = &d->results;
r->error = read_sysfs_int(d->sysfs_entry, "error");
r->request_min = read_sysfs_int(d->sysfs_entry, "requests_per_second_min");
r->request_max = read_sysfs_int(d->sysfs_entry, "requests_per_second_max");
r->request_avg = read_sysfs_float(d->sysfs_entry, "requests_per_second_avg");
r->latency_min = read_sysfs_int(d->sysfs_entry, "latency_min");
r->latency_max = read_sysfs_int(d->sysfs_entry, "latency_max");
r->latency_avg = read_sysfs_float(d->sysfs_entry, "latency_avg");
r->throughput_min = read_sysfs_int(d->sysfs_entry, "throughput_min");
r->throughput_max = read_sysfs_int(d->sysfs_entry, "throughput_max");
r->throughput_avg = read_sysfs_float(d->sysfs_entry, "throughput_avg");
r->apbridge_unipro_latency_min =
read_sysfs_int(d->sysfs_entry, "apbridge_unipro_latency_min");
r->apbridge_unipro_latency_max =
read_sysfs_int(d->sysfs_entry, "apbridge_unipro_latency_max");
r->apbridge_unipro_latency_avg =
read_sysfs_float(d->sysfs_entry, "apbridge_unipro_latency_avg");
r->gbphy_firmware_latency_min =
read_sysfs_int(d->sysfs_entry, "gbphy_firmware_latency_min");
r->gbphy_firmware_latency_max =
read_sysfs_int(d->sysfs_entry, "gbphy_firmware_latency_max");
r->gbphy_firmware_latency_avg =
read_sysfs_float(d->sysfs_entry, "gbphy_firmware_latency_avg");
r->request_jitter = r->request_max - r->request_min;
r->latency_jitter = r->latency_max - r->latency_min;
r->throughput_jitter = r->throughput_max - r->throughput_min;
r->apbridge_unipro_latency_jitter =
r->apbridge_unipro_latency_max - r->apbridge_unipro_latency_min;
r->gbphy_firmware_latency_jitter =
r->gbphy_firmware_latency_max - r->gbphy_firmware_latency_min;
}
/*calculate the aggregate results of all enabled devices */
if (t->aggregate_output) {
r = &t->aggregate_results;
r->request_min = get_request_min_aggregate(t);
r->request_max = get_request_max_aggregate(t);
r->request_avg = get_request_avg_aggregate(t);
r->latency_min = get_latency_min_aggregate(t);
r->latency_max = get_latency_max_aggregate(t);
r->latency_avg = get_latency_avg_aggregate(t);
r->throughput_min = get_throughput_min_aggregate(t);
r->throughput_max = get_throughput_max_aggregate(t);
r->throughput_avg = get_throughput_avg_aggregate(t);
r->apbridge_unipro_latency_min =
get_apbridge_unipro_latency_min_aggregate(t);
r->apbridge_unipro_latency_max =
get_apbridge_unipro_latency_max_aggregate(t);
r->apbridge_unipro_latency_avg =
get_apbridge_unipro_latency_avg_aggregate(t);
r->gbphy_firmware_latency_min =
get_gbphy_firmware_latency_min_aggregate(t);
r->gbphy_firmware_latency_max =
get_gbphy_firmware_latency_max_aggregate(t);
r->gbphy_firmware_latency_avg =
get_gbphy_firmware_latency_avg_aggregate(t);
r->request_jitter = r->request_max - r->request_min;
r->latency_jitter = r->latency_max - r->latency_min;
r->throughput_jitter = r->throughput_max - r->throughput_min;
r->apbridge_unipro_latency_jitter =
r->apbridge_unipro_latency_max - r->apbridge_unipro_latency_min;
r->gbphy_firmware_latency_jitter =
r->gbphy_firmware_latency_max - r->gbphy_firmware_latency_min;
}
return 0;
}
int format_output(struct loopback_test *t,
struct loopback_results *r,
const char *dev_name,
char *buf, int buf_len,
struct tm *tm)
{
int len = 0;
memset(buf, 0x00, buf_len);
len = snprintf(buf, buf_len, "%u-%u-%u %u:%u:%u",
tm->tm_year + 1900, tm->tm_mon + 1, tm->tm_mday,
tm->tm_hour, tm->tm_min, tm->tm_sec);
if (t->porcelain) {
len += snprintf(&buf[len], buf_len - len,
"\n test:\t\t\t%s\n path:\t\t\t%s\n size:\t\t\t%u\n iterations:\t\t%u\n errors:\t\t%u\n async:\t\t\t%s\n",
t->test_name,
dev_name,
t->size,
t->iteration_max,
r->error,
t->use_async ? "Enabled" : "Disabled");
len += snprintf(&buf[len], buf_len - len,
" requests per-sec:\tmin=%u, max=%u, average=%f, jitter=%u\n",
r->request_min,
r->request_max,
r->request_avg,
r->request_jitter);
len += snprintf(&buf[len], buf_len - len,
" ap-throughput B/s:\tmin=%u max=%u average=%f jitter=%u\n",
r->throughput_min,
r->throughput_max,
r->throughput_avg,
r->throughput_jitter);
len += snprintf(&buf[len], buf_len - len,
" ap-latency usec:\tmin=%u max=%u average=%f jitter=%u\n",
r->latency_min,
r->latency_max,
r->latency_avg,
r->latency_jitter);
len += snprintf(&buf[len], buf_len - len,
" apbridge-latency usec:\tmin=%u max=%u average=%f jitter=%u\n",
r->apbridge_unipro_latency_min,
r->apbridge_unipro_latency_max,
r->apbridge_unipro_latency_avg,
r->apbridge_unipro_latency_jitter);
len += snprintf(&buf[len], buf_len - len,
" gbphy-latency usec:\tmin=%u max=%u average=%f jitter=%u\n",
r->gbphy_firmware_latency_min,
r->gbphy_firmware_latency_max,
r->gbphy_firmware_latency_avg,
r->gbphy_firmware_latency_jitter);
} else {
len += snprintf(&buf[len], buf_len - len, ",%s,%s,%u,%u,%u",
t->test_name, dev_name, t->size, t->iteration_max,
r->error);
len += snprintf(&buf[len], buf_len - len, ",%u,%u,%f,%u",
r->request_min,
r->request_max,
r->request_avg,
r->request_jitter);
len += snprintf(&buf[len], buf_len - len, ",%u,%u,%f,%u",
r->latency_min,
r->latency_max,
r->latency_avg,
r->latency_jitter);
len += snprintf(&buf[len], buf_len - len, ",%u,%u,%f,%u",
r->throughput_min,
r->throughput_max,
r->throughput_avg,
r->throughput_jitter);
len += snprintf(&buf[len], buf_len - len, ",%u,%u,%f,%u",
r->apbridge_unipro_latency_min,
r->apbridge_unipro_latency_max,
r->apbridge_unipro_latency_avg,
r->apbridge_unipro_latency_jitter);
len += snprintf(&buf[len], buf_len - len, ",%u,%u,%f,%u",
r->gbphy_firmware_latency_min,
r->gbphy_firmware_latency_max,
r->gbphy_firmware_latency_avg,
r->gbphy_firmware_latency_jitter);
}
printf("\n%s\n", buf);
return len;
}
static int log_results(struct loopback_test *t)
{
int fd, i, len, ret;
struct tm tm;
time_t local_time;
char file_name[MAX_SYSFS_PATH];
char data[CSV_MAX_LINE];
local_time = time(NULL);
tm = *localtime(&local_time);
/*
* file name will test_name_size_iteration_max.csv
* every time the same test with the same parameters is run we will then
* append to the same CSV with datestamp - representing each test
* dataset.
*/
if (t->file_output && !t->porcelain) {
snprintf(file_name, sizeof(file_name), "%s_%d_%d.csv",
t->test_name, t->size, t->iteration_max);
fd = open(file_name, O_WRONLY | O_CREAT | O_APPEND, 0644);
if (fd < 0) {
fprintf(stderr, "unable to open %s for appending\n", file_name);
abort();
}
}
for (i = 0; i < t->device_count; i++) {
if (!device_enabled(t, i))
continue;
len = format_output(t, &t->devices[i].results,
t->devices[i].name,
data, sizeof(data), &tm);
if (t->file_output && !t->porcelain) {
ret = write(fd, data, len);
if (ret == -1)
fprintf(stderr, "unable to write %d bytes to csv.\n", len);
}
}
if (t->aggregate_output) {
len = format_output(t, &t->aggregate_results, "aggregate",
data, sizeof(data), &tm);
if (t->file_output && !t->porcelain) {
ret = write(fd, data, len);
if (ret == -1)
fprintf(stderr, "unable to write %d bytes to csv.\n", len);
}
}
if (t->file_output && !t->porcelain)
close(fd);
return 0;
}
int is_loopback_device(const char *path, const char *node)
{
char file[MAX_SYSFS_PATH];
snprintf(file, MAX_SYSFS_PATH, "%s%s/iteration_count", path, node);
if (access(file, F_OK) == 0)
return 1;
return 0;
}
int find_loopback_devices(struct loopback_test *t)
{
struct dirent **namelist;
int i, n, ret;
unsigned int dev_id;
struct loopback_device *d;
n = scandir(t->sysfs_prefix, &namelist, NULL, alphasort);
if (n < 0) {
perror("scandir");
ret = -ENODEV;
goto baddir;
}
/* Don't include '.' and '..' */
if (n <= 2) {
ret = -ENOMEM;
goto done;
}
for (i = 0; i < n; i++) {
ret = sscanf(namelist[i]->d_name, "gb_loopback%u", &dev_id);
if (ret != 1)
continue;
if (!is_loopback_device(t->sysfs_prefix, namelist[i]->d_name))
continue;
if (t->device_count == MAX_NUM_DEVICES) {
fprintf(stderr, "max number of devices reached!\n");
break;
}
d = &t->devices[t->device_count++];
snprintf(d->name, MAX_STR_LEN, "gb_loopback%u", dev_id);
snprintf(d->sysfs_entry, MAX_SYSFS_PATH, "%s%s/",
t->sysfs_prefix, d->name);
snprintf(d->debugfs_entry, MAX_SYSFS_PATH, "%sraw_latency_%s",
t->debugfs_prefix, d->name);
if (t->debug)
printf("add %s %s\n", d->sysfs_entry, d->debugfs_entry);
}
ret = 0;
done:
for (i = 0; i < n; i++)
free(namelist[i]);
free(namelist);
baddir:
return ret;
}
static int open_poll_files(struct loopback_test *t)
{
struct loopback_device *dev;
char buf[MAX_SYSFS_PATH + MAX_STR_LEN];
char dummy;
int fds_idx = 0;
int i;
for (i = 0; i < t->device_count; i++) {
dev = &t->devices[i];
if (!device_enabled(t, i))
continue;
snprintf(buf, sizeof(buf), "%s%s", dev->sysfs_entry, "iteration_count");
t->fds[fds_idx].fd = open(buf, O_RDONLY);
if (t->fds[fds_idx].fd < 0) {
fprintf(stderr, "Error opening poll file!\n");
goto err;
}
read(t->fds[fds_idx].fd, &dummy, 1);
t->fds[fds_idx].events = POLLERR | POLLPRI;
t->fds[fds_idx].revents = 0;
fds_idx++;
}
t->poll_count = fds_idx;
return 0;
err:
for (i = 0; i < fds_idx; i++)
close(t->fds[i].fd);
return -1;
}
static int close_poll_files(struct loopback_test *t)
{
int i;
for (i = 0; i < t->poll_count; i++)
close(t->fds[i].fd);
return 0;
}
static int is_complete(struct loopback_test *t)
{
int iteration_count;
int i;
for (i = 0; i < t->device_count; i++) {
if (!device_enabled(t, i))
continue;
iteration_count = read_sysfs_int(t->devices[i].sysfs_entry,
"iteration_count");
/* at least one device did not finish yet */
if (iteration_count != t->iteration_max)
return 0;
}
return 1;
}
static void stop_tests(struct loopback_test *t)
{
int i;
for (i = 0; i < t->device_count; i++) {
if (!device_enabled(t, i))
continue;
write_sysfs_val(t->devices[i].sysfs_entry, "type", 0);
}
}
static void handler(int sig) { /* do nothing */ }
static int wait_for_complete(struct loopback_test *t)
{
int number_of_events = 0;
char dummy;
int ret;
int i;
struct timespec *ts = NULL;
struct sigaction sa;
sigset_t mask_old, mask;
sigemptyset(&mask);
sigemptyset(&mask_old);
sigaddset(&mask, SIGINT);
sigprocmask(SIG_BLOCK, &mask, &mask_old);
sa.sa_handler = handler;
sa.sa_flags = 0;
sigemptyset(&sa.sa_mask);
if (sigaction(SIGINT, &sa, NULL) == -1) {
fprintf(stderr, "sigaction error\n");
return -1;
}
if (t->poll_timeout.tv_sec != 0)
ts = &t->poll_timeout;
while (1) {
ret = ppoll(t->fds, t->poll_count, ts, &mask_old);
if (ret <= 0) {
stop_tests(t);
fprintf(stderr, "Poll exit with errno %d\n", errno);
return -1;
}
for (i = 0; i < t->poll_count; i++) {
if (t->fds[i].revents & POLLPRI) {
/* Dummy read to clear the event */
read(t->fds[i].fd, &dummy, 1);
number_of_events++;
}
}
if (number_of_events == t->poll_count)
break;
}
if (!is_complete(t)) {
fprintf(stderr, "Iteration count did not finish!\n");
return -1;
}
return 0;
}
static void prepare_devices(struct loopback_test *t)
{
int i;
/*
* Cancel any running tests on enabled devices. If
* stop_all option is given, stop test on all devices.
*/
for (i = 0; i < t->device_count; i++)
if (t->stop_all || device_enabled(t, i))
write_sysfs_val(t->devices[i].sysfs_entry, "type", 0);
for (i = 0; i < t->device_count; i++) {
if (!device_enabled(t, i))
continue;
write_sysfs_val(t->devices[i].sysfs_entry, "us_wait",
t->us_wait);
/* Set operation size */
write_sysfs_val(t->devices[i].sysfs_entry, "size", t->size);
/* Set iterations */
write_sysfs_val(t->devices[i].sysfs_entry, "iteration_max",
t->iteration_max);
if (t->use_async) {
write_sysfs_val(t->devices[i].sysfs_entry, "async", 1);
write_sysfs_val(t->devices[i].sysfs_entry,
"timeout", t->async_timeout);
write_sysfs_val(t->devices[i].sysfs_entry,
"outstanding_operations_max",
t->async_outstanding_operations);
} else {
write_sysfs_val(t->devices[i].sysfs_entry, "async", 0);
}
}
}
static int start(struct loopback_test *t)
{
int i;
/* the test starts by writing test_id to the type file. */
for (i = 0; i < t->device_count; i++) {
if (!device_enabled(t, i))
continue;
write_sysfs_val(t->devices[i].sysfs_entry, "type", t->test_id);
}
return 0;
}
void loopback_run(struct loopback_test *t)
{
int i;
int ret;
for (i = 0; dict[i].name != NULL; i++) {
if (strstr(dict[i].name, t->test_name))
t->test_id = dict[i].type;
}
if (!t->test_id) {
fprintf(stderr, "invalid test %s\n", t->test_name);
usage();
return;
}
prepare_devices(t);
ret = open_poll_files(t);
if (ret)
goto err;
start(t);
ret = wait_for_complete(t);
close_poll_files(t);
if (ret)
goto err;
get_results(t);
log_results(t);
return;
err:
printf("Error running test\n");
}
static int sanity_check(struct loopback_test *t)
{
int i;
if (t->device_count == 0) {
fprintf(stderr, "No loopback devices found\n");
return -1;
}
for (i = 0; i < MAX_NUM_DEVICES; i++) {
if (!device_enabled(t, i))
continue;
if (t->mask && !strcmp(t->devices[i].name, "")) {
fprintf(stderr, "Bad device mask %x\n", (1 << i));
return -1;
}
}
return 0;
}
int main(int argc, char *argv[])
{
int o, ret;
char *sysfs_prefix = "/sys/class/gb_loopback/";
char *debugfs_prefix = "/sys/kernel/debug/gb_loopback/";
memset(&t, 0, sizeof(t));
while ((o = getopt(argc, argv,
"t:s:i:S:D:m:v::d::r::p::a::l::x::o:O:c:w:z::f::")) != -1) {
switch (o) {
case 't':
snprintf(t.test_name, MAX_STR_LEN, "%s", optarg);
break;
case 's':
t.size = atoi(optarg);
break;
case 'i':
t.iteration_max = atoi(optarg);
break;
case 'S':
snprintf(t.sysfs_prefix, MAX_SYSFS_PREFIX, "%s", optarg);
break;
case 'D':
snprintf(t.debugfs_prefix, MAX_SYSFS_PREFIX, "%s", optarg);
break;
case 'm':
t.mask = atol(optarg);
break;
case 'v':
t.verbose = 1;
break;
case 'd':
t.debug = 1;
break;
case 'r':
t.raw_data_dump = 1;
break;
case 'p':
t.porcelain = 1;
break;
case 'a':
t.aggregate_output = 1;
break;
case 'l':
t.list_devices = 1;
break;
case 'x':
t.use_async = 1;
break;
case 'o':
t.async_timeout = atoi(optarg);
break;
case 'O':
t.poll_timeout.tv_sec = atoi(optarg);
break;
case 'c':
t.async_outstanding_operations = atoi(optarg);
break;
case 'w':
t.us_wait = atoi(optarg);
break;
case 'z':
t.file_output = 1;
break;
case 'f':
t.stop_all = 1;
break;
default:
usage();
return -EINVAL;
}
}
if (!strcmp(t.sysfs_prefix, ""))
snprintf(t.sysfs_prefix, MAX_SYSFS_PREFIX, "%s", sysfs_prefix);
if (!strcmp(t.debugfs_prefix, ""))
snprintf(t.debugfs_prefix, MAX_SYSFS_PREFIX, "%s", debugfs_prefix);
ret = find_loopback_devices(&t);
if (ret)
return ret;
ret = sanity_check(&t);
if (ret)
return ret;
if (t.list_devices) {
show_loopback_devices(&t);
return 0;
}
if (t.test_name[0] == '\0' || t.iteration_max == 0)
usage();
if (t.async_timeout == 0)
t.async_timeout = DEFAULT_ASYNC_TIMEOUT;
loopback_run(&t);
return 0;
}

2
drivers/staging/iio/resolver/ad2s1210.c
View File

@ -102,7 +102,7 @@ struct ad2s1210_state {
static const int ad2s1210_mode_vals[4][2] = {
[MOD_POS] = { 0, 0 },
[MOD_VEL] = { 0, 1 },
[MOD_CONFIG] = { 1, 0 },
[MOD_CONFIG] = { 1, 1 },
};
static inline void ad2s1210_set_mode(enum ad2s1210_mode mode,

5
drivers/staging/ks7010/ks_hostif.c
View File

@ -75,9 +75,8 @@ static void ks_wlan_hw_wakeup_task(struct work_struct *work)
if (ps_status == PS_SNOOZE) {
ks_wlan_hw_wakeup_request(priv);
time_left = wait_for_completion_interruptible_timeout(
&priv->psstatus.wakeup_wait,
msecs_to_jiffies(20));
time_left = wait_for_completion_interruptible_timeout(&priv->psstatus.wakeup_wait,
msecs_to_jiffies(20));
if (time_left <= 0) {
netdev_dbg(priv->net_dev, "wake up timeout or interrupted !!!\n");
schedule_work(&priv->wakeup_work);

15
drivers/staging/most/dim2/dim2.c
View File

@ -108,7 +108,10 @@ struct dim2_platform_data {
u8 fcnt;
};
#define iface_to_hdm(iface) container_of(iface, struct dim2_hdm, most_iface)
static inline struct dim2_hdm *iface_to_hdm(struct most_interface *iface)
{
return container_of(iface, struct dim2_hdm, most_iface);
}
/* Macro to identify a network status message */
#define PACKET_IS_NET_INFO(p) \
@ -775,8 +778,7 @@ static int dim2_probe(struct platform_device *pdev)
goto err_free_dev;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
dev->io_base = devm_ioremap_resource(&pdev->dev, res);
dev->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(dev->io_base)) {
ret = PTR_ERR(dev->io_base);
goto err_free_dev;
@ -906,13 +908,11 @@ err_free_dev:
*
* Unregister the interface from mostcore
*/
static int dim2_remove(struct platform_device *pdev)
static void dim2_remove(struct platform_device *pdev)
{
struct dim2_hdm *dev = platform_get_drvdata(pdev);
most_deregister_interface(&dev->most_iface);
return 0;
}
/* platform specific functions [[ */
@ -987,7 +987,6 @@ static int rcar_gen2_enable(struct platform_device *pdev)
writel(0x04, dev->io_base + 0x600);
}
/* BBCR = 0b11 */
writel(0x03, dev->io_base + 0x500);
writel(0x0002FF02, dev->io_base + 0x508);
@ -1091,7 +1090,7 @@ MODULE_DEVICE_TABLE(of, dim2_of_match);
static struct platform_driver dim2_driver = {
.probe = dim2_probe,
.remove = dim2_remove,
.remove_new = dim2_remove,
.driver = {
.name = "hdm_dim2",
.of_match_table = dim2_of_match,

5
drivers/staging/most/dim2/hal.c
View File

@ -346,9 +346,8 @@ static void dim2_clear_ctram(void)
dim2_clear_ctr(ctr_addr);
}
static void dim2_configure_channel(
u8 ch_addr, u8 type, u8 is_tx, u16 dbr_address, u16 hw_buffer_size,
u16 packet_length)
static void dim2_configure_channel(u8 ch_addr, u8 type, u8 is_tx, u16 dbr_address,
u16 hw_buffer_size, u16 packet_length)
{
dim2_configure_cdt(ch_addr, dbr_address, hw_buffer_size, packet_length);
dim2_configure_cat(MLB_CAT, ch_addr, type, is_tx ? 1 : 0);

5
drivers/staging/most/i2c/i2c.c
View File

@ -44,7 +44,10 @@ struct hdm_i2c {
char name[64];
};
#define to_hdm(iface) container_of(iface, struct hdm_i2c, most_iface)
static inline struct hdm_i2c *to_hdm(struct most_interface *iface)
{
return container_of(iface, struct hdm_i2c, most_iface);
}
static irqreturn_t most_irq_handler(int, void *);
static void pending_rx_work(struct work_struct *);

3
drivers/staging/most/video/video.c
View File

@ -365,8 +365,7 @@ static const struct video_device comp_videodev_template = {
/**************************************************************************/
static struct most_video_dev *get_comp_dev(
struct most_interface *iface, int channel_idx)
static struct most_video_dev *get_comp_dev(struct most_interface *iface, int channel_idx)
{
struct most_video_dev *mdev;
unsigned long flags;

6
drivers/staging/nvec/nvec.c
View File

@ -882,7 +882,7 @@ static int tegra_nvec_probe(struct platform_device *pdev)
return 0;
}
static int tegra_nvec_remove(struct platform_device *pdev)
static void tegra_nvec_remove(struct platform_device *pdev)
{
struct nvec_chip *nvec = platform_get_drvdata(pdev);
@ -893,8 +893,6 @@ static int tegra_nvec_remove(struct platform_device *pdev)
cancel_work_sync(&nvec->tx_work);
/* FIXME: needs check whether nvec is responsible for power off */
pm_power_off = NULL;
return 0;
}
#ifdef CONFIG_PM_SLEEP
@ -942,7 +940,7 @@ MODULE_DEVICE_TABLE(of, nvidia_nvec_of_match);
static struct platform_driver nvec_device_driver = {
.probe = tegra_nvec_probe,
.remove = tegra_nvec_remove,
.remove_new = tegra_nvec_remove,
.driver = {
.name = "nvec",
.pm = &nvec_pm_ops,

6
drivers/staging/nvec/nvec_kbd.c
View File

@ -161,7 +161,7 @@ static int nvec_kbd_probe(struct platform_device *pdev)
return 0;
}
static int nvec_kbd_remove(struct platform_device *pdev)
static void nvec_kbd_remove(struct platform_device *pdev)
{
struct nvec_chip *nvec = dev_get_drvdata(pdev->dev.parent);
char disable_kbd[] = { NVEC_KBD, DISABLE_KBD },
@ -170,13 +170,11 @@ static int nvec_kbd_remove(struct platform_device *pdev)
nvec_write_async(nvec, uncnfg_wake_key_reporting, 3);
nvec_write_async(nvec, disable_kbd, 2);
nvec_unregister_notifier(nvec, &keys_dev.notifier);
return 0;
}
static struct platform_driver nvec_kbd_driver = {
.probe = nvec_kbd_probe,
.remove = nvec_kbd_remove,
.remove_new = nvec_kbd_remove,
.driver = {
.name = "nvec-kbd",
},

5
drivers/staging/nvec/nvec_paz00.c
View File

@ -14,9 +14,6 @@
#include <linux/platform_device.h>
#include "nvec.h"
#define to_nvec_led(led_cdev) \
container_of(led_cdev, struct nvec_led, cdev)
#define NVEC_LED_REQ {'\x0d', '\x10', '\x45', '\x10', '\x00'}
#define NVEC_LED_MAX 8
@ -29,7 +26,7 @@ struct nvec_led {
static void nvec_led_brightness_set(struct led_classdev *led_cdev,
enum led_brightness value)
{
struct nvec_led *led = to_nvec_led(led_cdev);
struct nvec_led *led = container_of(led_cdev, struct nvec_led, cdev);
unsigned char buf[] = NVEC_LED_REQ;
buf[4] = value;

6
drivers/staging/nvec/nvec_power.c
View File

@ -416,7 +416,7 @@ static int nvec_power_probe(struct platform_device *pdev)
return PTR_ERR_OR_ZERO(*psy);
}
static int nvec_power_remove(struct platform_device *pdev)
static void nvec_power_remove(struct platform_device *pdev)
{
struct nvec_power *power = platform_get_drvdata(pdev);
@ -429,13 +429,11 @@ static int nvec_power_remove(struct platform_device *pdev)
case BAT:
power_supply_unregister(nvec_bat_psy);
}
return 0;
}
static struct platform_driver nvec_power_driver = {
.probe = nvec_power_probe,
.remove = nvec_power_remove,
.remove_new = nvec_power_remove,
.driver = {
.name = "nvec-power",
}

6
drivers/staging/nvec/nvec_ps2.c
View File

@ -125,7 +125,7 @@ static int nvec_mouse_probe(struct platform_device *pdev)
return 0;
}
static int nvec_mouse_remove(struct platform_device *pdev)
static void nvec_mouse_remove(struct platform_device *pdev)
{
struct nvec_chip *nvec = dev_get_drvdata(pdev->dev.parent);
@ -133,8 +133,6 @@ static int nvec_mouse_remove(struct platform_device *pdev)
ps2_stopstreaming(ps2_dev.ser_dev);
nvec_unregister_notifier(nvec, &ps2_dev.notifier);
serio_unregister_port(ps2_dev.ser_dev);
return 0;
}
#ifdef CONFIG_PM_SLEEP
@ -166,7 +164,7 @@ static SIMPLE_DEV_PM_OPS(nvec_mouse_pm_ops, nvec_mouse_suspend,
static struct platform_driver nvec_mouse_driver = {
.probe = nvec_mouse_probe,
.remove = nvec_mouse_remove,
.remove_new = nvec_mouse_remove,
.driver = {
.name = "nvec-mouse",
.pm = &nvec_mouse_pm_ops,

5
drivers/staging/octeon/ethernet.c
View File

@ -924,7 +924,7 @@ static int cvm_oct_probe(struct platform_device *pdev)
return 0;
}
static int cvm_oct_remove(struct platform_device *pdev)
static void cvm_oct_remove(struct platform_device *pdev)
{
int port;
@ -965,7 +965,6 @@ static int cvm_oct_remove(struct platform_device *pdev)
if (CVMX_FPA_OUTPUT_BUFFER_POOL != CVMX_FPA_PACKET_POOL)
cvm_oct_mem_empty_fpa(CVMX_FPA_OUTPUT_BUFFER_POOL,
CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE, 128);
return 0;
}
static const struct of_device_id cvm_oct_match[] = {
@ -978,7 +977,7 @@ MODULE_DEVICE_TABLE(of, cvm_oct_match);
static struct platform_driver cvm_oct_driver = {
.probe = cvm_oct_probe,
.remove = cvm_oct_remove,
.remove_new = cvm_oct_remove,
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = cvm_oct_match,

4
drivers/staging/octeon/octeon-stubs.h
View File

@ -1372,9 +1372,7 @@ static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr,
int32_t value)
{ }
static inline union cvmx_gmxx_rxx_rx_inbnd cvmx_spi4000_check_speed(
int interface,
int port)
static inline union cvmx_gmxx_rxx_rx_inbnd cvmx_spi4000_check_speed(int interface, int port)
{
union cvmx_gmxx_rxx_rx_inbnd r;

35
drivers/staging/qlge/qlge_dbg.c
View File

@ -351,26 +351,23 @@ static int qlge_get_xgmac_regs(struct qlge_adapter *qdev, u32 *buf,
/* We're reading 400 xgmac registers, but we filter out
* several locations that are non-responsive to reads.
*/
if ((i == 0x00000114) ||
(i == 0x00000118) ||
(i == 0x0000013c) ||
(i == 0x00000140) ||
(i > 0x00000150 && i < 0x000001fc) ||
(i > 0x00000278 && i < 0x000002a0) ||
(i > 0x000002c0 && i < 0x000002cf) ||
(i > 0x000002dc && i < 0x000002f0) ||
(i > 0x000003c8 && i < 0x00000400) ||
(i > 0x00000400 && i < 0x00000410) ||
(i > 0x00000410 && i < 0x00000420) ||
(i > 0x00000420 && i < 0x00000430) ||
(i > 0x00000430 && i < 0x00000440) ||
(i > 0x00000440 && i < 0x00000450) ||
(i > 0x00000450 && i < 0x00000500) ||
(i > 0x0000054c && i < 0x00000568) ||
(i > 0x000005c8 && i < 0x00000600)) {
if ((i == 0x00000114) || (i == 0x00000118) ||
(i == 0x0000013c) || (i == 0x00000140) ||
(i > 0x00000150 && i < 0x000001fc) ||
(i > 0x00000278 && i < 0x000002a0) ||
(i > 0x000002c0 && i < 0x000002cf) ||
(i > 0x000002dc && i < 0x000002f0) ||
(i > 0x000003c8 && i < 0x00000400) ||
(i > 0x00000400 && i < 0x00000410) ||
(i > 0x00000410 && i < 0x00000420) ||
(i > 0x00000420 && i < 0x00000430) ||
(i > 0x00000430 && i < 0x00000440) ||
(i > 0x00000440 && i < 0x00000450) ||
(i > 0x00000450 && i < 0x00000500) ||
(i > 0x0000054c && i < 0x00000568) ||
(i > 0x000005c8 && i < 0x00000600)) {
if (other_function)
status =
qlge_read_other_func_xgmac_reg(qdev, i, buf);
status = qlge_read_other_func_xgmac_reg(qdev, i, buf);
else
status = qlge_read_xgmac_reg(qdev, i, buf);

2
drivers/staging/rtl8192e/rtl8192e/Makefile
View File

@ -4,7 +4,7 @@ r8192e_pci-objs := \
r8192E_phy.o \
r8192E_firmware.o \
r8192E_cmdpkt.o \
r8192E_hwimg.o \
table.o \
r8190P_rtl8256.o \
rtl_cam.o \
rtl_core.o \

11
drivers/staging/rtl8192e/rtl8192e/r8190P_def.h
View File

@ -103,21 +103,10 @@ enum rf_optype {
struct bb_reg_definition {
u32 rfintfs;
u32 rfintfi;
u32 rfintfo;
u32 rfintfe;
u32 rf3wireOffset;
u32 rfLSSI_Select;
u32 rfTxGainStage;
u32 rfHSSIPara1;
u32 rfHSSIPara2;
u32 rfSwitchControl;
u32 rfAGCControl1;
u32 rfAGCControl2;
u32 rfRxIQImbalance;
u32 rfRxAFE;
u32 rfTxIQImbalance;
u32 rfTxAFE;
u32 rfLSSIReadBack;
u32 rfLSSIReadBackPi;
};

10
drivers/staging/rtl8192e/rtl8192e/r8190P_rtl8256.c
View File

@ -22,9 +22,6 @@ void rtl92e_set_bandwidth(struct net_device *dev,
}
for (eRFPath = 0; eRFPath < priv->num_total_rf_path; eRFPath++) {
if (!rtl92e_is_legal_rf_path(dev, eRFPath))
continue;
switch (bandwidth) {
case HT_CHANNEL_WIDTH_20:
rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
@ -67,19 +64,14 @@ bool rtl92e_config_rf(struct net_device *dev)
for (eRFPath = (enum rf90_radio_path)RF90_PATH_A;
eRFPath < priv->num_total_rf_path; eRFPath++) {
if (!rtl92e_is_legal_rf_path(dev, eRFPath))
continue;
pPhyReg = &priv->phy_reg_def[eRFPath];
switch (eRFPath) {
case RF90_PATH_A:
case RF90_PATH_C:
u4RegValue = rtl92e_get_bb_reg(dev, pPhyReg->rfintfs,
bRFSI_RFENV);
break;
case RF90_PATH_B:
case RF90_PATH_D:
u4RegValue = rtl92e_get_bb_reg(dev, pPhyReg->rfintfs,
bRFSI_RFENV<<16);
break;
@ -120,12 +112,10 @@ bool rtl92e_config_rf(struct net_device *dev)
switch (eRFPath) {
case RF90_PATH_A:
case RF90_PATH_C:
rtl92e_set_bb_reg(dev, pPhyReg->rfintfs, bRFSI_RFENV,
u4RegValue);
break;
case RF90_PATH_B:
case RF90_PATH_D:
rtl92e_set_bb_reg(dev, pPhyReg->rfintfs,
bRFSI_RFENV<<16, u4RegValue);
break;

82
drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c
View File

@ -343,18 +343,11 @@ static void _rtl92e_read_eeprom_info(struct net_device *dev)
else
priv->tx_pwr_data_read_from_eeprom = false;
priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
if (priv->card_8192_version > VERSION_8190_BD) {
if (!priv->autoload_fail_flag) {
tempval = (rtl92e_eeprom_read(dev,
(EEPROM_RFInd_PowerDiff >> 1))) & 0xff;
priv->eeprom_legacy_ht_tx_pwr_diff = tempval & 0xf;
if (tempval&0x80)
priv->rf_type = RF_1T2R;
else
priv->rf_type = RF_2T4R;
} else {
priv->eeprom_legacy_ht_tx_pwr_diff = 0x04;
}
@ -433,26 +426,12 @@ static void _rtl92e_read_eeprom_info(struct net_device *dev)
rtl92e_init_adaptive_rate(dev);
priv->rf_chip = RF_8256;
if (priv->reg_chnl_plan == 0xf)
priv->chnl_plan = priv->eeprom_chnl_plan;
else
priv->chnl_plan = priv->reg_chnl_plan;
if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304)
priv->customer_id = RT_CID_DLINK;
switch (priv->eeprom_customer_id) {
case EEPROM_CID_DEFAULT:
priv->customer_id = RT_CID_DEFAULT;
break;
case EEPROM_CID_CAMEO:
priv->customer_id = RT_CID_819x_CAMEO;
break;
case EEPROM_CID_RUNTOP:
priv->customer_id = RT_CID_819x_RUNTOP;
break;
case EEPROM_CID_NetCore:
priv->customer_id = RT_CID_819X_NETCORE;
break;
@ -463,20 +442,6 @@ static void _rtl92e_read_eeprom_info(struct net_device *dev)
else
priv->chnl_plan = 0x0;
break;
case EEPROM_CID_Nettronix:
priv->customer_id = RT_CID_Nettronix;
break;
case EEPROM_CID_Pronet:
priv->customer_id = RT_CID_PRONET;
break;
case EEPROM_CID_DLINK:
priv->customer_id = RT_CID_DLINK;
break;
case EEPROM_CID_WHQL:
break;
default:
break;
}
if (priv->chnl_plan > CHANNEL_PLAN_LEN - 1)
@ -512,16 +477,6 @@ static void _rtl92e_hwconfig(struct net_device *dev)
regRATR = RATE_ALL_CCK;
regRRSR = RATE_ALL_CCK;
break;
case WIRELESS_MODE_A:
regBwOpMode = BW_OPMODE_5G | BW_OPMODE_20MHZ;
regRATR = RATE_ALL_OFDM_AG;
regRRSR = RATE_ALL_OFDM_AG;
break;
case WIRELESS_MODE_G:
regBwOpMode = BW_OPMODE_20MHZ;
regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
break;
case WIRELESS_MODE_AUTO:
case WIRELESS_MODE_N_24G:
regBwOpMode = BW_OPMODE_20MHZ;
@ -529,12 +484,7 @@ static void _rtl92e_hwconfig(struct net_device *dev)
RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
break;
case WIRELESS_MODE_N_5G:
regBwOpMode = BW_OPMODE_5G;
regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS |
RATE_ALL_OFDM_2SS;
regRRSR = RATE_ALL_OFDM_AG;
break;
case WIRELESS_MODE_G:
default:
regBwOpMode = BW_OPMODE_20MHZ;
regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
@ -547,8 +497,7 @@ static void _rtl92e_hwconfig(struct net_device *dev)
u32 ratr_value;
ratr_value = regRATR;
if (priv->rf_type == RF_1T2R)
ratr_value &= ~(RATE_ALL_OFDM_2SS);
ratr_value &= ~(RATE_ALL_OFDM_2SS);
rtl92e_writel(dev, RATR0, ratr_value);
rtl92e_writeb(dev, UFWP, 1);
}
@ -701,7 +650,7 @@ start:
}
if (priv->rst_progress == RESET_TYPE_NORESET) {
rtStatus = rtl92e_config_phy(dev);
rtStatus = rtl92e_config_rf(dev);
if (!rtStatus) {
netdev_info(dev, "RF Config failed\n");
return rtStatus;
@ -806,7 +755,7 @@ void rtl92e_link_change(struct net_device *dev)
if (ieee->state == RTLLIB_LINKED) {
_rtl92e_net_update(dev);
priv->ops->update_ratr_table(dev);
rtl92e_update_ratr_table(dev);
if ((ieee->pairwise_key_type == KEY_TYPE_WEP40) ||
(ieee->pairwise_key_type == KEY_TYPE_WEP104))
rtl92e_enable_hw_security_config(dev);
@ -1515,9 +1464,7 @@ static void _rtl92e_process_phyinfo(struct r8192_priv *priv, u8 *buffer,
return;
if (!prev_st->bIsCCK && prev_st->bPacketToSelf) {
for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) {
if (!rtl92e_is_legal_rf_path(priv->rtllib->dev, rfpath))
continue;
for (rfpath = RF90_PATH_A; rfpath < priv->num_total_rf_path; rfpath++) {
if (priv->stats.rx_rssi_percentage[rfpath] == 0) {
priv->stats.rx_rssi_percentage[rfpath] =
prev_st->RxMIMOSignalStrength[rfpath];
@ -1895,14 +1842,10 @@ void rtl92e_update_ratr_table(struct net_device *dev)
break;
case IEEE_N_24G:
case IEEE_N_5G:
if (ieee->ht_info->peer_mimo_ps == 0) {
if (ieee->ht_info->peer_mimo_ps == 0)
ratr_value &= 0x0007F007;
} else {
if (priv->rf_type == RF_1T2R)
ratr_value &= 0x000FF007;
else
ratr_value &= 0x0F81F007;
}
else
ratr_value &= 0x000FF007;
break;
default:
break;
@ -1970,15 +1913,6 @@ void rtl92e_disable_irq(struct net_device *dev)
priv->irq_enabled = 0;
}
void rtl92e_clear_irq(struct net_device *dev)
{
u32 tmp;
tmp = rtl92e_readl(dev, ISR);
rtl92e_writel(dev, ISR, tmp);
}
void rtl92e_enable_rx(struct net_device *dev)
{
struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);

1
drivers/staging/rtl8192e/rtl8192e/r8192E_dev.h
View File

@ -18,7 +18,6 @@ void rtl92e_enable_rx(struct net_device *dev);
void rtl92e_enable_tx(struct net_device *dev);
void rtl92e_enable_irq(struct net_device *dev);
void rtl92e_disable_irq(struct net_device *dev);
void rtl92e_clear_irq(struct net_device *dev);
void rtl92e_init_variables(struct net_device *dev);
void rtl92e_start_beacon(struct net_device *dev);
void rtl92e_set_reg(struct net_device *dev, u8 variable, u8 *val);

2
drivers/staging/rtl8192e/rtl8192e/r8192E_firmware.c
View File

@ -6,7 +6,7 @@
*/
#include "rtl_core.h"
#include "r8192E_hw.h"
#include "r8192E_hwimg.h"
#include "table.h"
#include "r8192E_firmware.h"
#include "r8192E_cmdpkt.h"
#include <linux/firmware.h>

7
drivers/staging/rtl8192e/rtl8192e/r8192E_hw.h
View File

@ -30,15 +30,8 @@ enum baseband_config {
#define EEPROM_TxPwIndex_CCK 0x2C
#define EEPROM_TxPwIndex_OFDM_24G 0x3A
#define EEPROM_CID_DEFAULT 0x0
#define EEPROM_CID_CAMEO 0x1
#define EEPROM_CID_RUNTOP 0x2
#define EEPROM_CID_TOSHIBA 0x4
#define EEPROM_CID_NetCore 0x5
#define EEPROM_CID_Nettronix 0x6
#define EEPROM_CID_Pronet 0x7
#define EEPROM_CID_DLINK 0x8
#define EEPROM_CID_WHQL 0xFE
enum _RTL8192PCI_HW {
MAC0 = 0x000,
MAC4 = 0x004,

33
drivers/staging/rtl8192e/rtl8192e/r8192E_hwimg.h
View File

@ -1,33 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
*
* Contact Information: wlanfae <wlanfae@realtek.com>
*/
#ifndef __INC_HAL8192PciE_FW_IMG_H
#define __INC_HAL8192PciE_FW_IMG_H
/*Created on 2008/11/18, 3: 7*/
#include <linux/types.h>
#define PHY_REGArrayLengthPciE 1
extern u32 Rtl8192PciEPHY_REGArray[PHY_REGArrayLengthPciE];
#define PHY_REG_1T2RArrayLengthPciE 296
extern u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLengthPciE];
#define RadioA_ArrayLengthPciE 246
extern u32 Rtl8192PciERadioA_Array[RadioA_ArrayLengthPciE];
#define RadioB_ArrayLengthPciE 78
extern u32 Rtl8192PciERadioB_Array[RadioB_ArrayLengthPciE];
#define RadioC_ArrayLengthPciE 2
extern u32 Rtl8192PciERadioC_Array[RadioC_ArrayLengthPciE];
#define RadioD_ArrayLengthPciE 2
extern u32 Rtl8192PciERadioD_Array[RadioD_ArrayLengthPciE];
#define MACPHY_ArrayLengthPciE 18
extern u32 Rtl8192PciEMACPHY_Array[MACPHY_ArrayLengthPciE];
#define MACPHY_Array_PGLengthPciE 30
extern u32 Rtl8192PciEMACPHY_Array_PG[MACPHY_Array_PGLengthPciE];
#define AGCTAB_ArrayLengthPciE 384
extern u32 Rtl8192PciEAGCTAB_Array[AGCTAB_ArrayLengthPciE];
#endif

613
drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c
View File

@ -12,25 +12,7 @@
#include "r8192E_phy.h"
#include "rtl_dm.h"
#include "r8192E_hwimg.h"
static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
0,
0x085c,
0x08dc,
0x095c,
0x09dc,
0x0a5c,
0x0adc,
0x0b5c,
0x0bdc,
0x0c5c,
0x0cdc,
0x0d5c,
0x0ddc,
0x0e5c,
0x0f72,
};
#include "table.h"
/*************************Define local function prototype**********************/
@ -47,22 +29,6 @@ static u32 _rtl92e_calculate_bit_shift(u32 dwBitMask)
return ffs(dwBitMask) - 1;
}
u8 rtl92e_is_legal_rf_path(struct net_device *dev, u32 eRFPath)
{
u8 ret = 1;
struct r8192_priv *priv = rtllib_priv(dev);
if (priv->rf_type == RF_2T4R)
ret = 0;
else if (priv->rf_type == RF_1T2R) {
if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
ret = 1;
else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
ret = 0;
}
return ret;
}
void rtl92e_set_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask,
u32 dwData)
{
@ -98,24 +64,20 @@ static u32 _rtl92e_phy_rf_read(struct net_device *dev,
Offset &= 0x3f;
if (priv->rf_chip == RF_8256) {
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
if (Offset >= 31) {
priv->rf_reg_0value[eRFPath] |= 0x140;
rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
bMaskDWord,
(priv->rf_reg_0value[eRFPath] << 16));
NewOffset = Offset - 30;
} else if (Offset >= 16) {
priv->rf_reg_0value[eRFPath] |= 0x100;
priv->rf_reg_0value[eRFPath] &= (~0x40);
rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
bMaskDWord,
(priv->rf_reg_0value[eRFPath] << 16));
NewOffset = Offset - 15;
} else
NewOffset = Offset;
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
if (Offset >= 31) {
priv->rf_reg_0value[eRFPath] |= 0x140;
rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
bMaskDWord,
(priv->rf_reg_0value[eRFPath] << 16));
NewOffset = Offset - 30;
} else if (Offset >= 16) {
priv->rf_reg_0value[eRFPath] |= 0x100;
priv->rf_reg_0value[eRFPath] &= (~0x40);
rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
bMaskDWord,
(priv->rf_reg_0value[eRFPath] << 16));
NewOffset = Offset - 15;
} else {
NewOffset = Offset;
}
@ -129,15 +91,12 @@ static u32 _rtl92e_phy_rf_read(struct net_device *dev,
ret = rtl92e_get_bb_reg(dev, pPhyReg->rfLSSIReadBack,
bLSSIReadBackData);
if (priv->rf_chip == RF_8256) {
priv->rf_reg_0value[eRFPath] &= 0xebf;
priv->rf_reg_0value[eRFPath] &= 0xebf;
rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
(priv->rf_reg_0value[eRFPath] << 16));
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
}
rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
(priv->rf_reg_0value[eRFPath] << 16));
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
return ret;
@ -152,24 +111,22 @@ static void _rtl92e_phy_rf_write(struct net_device *dev,
struct bb_reg_definition *pPhyReg = &priv->phy_reg_def[eRFPath];
Offset &= 0x3f;
if (priv->rf_chip == RF_8256) {
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
if (Offset >= 31) {
priv->rf_reg_0value[eRFPath] |= 0x140;
rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
bMaskDWord,
(priv->rf_reg_0value[eRFPath] << 16));
NewOffset = Offset - 30;
} else if (Offset >= 16) {
priv->rf_reg_0value[eRFPath] |= 0x100;
priv->rf_reg_0value[eRFPath] &= (~0x40);
rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
bMaskDWord,
(priv->rf_reg_0value[eRFPath] << 16));
NewOffset = Offset - 15;
} else
NewOffset = Offset;
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
if (Offset >= 31) {
priv->rf_reg_0value[eRFPath] |= 0x140;
rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
bMaskDWord,
(priv->rf_reg_0value[eRFPath] << 16));
NewOffset = Offset - 30;
} else if (Offset >= 16) {
priv->rf_reg_0value[eRFPath] |= 0x100;
priv->rf_reg_0value[eRFPath] &= (~0x40);
rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
bMaskDWord,
(priv->rf_reg_0value[eRFPath] << 16));
NewOffset = Offset - 15;
} else {
NewOffset = Offset;
}
@ -181,15 +138,13 @@ static void _rtl92e_phy_rf_write(struct net_device *dev,
if (Offset == 0x0)
priv->rf_reg_0value[eRFPath] = Data;
if (priv->rf_chip == RF_8256) {
if (Offset != 0) {
priv->rf_reg_0value[eRFPath] &= 0xebf;
rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
bMaskDWord,
(priv->rf_reg_0value[eRFPath] << 16));
}
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
if (Offset != 0) {
priv->rf_reg_0value[eRFPath] &= 0xebf;
rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
bMaskDWord,
(priv->rf_reg_0value[eRFPath] << 16));
}
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
}
void rtl92e_set_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath,
@ -198,8 +153,6 @@ void rtl92e_set_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath,
struct r8192_priv *priv = rtllib_priv(dev);
u32 Original_Value, BitShift, New_Value;
if (!rtl92e_is_legal_rf_path(dev, eRFPath))
return;
if (priv->rtllib->rf_power_state != rf_on && !priv->being_init_adapter)
return;
@ -235,8 +188,6 @@ u32 rtl92e_get_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath,
u32 Original_Value, Readback_Value, BitShift;
struct r8192_priv *priv = rtllib_priv(dev);
if (!rtl92e_is_legal_rf_path(dev, eRFPath))
return 0;
if (priv->rtllib->rf_power_state != rf_on && !priv->being_init_adapter)
return 0;
mutex_lock(&priv->rf_mutex);
@ -307,12 +258,12 @@ void rtl92e_config_mac(struct net_device *dev)
struct r8192_priv *priv = rtllib_priv(dev);
if (priv->tx_pwr_data_read_from_eeprom) {
dwArrayLen = MACPHY_Array_PGLength;
pdwArray = Rtl819XMACPHY_Array_PG;
dwArrayLen = RTL8192E_MACPHY_ARR_PG_LEN;
pdwArray = RTL8192E_MACPHY_ARR_PG;
} else {
dwArrayLen = MACPHY_ArrayLength;
pdwArray = Rtl819XMACPHY_Array;
dwArrayLen = RTL8192E_MACPHY_ARR_LEN;
pdwArray = RTL8192E_MACPHY_ARR;
}
for (i = 0; i < dwArrayLen; i += 3) {
if (pdwArray[i] == 0x318)
@ -330,17 +281,11 @@ static void _rtl92e_phy_config_bb(struct net_device *dev, u8 ConfigType)
u32 *Rtl819XPHY_REGArray_Table = NULL;
u32 *Rtl819XAGCTAB_Array_Table = NULL;
u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
struct r8192_priv *priv = rtllib_priv(dev);
AGCTAB_ArrayLen = AGCTAB_ArrayLength;
Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
if (priv->rf_type == RF_2T4R) {
PHY_REGArrayLen = PHY_REGArrayLength;
Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
} else if (priv->rf_type == RF_1T2R) {
PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
}
AGCTAB_ArrayLen = RTL8192E_AGCTAB_ARR_LEN;
Rtl819XAGCTAB_Array_Table = RTL8192E_AGCTAB_ARR;
PHY_REGArrayLen = RTL8192E_PHY_REG_1T2R_ARR_LEN;
Rtl819XPHY_REGArray_Table = RTL8192E_PHY_REG_1T2R_ARR;
if (ConfigType == BB_CONFIG_PHY_REG) {
for (i = 0; i < PHY_REGArrayLen; i += 2) {
@ -363,89 +308,21 @@ static void _rtl92e_init_bb_rf_reg_def(struct net_device *dev)
priv->phy_reg_def[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
priv->phy_reg_def[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
priv->phy_reg_def[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
priv->phy_reg_def[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
priv->phy_reg_def[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
priv->phy_reg_def[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
priv->phy_reg_def[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
priv->phy_reg_def[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
priv->phy_reg_def[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
priv->phy_reg_def[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
priv->phy_reg_def[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
priv->phy_reg_def[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
priv->phy_reg_def[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
priv->phy_reg_def[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
priv->phy_reg_def[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
priv->phy_reg_def[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
priv->phy_reg_def[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
priv->phy_reg_def[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
priv->phy_reg_def[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
priv->phy_reg_def[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
priv->phy_reg_def[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
priv->phy_reg_def[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
priv->phy_reg_def[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
priv->phy_reg_def[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
priv->phy_reg_def[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
priv->phy_reg_def[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
priv->phy_reg_def[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
priv->phy_reg_def[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
priv->phy_reg_def[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
priv->phy_reg_def[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
priv->phy_reg_def[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
priv->phy_reg_def[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
priv->phy_reg_def[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
priv->phy_reg_def[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
priv->phy_reg_def[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
priv->phy_reg_def[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
priv->phy_reg_def[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
priv->phy_reg_def[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
priv->phy_reg_def[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
priv->phy_reg_def[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
priv->phy_reg_def[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
priv->phy_reg_def[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
priv->phy_reg_def[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
priv->phy_reg_def[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
priv->phy_reg_def[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
priv->phy_reg_def[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
priv->phy_reg_def[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
priv->phy_reg_def[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
priv->phy_reg_def[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
priv->phy_reg_def[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
priv->phy_reg_def[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
priv->phy_reg_def[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
priv->phy_reg_def[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
priv->phy_reg_def[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
priv->phy_reg_def[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
priv->phy_reg_def[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
priv->phy_reg_def[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
priv->phy_reg_def[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
priv->phy_reg_def[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
priv->phy_reg_def[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
priv->phy_reg_def[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
priv->phy_reg_def[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
priv->phy_reg_def[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
priv->phy_reg_def[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
priv->phy_reg_def[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
priv->phy_reg_def[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
priv->phy_reg_def[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
priv->phy_reg_def[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
}
bool rtl92e_check_bb_and_rf(struct net_device *dev, enum hw90_block CheckBlock,
@ -534,12 +411,7 @@ static bool _rtl92e_bb_config_para_file(struct net_device *dev)
_rtl92e_phy_config_bb(dev, BB_CONFIG_AGC_TAB);
if (priv->ic_cut > VERSION_8190_BD) {
if (priv->rf_type == RF_2T4R)
dwRegValue = priv->antenna_tx_pwr_diff[2] << 8 |
priv->antenna_tx_pwr_diff[1] << 4 |
priv->antenna_tx_pwr_diff[0];
else
dwRegValue = 0x0;
dwRegValue = 0x0;
rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage,
(bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
@ -590,53 +462,10 @@ void rtl92e_set_tx_power(struct net_device *dev, u8 channel)
if (priv->epromtype == EEPROM_93C46) {
powerlevel = priv->tx_pwr_level_cck[channel - 1];
powerlevelOFDM24G = priv->tx_pwr_level_ofdm_24g[channel - 1];
} else if (priv->epromtype == EEPROM_93C56) {
if (priv->rf_type == RF_2T4R) {
priv->antenna_tx_pwr_diff[2] = 0;
priv->antenna_tx_pwr_diff[1] = 0;
priv->antenna_tx_pwr_diff[0] = 0;
rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage,
(bXBTxAGC | bXCTxAGC | bXDTxAGC), 0);
}
}
switch (priv->rf_chip) {
case RF_8225:
break;
case RF_8256:
rtl92e_set_cck_tx_power(dev, powerlevel);
rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G);
break;
case RF_8258:
break;
default:
netdev_err(dev, "Invalid RF Chip ID.\n");
break;
}
}
bool rtl92e_config_phy(struct net_device *dev)
{
struct r8192_priv *priv = rtllib_priv(dev);
bool rtStatus = true;
switch (priv->rf_chip) {
case RF_8225:
break;
case RF_8256:
rtStatus = rtl92e_config_rf(dev);
break;
case RF_8258:
break;
case RF_PSEUDO_11N:
break;
default:
netdev_err(dev, "Invalid RF Chip ID.\n");
break;
}
return rtStatus;
rtl92e_set_cck_tx_power(dev, powerlevel);
rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G);
}
u8 rtl92e_config_rf_path(struct net_device *dev, enum rf90_radio_path eRFPath)
@ -646,50 +475,26 @@ u8 rtl92e_config_rf_path(struct net_device *dev, enum rf90_radio_path eRFPath)
switch (eRFPath) {
case RF90_PATH_A:
for (i = 0; i < RadioA_ArrayLength; i += 2) {
if (Rtl819XRadioA_Array[i] == 0xfe) {
for (i = 0; i < RTL8192E_RADIO_A_ARR_LEN; i += 2) {
if (RTL8192E_RADIO_A_ARR[i] == 0xfe) {
msleep(100);
continue;
}
rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioA_Array[i],
rtl92e_set_rf_reg(dev, eRFPath, RTL8192E_RADIO_A_ARR[i],
bMask12Bits,
Rtl819XRadioA_Array[i+1]);
RTL8192E_RADIO_A_ARR[i + 1]);
}
break;
case RF90_PATH_B:
for (i = 0; i < RadioB_ArrayLength; i += 2) {
if (Rtl819XRadioB_Array[i] == 0xfe) {
for (i = 0; i < RTL8192E_RADIO_B_ARR_LEN; i += 2) {
if (RTL8192E_RADIO_B_ARR[i] == 0xfe) {
msleep(100);
continue;
}
rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioB_Array[i],
rtl92e_set_rf_reg(dev, eRFPath, RTL8192E_RADIO_B_ARR[i],
bMask12Bits,
Rtl819XRadioB_Array[i+1]);
}
break;
case RF90_PATH_C:
for (i = 0; i < RadioC_ArrayLength; i += 2) {
if (Rtl819XRadioC_Array[i] == 0xfe) {
msleep(100);
continue;
}
rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioC_Array[i],
bMask12Bits,
Rtl819XRadioC_Array[i+1]);
}
break;
case RF90_PATH_D:
for (i = 0; i < RadioD_ArrayLength; i += 2) {
if (Rtl819XRadioD_Array[i] == 0xfe) {
msleep(100);
continue;
}
rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioD_Array[i],
bMask12Bits,
Rtl819XRadioD_Array[i+1]);
RTL8192E_RADIO_B_ARR[i + 1]);
}
break;
@ -707,21 +512,8 @@ static void _rtl92e_set_tx_power_level(struct net_device *dev, u8 channel)
u8 powerlevel = priv->tx_pwr_level_cck[channel - 1];
u8 powerlevelOFDM24G = priv->tx_pwr_level_ofdm_24g[channel - 1];
switch (priv->rf_chip) {
case RF_8225:
break;
case RF_8256:
rtl92e_set_cck_tx_power(dev, powerlevel);
rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G);
break;
case RF_8258:
break;
default:
netdev_warn(dev, "%s(): Invalid RF Chip ID\n", __func__);
break;
}
rtl92e_set_cck_tx_power(dev, powerlevel);
rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G);
}
static u8 _rtl92e_phy_set_sw_chnl_cmd_array(struct net_device *dev,
@ -786,58 +578,25 @@ static u8 _rtl92e_phy_switch_channel_step(struct net_device *dev, u8 channel,
0, 0, 0);
RfDependCmdCnt = 0;
switch (priv->rf_chip) {
case RF_8225:
if (!(channel >= 1 && channel <= 14)) {
netdev_err(dev,
"Invalid channel requested for 8225: %d\n",
channel);
return false;
}
_rtl92e_phy_set_sw_chnl_cmd_array(dev,
ieee->RfDependCmd,
RfDependCmdCnt++,
MAX_RFDEPENDCMD_CNT,
CmdID_RF_WriteReg,
rZebra1_Channel,
RF_CHANNEL_TABLE_ZEBRA[channel],
10);
_rtl92e_phy_set_sw_chnl_cmd_array(dev,
ieee->RfDependCmd,
RfDependCmdCnt++,
MAX_RFDEPENDCMD_CNT,
CmdID_End, 0, 0, 0);
break;
case RF_8256:
if (!(channel >= 1 && channel <= 14)) {
netdev_err(dev,
"Invalid channel requested for 8256: %d\n",
channel);
return false;
}
_rtl92e_phy_set_sw_chnl_cmd_array(dev,
ieee->RfDependCmd,
RfDependCmdCnt++,
MAX_RFDEPENDCMD_CNT,
CmdID_RF_WriteReg,
rZebra1_Channel,
channel, 10);
_rtl92e_phy_set_sw_chnl_cmd_array(dev,
ieee->RfDependCmd,
RfDependCmdCnt++,
MAX_RFDEPENDCMD_CNT,
CmdID_End, 0, 0, 0);
break;
case RF_8258:
break;
default:
netdev_warn(dev, "Unknown RF Chip ID\n");
if (!(channel >= 1 && channel <= 14)) {
netdev_err(dev,
"Invalid channel requested for 8256: %d\n",
channel);
return false;
}
_rtl92e_phy_set_sw_chnl_cmd_array(dev,
ieee->RfDependCmd,
RfDependCmdCnt++,
MAX_RFDEPENDCMD_CNT,
CmdID_RF_WriteReg,
rZebra1_Channel,
channel, 10);
_rtl92e_phy_set_sw_chnl_cmd_array(dev,
ieee->RfDependCmd,
RfDependCmdCnt++,
MAX_RFDEPENDCMD_CNT,
CmdID_End, 0, 0, 0);
do {
switch (*stage) {
@ -937,15 +696,6 @@ u8 rtl92e_set_channel(struct net_device *dev, u8 channel)
switch (priv->rtllib->mode) {
case WIRELESS_MODE_A:
case WIRELESS_MODE_N_5G:
if (channel <= 14) {
netdev_warn(dev,
"Channel %d not available in 802.11a.\n",
channel);
return false;
}
break;
case WIRELESS_MODE_B:
if (channel > 14) {
netdev_warn(dev,
@ -1078,10 +828,6 @@ static void _rtl92e_set_bw_mode_work_item(struct net_device *dev)
struct r8192_priv *priv = rtllib_priv(dev);
u8 regBwOpMode;
if (priv->rf_chip == RF_PSEUDO_11N) {
priv->set_bw_mode_in_progress = false;
return;
}
if (!priv->up) {
netdev_err(dev, "%s(): Driver is not initialized\n", __func__);
return;
@ -1147,25 +893,7 @@ static void _rtl92e_set_bw_mode_work_item(struct net_device *dev)
}
switch (priv->rf_chip) {
case RF_8225:
break;
case RF_8256:
rtl92e_set_bandwidth(dev, priv->current_chnl_bw);
break;
case RF_8258:
break;
case RF_PSEUDO_11N:
break;
default:
netdev_info(dev, "%s(): Unknown RFChipID: %d\n", __func__,
priv->rf_chip);
break;
}
rtl92e_set_bandwidth(dev, priv->current_chnl_bw);
atomic_dec(&(priv->rtllib->atm_swbw));
priv->set_bw_mode_in_progress = false;
@ -1291,129 +1019,88 @@ static bool _rtl92e_set_rf_power_state(struct net_device *dev,
return false;
priv->set_rf_pwr_state_in_progress = true;
switch (priv->rf_chip) {
case RF_8256:
switch (rf_power_state) {
case rf_on:
if ((priv->rtllib->rf_power_state == rf_off) &&
RT_IN_PS_LEVEL(psc, RT_RF_OFF_LEVL_HALT_NIC)) {
bool rtstatus;
u32 InitilizeCount = 3;
do {
InitilizeCount--;
rtstatus = rtl92e_enable_nic(dev);
} while (!rtstatus && (InitilizeCount > 0));
if (!rtstatus) {
netdev_err(dev,
"%s(): Failed to initialize Adapter.\n",
__func__);
priv->set_rf_pwr_state_in_progress = false;
return false;
}
RT_CLEAR_PS_LEVEL(psc,
RT_RF_OFF_LEVL_HALT_NIC);
} else {
rtl92e_writeb(dev, ANAPAR, 0x37);
mdelay(1);
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
0x4, 0x1);
priv->hw_rf_off_action = 0;
rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE,
BIT4, 0x1);
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4,
0x300, 0x3);
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
0x18, 0x3);
rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable,
0x3, 0x3);
rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable,
0x3, 0x3);
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
0x60, 0x3);
switch (rf_power_state) {
case rf_on:
if ((priv->rtllib->rf_power_state == rf_off) &&
RT_IN_PS_LEVEL(psc, RT_RF_OFF_LEVL_HALT_NIC)) {
bool rtstatus;
u32 InitilizeCount = 3;
do {
InitilizeCount--;
rtstatus = rtl92e_enable_nic(dev);
} while (!rtstatus && (InitilizeCount > 0));
if (!rtstatus) {
netdev_err(dev,
"%s(): Failed to initialize Adapter.\n",
__func__);
priv->set_rf_pwr_state_in_progress = false;
return false;
}
break;
case rf_sleep:
if (priv->rtllib->rf_power_state == rf_off)
break;
for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
ring = &priv->tx_ring[QueueID];
if (skb_queue_len(&ring->queue) == 0) {
QueueID++;
continue;
} else {
udelay(10);
i++;
}
if (i >= MAX_DOZE_WAITING_TIMES_9x)
break;
}
rtl92e_set_rf_off(dev);
break;
case rf_off:
for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
ring = &priv->tx_ring[QueueID];
if (skb_queue_len(&ring->queue) == 0) {
QueueID++;
continue;
} else {
udelay(10);
i++;
}
if (i >= MAX_DOZE_WAITING_TIMES_9x)
break;
}
if (psc->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC &&
!RT_IN_PS_LEVEL(psc, RT_RF_OFF_LEVL_HALT_NIC)) {
rtl92e_disable_nic(dev);
RT_SET_PS_LEVEL(psc, RT_RF_OFF_LEVL_HALT_NIC);
} else if (!(psc->RegRfPsLevel &
RT_RF_OFF_LEVL_HALT_NIC)) {
rtl92e_set_rf_off(dev);
}
break;
default:
bResult = false;
netdev_warn(dev,
"%s(): Unknown state requested: 0x%X.\n",
__func__, rf_power_state);
break;
RT_CLEAR_PS_LEVEL(psc,
RT_RF_OFF_LEVL_HALT_NIC);
} else {
rtl92e_writeb(dev, ANAPAR, 0x37);
mdelay(1);
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
0x4, 0x1);
priv->hw_rf_off_action = 0;
rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE,
BIT4, 0x1);
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4,
0x300, 0x3);
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
0x18, 0x3);
rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable,
0x3, 0x3);
rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable,
0x3, 0x3);
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
0x60, 0x3);
}
break;
case rf_sleep:
if (priv->rtllib->rf_power_state == rf_off)
break;
for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
ring = &priv->tx_ring[QueueID];
if (skb_queue_len(&ring->queue) == 0) {
QueueID++;
continue;
} else {
udelay(10);
i++;
}
if (i >= MAX_DOZE_WAITING_TIMES_9x)
break;
}
rtl92e_set_rf_off(dev);
break;
case rf_off:
for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
ring = &priv->tx_ring[QueueID];
if (skb_queue_len(&ring->queue) == 0) {
QueueID++;
continue;
} else {
udelay(10);
i++;
}
if (i >= MAX_DOZE_WAITING_TIMES_9x)
break;
}
rtl92e_set_rf_off(dev);
break;
default:
netdev_warn(dev, "%s(): Unknown RF type\n", __func__);
bResult = false;
netdev_warn(dev,
"%s(): Unknown state requested: 0x%X.\n",
__func__, rf_power_state);
break;
}
if (bResult) {
priv->rtllib->rf_power_state = rf_power_state;
switch (priv->rf_chip) {
case RF_8256:
break;
default:
netdev_warn(dev, "%s(): Unknown RF type\n", __func__);
break;
}
}
priv->set_rf_pwr_state_in_progress = false;

32
drivers/staging/rtl8192e/rtl8192e/r8192E_phy.h
View File

@ -9,28 +9,6 @@
#define MAX_DOZE_WAITING_TIMES_9x 64
#define AGCTAB_ArrayLength AGCTAB_ArrayLengthPciE
#define MACPHY_ArrayLength MACPHY_ArrayLengthPciE
#define RadioA_ArrayLength RadioA_ArrayLengthPciE
#define RadioB_ArrayLength RadioB_ArrayLengthPciE
#define MACPHY_Array_PGLength MACPHY_Array_PGLengthPciE
#define RadioC_ArrayLength RadioC_ArrayLengthPciE
#define RadioD_ArrayLength RadioD_ArrayLengthPciE
#define PHY_REGArrayLength PHY_REGArrayLengthPciE
#define PHY_REG_1T2RArrayLength PHY_REG_1T2RArrayLengthPciE
#define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG
#define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array
#define Rtl819XRadioA_Array Rtl8192PciERadioA_Array
#define Rtl819XRadioB_Array Rtl8192PciERadioB_Array
#define Rtl819XRadioC_Array Rtl8192PciERadioC_Array
#define Rtl819XRadioD_Array Rtl8192PciERadioD_Array
#define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array
#define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray
#define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray
extern u32 rtl819XAGCTAB_Array[];
enum hw90_block {
HW90_BLOCK_MAC = 0,
HW90_BLOCK_PHY0 = 1,
@ -47,15 +25,6 @@ enum rf90_radio_path {
RF90_PATH_MAX
};
#define bMaskByte0 0xff
#define bMaskByte1 0xff00
#define bMaskByte2 0xff0000
#define bMaskByte3 0xff000000
#define bMaskHWord 0xffff0000
#define bMaskLWord 0x0000ffff
#define bMaskDWord 0xffffffff
u8 rtl92e_is_legal_rf_path(struct net_device *dev, u32 eRFPath);
void rtl92e_set_bb_reg(struct net_device *dev, u32 dwRegAddr,
u32 dwBitMask, u32 dwData);
u32 rtl92e_get_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask);
@ -70,7 +39,6 @@ bool rtl92e_check_bb_and_rf(struct net_device *dev,
bool rtl92e_config_bb(struct net_device *dev);
void rtl92e_get_tx_power(struct net_device *dev);
void rtl92e_set_tx_power(struct net_device *dev, u8 channel);
bool rtl92e_config_phy(struct net_device *dev);
u8 rtl92e_config_rf_path(struct net_device *dev, enum rf90_radio_path eRFPath);
u8 rtl92e_set_channel(struct net_device *dev, u8 channel);

37
drivers/staging/rtl8192e/rtl8192e/r8192E_phyreg.h
View File

@ -48,41 +48,22 @@
#define rFPGA0_TxGainStage 0x80c
#define rFPGA0_RFTiming1 0x810
#define rFPGA0_RFTiming2 0x814
#define rFPGA0_XA_HSSIParameter1 0x820
#define rFPGA0_XA_HSSIParameter2 0x824
#define rFPGA0_XB_HSSIParameter1 0x828
#define rFPGA0_XB_HSSIParameter2 0x82c
#define rFPGA0_XC_HSSIParameter1 0x830
#define rFPGA0_XC_HSSIParameter2 0x834
#define rFPGA0_XD_HSSIParameter1 0x838
#define rFPGA0_XD_HSSIParameter2 0x83c
#define rFPGA0_XA_LSSIParameter 0x840
#define rFPGA0_XB_LSSIParameter 0x844
#define rFPGA0_XC_LSSIParameter 0x848
#define rFPGA0_XD_LSSIParameter 0x84c
#define rFPGA0_RFWakeUpParameter 0x850
#define rFPGA0_RFSleepUpParameter 0x854
#define rFPGA0_XAB_SwitchControl 0x858
#define rFPGA0_XCD_SwitchControl 0x85c
#define rFPGA0_XA_RFInterfaceOE 0x860
#define rFPGA0_XB_RFInterfaceOE 0x864
#define rFPGA0_XC_RFInterfaceOE 0x868
#define rFPGA0_XD_RFInterfaceOE 0x86c
#define rFPGA0_XAB_RFInterfaceSW 0x870
#define rFPGA0_XCD_RFInterfaceSW 0x874
#define rFPGA0_XAB_RFParameter 0x878
#define rFPGA0_XCD_RFParameter 0x87c
#define rFPGA0_AnalogParameter1 0x880
#define rFPGA0_AnalogParameter2 0x884
#define rFPGA0_AnalogParameter3 0x888
#define rFPGA0_AnalogParameter4 0x88c
#define rFPGA0_XA_LSSIReadBack 0x8a0
#define rFPGA0_XB_LSSIReadBack 0x8a4
#define rFPGA0_XC_LSSIReadBack 0x8a8
#define rFPGA0_XD_LSSIReadBack 0x8ac
#define rFPGA0_PSDReport 0x8b4
#define rFPGA0_XAB_RFInterfaceRB 0x8e0
#define rFPGA0_XCD_RFInterfaceRB 0x8e4
/* Page 9 - RF mode & OFDM TxSC */
#define rFPGA1_RFMOD 0x900
@ -113,15 +94,6 @@
#define rOFDM0_TRxPathEnable 0xc04
#define rOFDM0_TRMuxPar 0xc08
#define rOFDM0_TRSWIsolation 0xc0c
/* RxIQ DC offset, Rx digital filter, DC notch filter */
#define rOFDM0_XARxAFE 0xc10
#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imbalance matrix */
#define rOFDM0_XBRxAFE 0xc18
#define rOFDM0_XBRxIQImbalance 0xc1c
#define rOFDM0_XCRxAFE 0xc20
#define rOFDM0_XCRxIQImbalance 0xc24
#define rOFDM0_XDRxAFE 0xc28
#define rOFDM0_XDRxIQImbalance 0xc2c
#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */
#define rOFDM0_RxDetector2 0xc34 /* SBD */
#define rOFDM0_RxDetector3 0xc38 /* Frame Sync */
@ -132,25 +104,16 @@
#define rOFDM0_CCADropThreshold 0xc48
#define rOFDM0_ECCAThreshold 0xc4c /* Energy CCA */
#define rOFDM0_XAAGCCore1 0xc50
#define rOFDM0_XAAGCCore2 0xc54
#define rOFDM0_XBAGCCore1 0xc58
#define rOFDM0_XBAGCCore2 0xc5c
#define rOFDM0_XCAGCCore1 0xc60
#define rOFDM0_XCAGCCore2 0xc64
#define rOFDM0_XDAGCCore1 0xc68
#define rOFDM0_XDAGCCore2 0xc6c
#define rOFDM0_AGCParameter1 0xc70
#define rOFDM0_AGCParameter2 0xc74
#define rOFDM0_AGCRSSITable 0xc78
#define rOFDM0_HTSTFAGC 0xc7c
#define rOFDM0_XATxIQImbalance 0xc80
#define rOFDM0_XATxAFE 0xc84
#define rOFDM0_XBTxIQImbalance 0xc88
#define rOFDM0_XBTxAFE 0xc8c
#define rOFDM0_XCTxIQImbalance 0xc90
#define rOFDM0_XCTxAFE 0xc94
#define rOFDM0_XDTxIQImbalance 0xc98
#define rOFDM0_XDTxAFE 0xc9c
#define rOFDM0_RxHPParameter 0xce0
#define rOFDM0_TxPseudoNoiseWgt 0xce4
#define rOFDM0_FrameSync 0xcf0

202
drivers/staging/rtl8192e/rtl8192e/rtl_core.c
View File

@ -25,32 +25,10 @@
int hwwep = 1;
static char *ifname = "wlan%d";
static const struct rtl819x_ops rtl819xp_ops = {
.nic_type = NIC_8192E,
.get_eeprom_size = rtl92e_get_eeprom_size,
.init_adapter_variable = rtl92e_init_variables,
.initialize_adapter = rtl92e_start_adapter,
.link_change = rtl92e_link_change,
.tx_fill_descriptor = rtl92e_fill_tx_desc,
.tx_fill_cmd_descriptor = rtl92e_fill_tx_cmd_desc,
.rx_query_status_descriptor = rtl92e_get_rx_stats,
.rx_command_packet_handler = NULL,
.stop_adapter = rtl92e_stop_adapter,
.update_ratr_table = rtl92e_update_ratr_table,
.irq_enable = rtl92e_enable_irq,
.irq_disable = rtl92e_disable_irq,
.irq_clear = rtl92e_clear_irq,
.rx_enable = rtl92e_enable_rx,
.tx_enable = rtl92e_enable_tx,
.interrupt_recognized = rtl92e_ack_irq,
.tx_check_stuck_handler = rtl92e_is_tx_stuck,
.rx_check_stuck_handler = rtl92e_is_rx_stuck,
};
static struct pci_device_id rtl8192_pci_id_tbl[] = {
{RTL_PCI_DEVICE(0x10ec, 0x8192, rtl819xp_ops)},
{RTL_PCI_DEVICE(0x07aa, 0x0044, rtl819xp_ops)},
{RTL_PCI_DEVICE(0x07aa, 0x0047, rtl819xp_ops)},
{PCI_DEVICE(0x10ec, 0x8192)},
{PCI_DEVICE(0x07aa, 0x0044)},
{PCI_DEVICE(0x07aa, 0x0047)},
{}
};
@ -255,14 +233,14 @@ void rtl92e_irq_enable(struct net_device *dev)
priv->irq_enabled = 1;
priv->ops->irq_enable(dev);
rtl92e_enable_irq(dev);
}
void rtl92e_irq_disable(struct net_device *dev)
{
struct r8192_priv *priv = rtllib_priv(dev);
priv->ops->irq_disable(dev);
rtl92e_disable_irq(dev);
priv->irq_enabled = 0;
}
@ -271,9 +249,6 @@ static void _rtl92e_set_chan(struct net_device *dev, short ch)
{
struct r8192_priv *priv = rtllib_priv(dev);
if (priv->chan_forced)
return;
priv->chan = ch;
if (priv->rf_set_chan)
@ -333,8 +308,7 @@ static const struct rtllib_qos_parameters def_qos_parameters = {
static void _rtl92e_update_beacon(void *data)
{
struct r8192_priv *priv = container_of_work_rsl(data, struct r8192_priv,
update_beacon_wq.work);
struct r8192_priv *priv = container_of(data, struct r8192_priv, update_beacon_wq.work);
struct net_device *dev = priv->rtllib->dev;
struct rtllib_device *ieee = priv->rtllib;
struct rtllib_network *net = &ieee->current_network;
@ -348,8 +322,7 @@ static void _rtl92e_update_beacon(void *data)
static void _rtl92e_qos_activate(void *data)
{
struct r8192_priv *priv = container_of_work_rsl(data, struct r8192_priv,
qos_activate);
struct r8192_priv *priv = container_of(data, struct r8192_priv, qos_activate);
struct net_device *dev = priv->rtllib->dev;
int i;
@ -499,7 +472,7 @@ static void _rtl92e_prepare_beacon(struct tasklet_struct *t)
skb_push(pnewskb, priv->rtllib->tx_headroom);
pdesc = &ring->desc[0];
priv->ops->tx_fill_descriptor(dev, pdesc, tcb_desc, pnewskb);
rtl92e_fill_tx_desc(dev, pdesc, tcb_desc, pnewskb);
__skb_queue_tail(&ring->queue, pnewskb);
pdesc->OWN = 1;
}
@ -605,8 +578,7 @@ static void _rtl92e_refresh_support_rate(struct r8192_priv *priv)
{
struct rtllib_device *ieee = priv->rtllib;
if (ieee->mode == WIRELESS_MODE_N_24G ||
ieee->mode == WIRELESS_MODE_N_5G) {
if (ieee->mode == WIRELESS_MODE_N_24G) {
memcpy(ieee->reg_dot11ht_oper_rate_set,
ieee->reg_ht_supp_rate_set, 16);
memcpy(ieee->reg_dot11tx_ht_oper_rate_set,
@ -617,52 +589,13 @@ static void _rtl92e_refresh_support_rate(struct r8192_priv *priv)
}
}
static u8 _rtl92e_get_supported_wireless_mode(struct net_device *dev)
{
struct r8192_priv *priv = rtllib_priv(dev);
u8 ret = 0;
switch (priv->rf_chip) {
case RF_8225:
case RF_8256:
case RF_6052:
case RF_PSEUDO_11N:
ret = (WIRELESS_MODE_N_24G | WIRELESS_MODE_G | WIRELESS_MODE_B);
break;
case RF_8258:
ret = (WIRELESS_MODE_A | WIRELESS_MODE_N_5G);
break;
default:
ret = WIRELESS_MODE_B;
break;
}
return ret;
}
void rtl92e_set_wireless_mode(struct net_device *dev, u8 wireless_mode)
{
struct r8192_priv *priv = rtllib_priv(dev);
u8 support_mode = _rtl92e_get_supported_wireless_mode(dev);
u8 support_mode = (WIRELESS_MODE_N_24G | WIRELESS_MODE_G | WIRELESS_MODE_B);
if ((wireless_mode == WIRELESS_MODE_AUTO) ||
((wireless_mode & support_mode) == 0)) {
if (support_mode & WIRELESS_MODE_N_24G) {
wireless_mode = WIRELESS_MODE_N_24G;
} else if (support_mode & WIRELESS_MODE_N_5G) {
wireless_mode = WIRELESS_MODE_N_5G;
} else if ((support_mode & WIRELESS_MODE_A)) {
wireless_mode = WIRELESS_MODE_A;
} else if ((support_mode & WIRELESS_MODE_G)) {
wireless_mode = WIRELESS_MODE_G;
} else if ((support_mode & WIRELESS_MODE_B)) {
wireless_mode = WIRELESS_MODE_B;
} else {
netdev_info(dev,
"%s(): Unsupported mode requested. Fallback to 802.11b\n",
__func__);
wireless_mode = WIRELESS_MODE_B;
}
}
if ((wireless_mode == WIRELESS_MODE_AUTO) || ((wireless_mode & support_mode) == 0))
wireless_mode = WIRELESS_MODE_N_24G;
if ((wireless_mode & (WIRELESS_MODE_B | WIRELESS_MODE_G)) ==
(WIRELESS_MODE_G | WIRELESS_MODE_B))
@ -670,12 +603,11 @@ void rtl92e_set_wireless_mode(struct net_device *dev, u8 wireless_mode)
priv->rtllib->mode = wireless_mode;
if ((wireless_mode == WIRELESS_MODE_N_24G) ||
(wireless_mode == WIRELESS_MODE_N_5G)) {
if (wireless_mode == WIRELESS_MODE_N_24G)
priv->rtllib->ht_info->enable_ht = 1;
} else {
else
priv->rtllib->ht_info->enable_ht = 0;
}
_rtl92e_refresh_support_rate(priv);
}
@ -692,7 +624,7 @@ static int _rtl92e_sta_up(struct net_device *dev, bool is_silent_reset)
priv->rtllib->ieee_up = 1;
priv->up_first_time = 0;
init_status = priv->ops->initialize_adapter(dev);
init_status = rtl92e_start_adapter(dev);
if (!init_status) {
netdev_err(dev, "%s(): Initialization failed!\n", __func__);
return -1;
@ -713,6 +645,7 @@ static int _rtl92e_sta_up(struct net_device *dev, bool is_silent_reset)
else
netif_wake_queue(dev);
priv->bfirst_after_down = false;
return 0;
}
@ -725,8 +658,7 @@ static int _rtl92e_sta_down(struct net_device *dev, bool shutdownrf)
if (priv->up == 0)
return -1;
if (priv->rtllib->rtllib_ips_leave)
priv->rtllib->rtllib_ips_leave(dev);
priv->rtllib->rtllib_ips_leave(dev);
if (priv->rtllib->state == RTLLIB_LINKED)
rtl92e_leisure_ps_leave(dev);
@ -762,7 +694,7 @@ static int _rtl92e_sta_down(struct net_device *dev, bool shutdownrf)
}
priv->rf_change_in_progress = true;
spin_unlock_irqrestore(&priv->rf_ps_lock, flags);
priv->ops->stop_adapter(dev, false);
rtl92e_stop_adapter(dev, false);
spin_lock_irqsave(&priv->rf_ps_lock, flags);
priv->rf_change_in_progress = false;
spin_unlock_irqrestore(&priv->rf_ps_lock, flags);
@ -779,7 +711,7 @@ static void _rtl92e_init_priv_handler(struct net_device *dev)
priv->rtllib->softmac_hard_start_xmit = _rtl92e_hard_start_xmit;
priv->rtllib->set_chan = _rtl92e_set_chan;
priv->rtllib->link_change = priv->ops->link_change;
priv->rtllib->link_change = rtl92e_link_change;
priv->rtllib->softmac_data_hard_start_xmit = _rtl92e_hard_data_xmit;
priv->rtllib->check_nic_enough_desc = _rtl92e_check_nic_enough_desc;
priv->rtllib->handle_assoc_response = _rtl92e_handle_assoc_response;
@ -854,7 +786,6 @@ static void _rtl92e_init_priv_variable(struct net_device *dev)
priv->rtllib->short_slot = 1;
priv->promisc = (dev->flags & IFF_PROMISC) ? 1 : 0;
priv->bcck_in_ch14 = false;
priv->bfsync_processing = false;
priv->cck_present_attn = 0;
priv->rfa_txpowertrackingindex = 0;
priv->rfc_txpowertrackingindex = 0;
@ -913,22 +844,15 @@ static void _rtl92e_init_priv_task(struct net_device *dev)
{
struct r8192_priv *priv = rtllib_priv(dev);
INIT_WORK_RSL(&priv->reset_wq, (void *)_rtl92e_restart, dev);
INIT_WORK_RSL(&priv->rtllib->ips_leave_wq, (void *)rtl92e_ips_leave_wq,
dev);
INIT_DELAYED_WORK_RSL(&priv->watch_dog_wq,
(void *)_rtl92e_watchdog_wq_cb, dev);
INIT_DELAYED_WORK_RSL(&priv->txpower_tracking_wq,
(void *)rtl92e_dm_txpower_tracking_wq, dev);
INIT_DELAYED_WORK_RSL(&priv->rfpath_check_wq,
(void *)rtl92e_dm_rf_pathcheck_wq, dev);
INIT_DELAYED_WORK_RSL(&priv->update_beacon_wq,
(void *)_rtl92e_update_beacon, dev);
INIT_WORK_RSL(&priv->qos_activate, (void *)_rtl92e_qos_activate, dev);
INIT_DELAYED_WORK_RSL(&priv->rtllib->hw_wakeup_wq,
(void *)rtl92e_hw_wakeup_wq, dev);
INIT_DELAYED_WORK_RSL(&priv->rtllib->hw_sleep_wq,
(void *)rtl92e_hw_sleep_wq, dev);
INIT_WORK(&priv->reset_wq, (void *)_rtl92e_restart);
INIT_WORK(&priv->rtllib->ips_leave_wq, (void *)rtl92e_ips_leave_wq);
INIT_DELAYED_WORK(&priv->watch_dog_wq, (void *)_rtl92e_watchdog_wq_cb);
INIT_DELAYED_WORK(&priv->txpower_tracking_wq, (void *)rtl92e_dm_txpower_tracking_wq);
INIT_DELAYED_WORK(&priv->rfpath_check_wq, (void *)rtl92e_dm_rf_pathcheck_wq);
INIT_DELAYED_WORK(&priv->update_beacon_wq, (void *)_rtl92e_update_beacon);
INIT_WORK(&priv->qos_activate, (void *)_rtl92e_qos_activate);
INIT_DELAYED_WORK(&priv->rtllib->hw_wakeup_wq, (void *)rtl92e_hw_wakeup_wq);
INIT_DELAYED_WORK(&priv->rtllib->hw_sleep_wq, (void *)rtl92e_hw_sleep_wq);
tasklet_setup(&priv->irq_rx_tasklet, _rtl92e_irq_rx_tasklet);
tasklet_setup(&priv->irq_tx_tasklet, _rtl92e_irq_tx_tasklet);
tasklet_setup(&priv->irq_prepare_beacon_tasklet,
@ -941,13 +865,6 @@ static short _rtl92e_get_channel_map(struct net_device *dev)
struct r8192_priv *priv = rtllib_priv(dev);
if ((priv->rf_chip != RF_8225) && (priv->rf_chip != RF_8256) &&
(priv->rf_chip != RF_6052)) {
netdev_err(dev, "%s: unknown rf chip, can't set channel map\n",
__func__);
return -1;
}
if (priv->chnl_plan >= COUNTRY_CODE_MAX) {
netdev_info(dev,
"rtl819x_init:Error channel plan! Set to default.\n");
@ -974,8 +891,8 @@ static short _rtl92e_init(struct net_device *dev)
_rtl92e_init_priv_variable(dev);
_rtl92e_init_priv_lock(priv);
_rtl92e_init_priv_task(dev);
priv->ops->get_eeprom_size(dev);
priv->ops->init_adapter_variable(dev);
rtl92e_get_eeprom_size(dev);
rtl92e_init_variables(dev);
_rtl92e_get_channel_map(dev);
rtl92e_dm_init(dev);
@ -1068,7 +985,7 @@ static enum reset_type _rtl92e_tx_check_stuck(struct net_device *dev)
spin_unlock_irqrestore(&priv->irq_th_lock, flags);
if (bCheckFwTxCnt) {
if (priv->ops->tx_check_stuck_handler(dev))
if (rtl92e_is_tx_stuck(dev))
return RESET_TYPE_SILENT;
}
@ -1077,9 +994,7 @@ static enum reset_type _rtl92e_tx_check_stuck(struct net_device *dev)
static enum reset_type _rtl92e_rx_check_stuck(struct net_device *dev)
{
struct r8192_priv *priv = rtllib_priv(dev);
if (priv->ops->rx_check_stuck_handler(dev))
if (rtl92e_is_rx_stuck(dev))
return RESET_TYPE_SILENT;
return RESET_TYPE_NORESET;
@ -1410,16 +1325,14 @@ static void _rtl92e_watchdog_timer_cb(struct timer_list *t)
****************************************************************************/
void rtl92e_rx_enable(struct net_device *dev)
{
struct r8192_priv *priv = rtllib_priv(dev);
priv->ops->rx_enable(dev);
rtl92e_enable_rx(dev);
}
void rtl92e_tx_enable(struct net_device *dev)
{
struct r8192_priv *priv = rtllib_priv(dev);
priv->ops->tx_enable(dev);
rtl92e_enable_tx(dev);
rtllib_reset_queue(priv->rtllib);
}
@ -1581,7 +1494,7 @@ static void _rtl92e_tx_cmd(struct net_device *dev, struct sk_buff *skb)
tcb_desc = (struct cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
priv->ops->tx_fill_cmd_descriptor(dev, entry, tcb_desc, skb);
rtl92e_fill_tx_cmd_desc(dev, entry, tcb_desc, skb);
__skb_queue_tail(&ring->queue, skb);
spin_unlock_irqrestore(&priv->irq_th_lock, flags);
@ -1640,7 +1553,7 @@ static short _rtl92e_tx(struct net_device *dev, struct sk_buff *skb)
if (priv->rtllib->LedControlHandler)
priv->rtllib->LedControlHandler(dev, LED_CTL_TX);
}
priv->ops->tx_fill_descriptor(dev, pdesc, tcb_desc, skb);
rtl92e_fill_tx_desc(dev, pdesc, tcb_desc, skb);
__skb_queue_tail(&ring->queue, skb);
pdesc->OWN = 1;
spin_unlock_irqrestore(&priv->irq_th_lock, flags);
@ -1680,7 +1593,7 @@ static short _rtl92e_alloc_rx_ring(struct net_device *dev)
priv->rx_buf[rx_queue_idx][i] = skb;
mapping = (dma_addr_t *)skb->cb;
*mapping = dma_map_single(&priv->pdev->dev,
skb_tail_pointer_rsl(skb),
skb_tail_pointer(skb),
priv->rxbuffersize, DMA_FROM_DEVICE);
if (dma_mapping_error(&priv->pdev->dev, *mapping)) {
dev_kfree_skb_any(skb);
@ -1890,8 +1803,7 @@ static void _rtl92e_rx_normal(struct net_device *dev)
if (pdesc->OWN)
return;
if (!priv->ops->rx_query_status_descriptor(dev, &stats,
pdesc, skb))
if (!rtl92e_get_rx_stats(dev, &stats, pdesc, skb))
goto done;
new_skb = dev_alloc_skb(priv->rxbuffersize);
/* if allocation of new skb failed - drop current packet
@ -1937,7 +1849,7 @@ static void _rtl92e_rx_normal(struct net_device *dev)
priv->rx_buf[rx_queue_idx][priv->rx_idx[rx_queue_idx]] =
skb;
*((dma_addr_t *)skb->cb) = dma_map_single(&priv->pdev->dev,
skb_tail_pointer_rsl(skb),
skb_tail_pointer(skb),
priv->rxbuffersize, DMA_FROM_DEVICE);
if (dma_mapping_error(&priv->pdev->dev, *((dma_addr_t *)skb->cb))) {
dev_kfree_skb_any(skb);
@ -2062,14 +1974,13 @@ void rtl92e_commit(struct net_device *dev)
return;
rtllib_softmac_stop_protocol(priv->rtllib, 0, true);
rtl92e_irq_disable(dev);
priv->ops->stop_adapter(dev, true);
rtl92e_stop_adapter(dev, true);
_rtl92e_up(dev, false);
}
static void _rtl92e_restart(void *data)
{
struct r8192_priv *priv = container_of_work_rsl(data, struct r8192_priv,
reset_wq);
struct r8192_priv *priv = container_of(data, struct r8192_priv, reset_wq);
struct net_device *dev = priv->rtllib->dev;
mutex_lock(&priv->wx_mutex);
@ -2118,7 +2029,7 @@ static irqreturn_t _rtl92e_irq(int irq, void *netdev)
spin_lock_irqsave(&priv->irq_th_lock, flags);
priv->ops->interrupt_recognized(dev, &inta, &intb);
rtl92e_ack_irq(dev, &inta, &intb);
if (!inta) {
spin_unlock_irqrestore(&priv->irq_th_lock, flags);
@ -2214,10 +2125,8 @@ static int _rtl92e_pci_probe(struct pci_dev *pdev,
unsigned long ioaddr = 0;
struct net_device *dev = NULL;
struct r8192_priv *priv = NULL;
struct rtl819x_ops *ops = (struct rtl819x_ops *)(id->driver_data);
unsigned long pmem_start, pmem_len, pmem_flags;
int err = -ENOMEM;
u8 revision_id;
if (pci_enable_device(pdev)) {
dev_err(&pdev->dev, "Failed to enable PCI device");
@ -2276,13 +2185,6 @@ static int _rtl92e_pci_probe(struct pci_dev *pdev,
dev->mem_start = ioaddr;
dev->mem_end = ioaddr + pci_resource_len(pdev, 0);
pci_read_config_byte(pdev, 0x08, &revision_id);
/* If the revisionid is 0x10, the device uses rtl8192se. */
if (pdev->device == 0x8192 && revision_id == 0x10)
goto err_unmap;
priv->ops = ops;
if (!rtl92e_check_adapter(pdev, dev))
goto err_unmap;
@ -2383,7 +2285,7 @@ bool rtl92e_enable_nic(struct net_device *dev)
return false;
}
init_status = priv->ops->initialize_adapter(dev);
init_status = rtl92e_start_adapter(dev);
if (!init_status) {
netdev_warn(dev, "%s(): Initialization failed!\n", __func__);
priv->bdisable_nic = false;
@ -2396,22 +2298,6 @@ bool rtl92e_enable_nic(struct net_device *dev)
return init_status;
}
bool rtl92e_disable_nic(struct net_device *dev)
{
struct r8192_priv *priv = rtllib_priv(dev);
u8 tmp_state = 0;
priv->bdisable_nic = true;
tmp_state = priv->rtllib->state;
rtllib_softmac_stop_protocol(priv->rtllib, 0, false);
priv->rtllib->state = tmp_state;
_rtl92e_cancel_deferred_work(priv);
rtl92e_irq_disable(dev);
priv->ops->stop_adapter(dev, false);
return true;
}
module_pci_driver(rtl8192_pci_driver);
void rtl92e_check_rfctrl_gpio_timer(struct timer_list *t)

69
drivers/staging/rtl8192e/rtl8192e/rtl_core.h
View File

@ -52,22 +52,12 @@
#define DRV_AUTHOR "<wlanfae@realtek.com>"
#define DRV_VERSION "0014.0401.2010"
#define IS_HARDWARE_TYPE_8192SE(_priv) \
(((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8192SE)
#define RTL_PCI_DEVICE(vend, dev, cfg) \
.vendor = (vend), .device = (dev), \
.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
.driver_data = (kernel_ulong_t)&(cfg)
#define TOTAL_CAM_ENTRY 32
#define CAM_CONTENT_COUNT 8
#define HAL_HW_PCI_REVISION_ID_8192PCIE 0x01
#define HAL_HW_PCI_REVISION_ID_8192SE 0x10
#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
#define RTLLIB_WATCH_DOG_TIME 2000
#define MAX_DEV_ADDR_SIZE 8 /*support till 64 bit bus width OS*/
@ -134,24 +124,10 @@ enum dcmg_txcmd_op {
TXCMD_XXXX_CTRL,
};
enum rt_rf_type_819xu {
RF_TYPE_MIN = 0,
RF_8225,
RF_8256,
RF_8258,
RF_6052 = 4,
RF_PSEUDO_11N = 5,
};
enum rt_customer_id {
RT_CID_DEFAULT = 0,
RT_CID_819x_CAMEO = 6,
RT_CID_819x_RUNTOP = 7,
RT_CID_TOSHIBA = 9,
RT_CID_819X_NETCORE = 10,
RT_CID_Nettronix = 11,
RT_CID_DLINK = 12,
RT_CID_PRONET = 13,
};
enum reset_type {
@ -203,41 +179,6 @@ struct rtl8192_tx_ring {
struct sk_buff_head queue;
};
struct rtl819x_ops {
enum nic_t nic_type;
void (*get_eeprom_size)(struct net_device *dev);
void (*init_adapter_variable)(struct net_device *dev);
void (*init_before_adapter_start)(struct net_device *dev);
bool (*initialize_adapter)(struct net_device *dev);
void (*link_change)(struct net_device *dev);
void (*tx_fill_descriptor)(struct net_device *dev,
struct tx_desc *tx_desc,
struct cb_desc *cb_desc,
struct sk_buff *skb);
void (*tx_fill_cmd_descriptor)(struct net_device *dev,
struct tx_desc_cmd *entry,
struct cb_desc *cb_desc,
struct sk_buff *skb);
bool (*rx_query_status_descriptor)(struct net_device *dev,
struct rtllib_rx_stats *stats,
struct rx_desc *pdesc,
struct sk_buff *skb);
bool (*rx_command_packet_handler)(struct net_device *dev,
struct sk_buff *skb,
struct rx_desc *pdesc);
void (*stop_adapter)(struct net_device *dev, bool reset);
void (*update_ratr_table)(struct net_device *dev);
void (*irq_enable)(struct net_device *dev);
void (*irq_disable)(struct net_device *dev);
void (*irq_clear)(struct net_device *dev);
void (*rx_enable)(struct net_device *dev);
void (*tx_enable)(struct net_device *dev);
void (*interrupt_recognized)(struct net_device *dev,
u32 *p_inta, u32 *p_intb);
bool (*tx_check_stuck_handler)(struct net_device *dev);
bool (*rx_check_stuck_handler)(struct net_device *dev);
};
struct r8192_priv {
struct pci_dev *pdev;
struct pci_dev *bridge_pdev;
@ -255,14 +196,12 @@ struct r8192_priv {
struct delayed_work txpower_tracking_wq;
struct delayed_work rfpath_check_wq;
struct delayed_work gpio_change_rf_wq;
struct rtl819x_ops *ops;
struct rtllib_device *rtllib;
struct work_struct reset_wq;
enum rt_customer_id customer_id;
enum rt_rf_type_819xu rf_chip;
enum ht_channel_width current_chnl_bw;
struct bb_reg_definition phy_reg_def[4];
struct rate_adaptive rate_adaptive;
@ -342,7 +281,6 @@ struct r8192_priv {
enum nic_t card_8192;
u8 card_8192_version;
u8 rf_type;
u8 ic_cut;
char nick[IW_ESSID_MAX_SIZE + 1];
u8 check_roaming_cnt;
@ -419,7 +357,6 @@ struct r8192_priv {
u8 rfa_txpowertrackingindex_real;
u8 rfa_txpowertracking_default;
u8 rfc_txpowertrackingindex;
u8 rfc_txpowertrackingindex_real;
bool btxpower_tracking;
bool bcck_in_ch14;
@ -438,14 +375,11 @@ struct r8192_priv {
bool bcurrent_turbo_EDCA;
bool bis_cur_rdlstate;
bool bfsync_processing;
u32 rate_record;
u32 rate_count_diff_rec;
u32 continue_diff_count;
bool bswitch_fsync;
u8 framesync;
u8 frame_sync_monitor;
u32 reset_count;
enum reset_type rst_progress;
@ -454,8 +388,6 @@ struct r8192_priv {
bool reset_in_progress;
bool force_reset;
bool force_lps;
bool chan_forced;
};
extern const struct ethtool_ops rtl819x_ethtool_ops;
@ -495,7 +427,6 @@ u8 rtl92e_rx_db_to_percent(s8 antpower);
void rtl92e_copy_mpdu_stats(struct rtllib_rx_stats *psrc_stats,
struct rtllib_rx_stats *ptarget_stats);
bool rtl92e_enable_nic(struct net_device *dev);
bool rtl92e_disable_nic(struct net_device *dev);
bool rtl92e_set_rf_state(struct net_device *dev,
enum rt_rf_power_state state_to_set,

256
drivers/staging/rtl8192e/rtl8192e/rtl_dm.c
View File

@ -173,7 +173,6 @@ static void _rtl92e_dm_pd_th(struct net_device *dev);
static void _rtl92e_dm_cs_ratio(struct net_device *dev);
static void _rtl92e_dm_init_cts_to_self(struct net_device *dev);
static void _rtl92e_dm_init_wa_broadcom_iot(struct net_device *dev);
static void _rtl92e_dm_check_edca_turbo(struct net_device *dev);
static void _rtl92e_dm_check_rx_path_selection(struct net_device *dev);
@ -214,11 +213,8 @@ void rtl92e_dm_init(struct net_device *dev)
_rtl92e_dm_init_fsync(dev);
_rtl92e_dm_init_rx_path_selection(dev);
_rtl92e_dm_init_cts_to_self(dev);
if (IS_HARDWARE_TYPE_8192SE(dev))
_rtl92e_dm_init_wa_broadcom_iot(dev);
INIT_DELAYED_WORK_RSL(&priv->gpio_change_rf_wq,
(void *)_rtl92e_dm_check_rf_ctrl_gpio, dev);
INIT_DELAYED_WORK(&priv->gpio_change_rf_wq, (void *)_rtl92e_dm_check_rf_ctrl_gpio);
}
void rtl92e_dm_deinit(struct net_device *dev)
@ -273,26 +269,14 @@ void rtl92e_init_adaptive_rate(struct net_device *dev)
pra->ping_rssi_enable = 0;
pra->ping_rssi_thresh_for_ra = 15;
if (priv->rf_type == RF_2T4R) {
pra->upper_rssi_threshold_ratr = 0x8f0f0000;
pra->middle_rssi_threshold_ratr = 0x8f0ff000;
pra->low_rssi_threshold_ratr = 0x8f0ff001;
pra->low_rssi_threshold_ratr_40M = 0x8f0ff005;
pra->low_rssi_threshold_ratr_20M = 0x8f0ff001;
pra->ping_rssi_ratr = 0x0000000d;
} else if (priv->rf_type == RF_1T2R) {
pra->upper_rssi_threshold_ratr = 0x000fc000;
pra->middle_rssi_threshold_ratr = 0x000ff000;
pra->low_rssi_threshold_ratr = 0x000ff001;
pra->low_rssi_threshold_ratr_40M = 0x000ff005;
pra->low_rssi_threshold_ratr_20M = 0x000ff001;
pra->ping_rssi_ratr = 0x0000000d;
}
pra->upper_rssi_threshold_ratr = 0x000fc000;
pra->middle_rssi_threshold_ratr = 0x000ff000;
pra->low_rssi_threshold_ratr = 0x000ff001;
pra->low_rssi_threshold_ratr_40M = 0x000ff005;
pra->low_rssi_threshold_ratr_20M = 0x000ff001;
pra->ping_rssi_ratr = 0x0000000d;
}
static void _rtl92e_dm_check_rate_adaptive(struct net_device *dev)
{
struct r8192_priv *priv = rtllib_priv(dev);
@ -309,8 +293,7 @@ static void _rtl92e_dm_check_rate_adaptive(struct net_device *dev)
if (pra->rate_adaptive_disabled)
return;
if (!(priv->rtllib->mode == WIRELESS_MODE_N_24G ||
priv->rtllib->mode == WIRELESS_MODE_N_5G))
if (priv->rtllib->mode != WIRELESS_MODE_N_24G)
return;
if (priv->rtllib->state == RTLLIB_LINKED) {
@ -391,8 +374,7 @@ static void _rtl92e_dm_check_rate_adaptive(struct net_device *dev)
u32 ratr_value;
ratr_value = targetRATR;
if (priv->rf_type == RF_1T2R)
ratr_value &= ~(RATE_ALL_OFDM_2SS);
ratr_value &= ~(RATE_ALL_OFDM_2SS);
rtl92e_writel(dev, RATR0, ratr_value);
rtl92e_writeb(dev, UFWP, 1);
@ -490,93 +472,39 @@ static u8 CCKSwingTable_Ch14[CCK_TABLE_LEN][8] = {
#define Tssi_Report_Value2 0x13e
#define FW_Busy_Flag 0x13f
static void _rtl92e_dm_tx_update_tssi_weak_signal(struct net_device *dev,
u8 RF_Type)
static void _rtl92e_dm_tx_update_tssi_weak_signal(struct net_device *dev)
{
struct r8192_priv *p = rtllib_priv(dev);
if (RF_Type == RF_2T4R) {
if ((p->rfa_txpowertrackingindex > 0) &&
(p->rfc_txpowertrackingindex > 0)) {
p->rfa_txpowertrackingindex--;
if (p->rfa_txpowertrackingindex_real > 4) {
p->rfa_txpowertrackingindex_real--;
rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
bMaskDWord,
dm_tx_bb_gain[p->rfa_txpowertrackingindex_real]);
}
p->rfc_txpowertrackingindex--;
if (p->rfc_txpowertrackingindex_real > 4) {
p->rfc_txpowertrackingindex_real--;
rtl92e_set_bb_reg(dev,
rOFDM0_XCTxIQImbalance,
bMaskDWord,
dm_tx_bb_gain[p->rfc_txpowertrackingindex_real]);
}
} else {
rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
bMaskDWord,
dm_tx_bb_gain[4]);
if (p->rfa_txpowertrackingindex > 0) {
p->rfa_txpowertrackingindex--;
if (p->rfa_txpowertrackingindex_real > 4) {
p->rfa_txpowertrackingindex_real--;
rtl92e_set_bb_reg(dev,
rOFDM0_XCTxIQImbalance,
bMaskDWord, dm_tx_bb_gain[4]);
rOFDM0_XATxIQImbalance,
bMaskDWord,
dm_tx_bb_gain[p->rfa_txpowertrackingindex_real]);
}
} else {
if (p->rfa_txpowertrackingindex > 0) {
p->rfa_txpowertrackingindex--;
if (p->rfa_txpowertrackingindex_real > 4) {
p->rfa_txpowertrackingindex_real--;
rtl92e_set_bb_reg(dev,
rOFDM0_XATxIQImbalance,
bMaskDWord,
dm_tx_bb_gain[p->rfa_txpowertrackingindex_real]);
}
} else {
rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
bMaskDWord, dm_tx_bb_gain[4]);
}
rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
bMaskDWord, dm_tx_bb_gain[4]);
}
}
static void _rtl92e_dm_tx_update_tssi_strong_signal(struct net_device *dev,
u8 RF_Type)
static void _rtl92e_dm_tx_update_tssi_strong_signal(struct net_device *dev)
{
struct r8192_priv *p = rtllib_priv(dev);
if (RF_Type == RF_2T4R) {
if ((p->rfa_txpowertrackingindex < TX_BB_GAIN_TABLE_LEN - 1) &&
(p->rfc_txpowertrackingindex < TX_BB_GAIN_TABLE_LEN - 1)) {
p->rfa_txpowertrackingindex++;
p->rfa_txpowertrackingindex_real++;
rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
bMaskDWord,
dm_tx_bb_gain[p->rfa_txpowertrackingindex_real]);
p->rfc_txpowertrackingindex++;
p->rfc_txpowertrackingindex_real++;
rtl92e_set_bb_reg(dev, rOFDM0_XCTxIQImbalance,
bMaskDWord,
dm_tx_bb_gain[p->rfc_txpowertrackingindex_real]);
} else {
rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
bMaskDWord,
dm_tx_bb_gain[TX_BB_GAIN_TABLE_LEN - 1]);
rtl92e_set_bb_reg(dev, rOFDM0_XCTxIQImbalance,
bMaskDWord,
dm_tx_bb_gain[TX_BB_GAIN_TABLE_LEN - 1]);
}
if (p->rfa_txpowertrackingindex < (TX_BB_GAIN_TABLE_LEN - 1)) {
p->rfa_txpowertrackingindex++;
p->rfa_txpowertrackingindex_real++;
rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
bMaskDWord,
dm_tx_bb_gain[p->rfa_txpowertrackingindex_real]);
} else {
if (p->rfa_txpowertrackingindex < (TX_BB_GAIN_TABLE_LEN - 1)) {
p->rfa_txpowertrackingindex++;
p->rfa_txpowertrackingindex_real++;
rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
bMaskDWord,
dm_tx_bb_gain[p->rfa_txpowertrackingindex_real]);
} else {
rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
bMaskDWord,
dm_tx_bb_gain[TX_BB_GAIN_TABLE_LEN - 1]);
}
rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
bMaskDWord,
dm_tx_bb_gain[TX_BB_GAIN_TABLE_LEN - 1]);
}
}
@ -585,10 +513,8 @@ static void _rtl92e_dm_tx_power_tracking_callback_tssi(struct net_device *dev)
struct r8192_priv *priv = rtllib_priv(dev);
bool viviflag = false;
struct dcmd_txcmd tx_cmd;
u8 powerlevelOFDM24G;
int i = 0, j = 0, k = 0;
u8 RF_Type, tmp_report[5] = {0, 0, 0, 0, 0};
u32 Value;
u8 tmp_report[5] = {0, 0, 0, 0, 0};
u8 Pwr_Flag;
u16 Avg_TSSI_Meas, tssi_13dBm, Avg_TSSI_Meas_from_driver = 0;
u32 delta = 0;
@ -597,15 +523,11 @@ static void _rtl92e_dm_tx_power_tracking_callback_tssi(struct net_device *dev)
rtl92e_writeb(dev, FW_Busy_Flag, 0);
priv->rtllib->bdynamic_txpower_enable = false;
powerlevelOFDM24G = priv->pwr_track >> 24;
RF_Type = priv->rf_type;
Value = (RF_Type<<8) | powerlevelOFDM24G;
for (j = 0; j <= 30; j++) {
tx_cmd.op = TXCMD_SET_TX_PWR_TRACKING;
tx_cmd.length = 4;
tx_cmd.value = Value;
tx_cmd.value = priv->pwr_track >> 24;
rtl92e_send_cmd_pkt(dev, DESC_PACKET_TYPE_NORMAL, (u8 *)&tx_cmd,
sizeof(struct dcmd_txcmd));
mdelay(1);
@ -677,18 +599,12 @@ static void _rtl92e_dm_tx_power_tracking_callback_tssi(struct net_device *dev)
return;
}
if (Avg_TSSI_Meas_from_driver < tssi_13dBm - E_FOR_TX_POWER_TRACK)
_rtl92e_dm_tx_update_tssi_weak_signal(dev,
RF_Type);
_rtl92e_dm_tx_update_tssi_weak_signal(dev);
else
_rtl92e_dm_tx_update_tssi_strong_signal(dev, RF_Type);
_rtl92e_dm_tx_update_tssi_strong_signal(dev);
if (RF_Type == RF_2T4R) {
priv->cck_present_attn_diff
= priv->rfa_txpowertrackingindex - priv->rfa_txpowertracking_default;
} else {
priv->cck_present_attn_diff
= priv->rfa_txpowertrackingindex_real - priv->rfa_txpowertracking_default;
}
priv->cck_present_attn_diff
= priv->rfa_txpowertrackingindex_real - priv->rfa_txpowertracking_default;
if (priv->current_chnl_bw == HT_CHANNEL_WIDTH_20)
priv->cck_present_attn =
@ -897,10 +813,7 @@ static void _rtl92e_dm_check_tx_power_tracking_thermal(struct net_device *dev)
static u8 TM_Trigger;
u8 TxPowerCheckCnt = 0;
if (IS_HARDWARE_TYPE_8192SE(dev))
TxPowerCheckCnt = 5;
else
TxPowerCheckCnt = 2;
TxPowerCheckCnt = 2;
if (!priv->btxpower_tracking)
return;
@ -1042,12 +955,10 @@ void rtl92e_dm_restore_state(struct net_device *dev)
if (priv->rate_adaptive.rate_adaptive_disabled)
return;
if (!(priv->rtllib->mode == WIRELESS_MODE_N_24G ||
priv->rtllib->mode == WIRELESS_MODE_N_5G))
if (priv->rtllib->mode != WIRELESS_MODE_N_24G)
return;
ratr_value = reg_ratr;
if (priv->rf_type == RF_1T2R)
ratr_value &= ~(RATE_ALL_OFDM_2SS);
ratr_value &= ~(RATE_ALL_OFDM_2SS);
rtl92e_writel(dev, RATR0, ratr_value);
rtl92e_writeb(dev, UFWP, 1);
if (priv->tx_pwr_tracking_init && priv->btxpower_tracking)
@ -1087,7 +998,6 @@ void rtl92e_dm_backup_state(struct net_device *dev)
u32 bit_mask = bMaskByte0;
priv->bswitch_fsync = false;
priv->bfsync_processing = false;
if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
return;
@ -1619,16 +1529,6 @@ static void _rtl92e_dm_cts_to_self(struct net_device *dev)
}
}
static void _rtl92e_dm_init_wa_broadcom_iot(struct net_device *dev)
{
struct r8192_priv *priv = rtllib_priv((struct net_device *)dev);
struct rt_hi_throughput *ht_info = priv->rtllib->ht_info;
ht_info->bWAIotBroadcom = false;
ht_info->WAIotTH = WA_IOT_TH_VAL;
}
static void _rtl92e_dm_check_rf_ctrl_gpio(void *data)
{
struct r8192_priv *priv = container_of_dwork_rsl(data,
@ -1638,15 +1538,11 @@ static void _rtl92e_dm_check_rf_ctrl_gpio(void *data)
enum rt_rf_power_state rf_power_state_to_set;
bool bActuallySet = false;
bActuallySet = false;
if ((priv->up_first_time == 1) || (priv->being_init_adapter))
return;
if (priv->bfirst_after_down) {
priv->bfirst_after_down = true;
if (priv->bfirst_after_down)
return;
}
tmp1byte = rtl92e_readb(dev, GPI);
@ -1730,9 +1626,6 @@ static void _rtl92e_dm_rx_path_sel_byrssi(struct net_device *dev)
static u8 disabled_rf_cnt, cck_Rx_Path_initialized;
u8 update_cck_rx_path;
if (priv->rf_type != RF_2T4R)
return;
if (!cck_Rx_Path_initialized) {
dm_rx_path_sel_table.cck_rx_path = (rtl92e_readb(dev, 0xa07)&0xf);
cck_Rx_Path_initialized = 1;
@ -1932,7 +1825,6 @@ static void _rtl92e_dm_init_fsync(struct net_device *dev)
priv->rtllib->fsync_firstdiff_ratethreshold = 100;
priv->rtllib->fsync_seconddiff_ratethreshold = 200;
priv->rtllib->fsync_state = Default_Fsync;
priv->frame_sync_monitor = 1;
timer_setup(&priv->fsync_timer, _rtl92e_dm_fsync_timer_callback, 0);
}
@ -2159,12 +2051,10 @@ static void _rtl92e_dm_check_fsync(struct net_device *dev)
}
}
if (priv->frame_sync_monitor) {
if (reg_c38_State != RegC38_Fsync_AP_BCM) {
rtl92e_writeb(dev, rOFDM0_RxDetector3, 0x95);
if (reg_c38_State != RegC38_Fsync_AP_BCM) {
rtl92e_writeb(dev, rOFDM0_RxDetector3, 0x95);
reg_c38_State = RegC38_Fsync_AP_BCM;
}
reg_c38_State = RegC38_Fsync_AP_BCM;
}
} else {
switch (priv->rtllib->fsync_state) {
@ -2181,50 +2071,40 @@ static void _rtl92e_dm_check_fsync(struct net_device *dev)
break;
}
if (priv->frame_sync_monitor) {
if (priv->rtllib->state == RTLLIB_LINKED) {
if (priv->undecorated_smoothed_pwdb <=
RegC38_TH) {
if (reg_c38_State !=
RegC38_NonFsync_Other_AP) {
rtl92e_writeb(dev,
rOFDM0_RxDetector3,
0x90);
if (priv->rtllib->state == RTLLIB_LINKED) {
if (priv->undecorated_smoothed_pwdb <=
RegC38_TH) {
if (reg_c38_State !=
RegC38_NonFsync_Other_AP) {
rtl92e_writeb(dev,
rOFDM0_RxDetector3,
0x90);
reg_c38_State =
RegC38_NonFsync_Other_AP;
}
} else if (priv->undecorated_smoothed_pwdb >=
(RegC38_TH+5)) {
if (reg_c38_State) {
rtl92e_writeb(dev,
rOFDM0_RxDetector3,
priv->framesync);
reg_c38_State = RegC38_Default;
}
reg_c38_State =
RegC38_NonFsync_Other_AP;
}
} else {
} else if (priv->undecorated_smoothed_pwdb >=
(RegC38_TH+5)) {
if (reg_c38_State) {
rtl92e_writeb(dev, rOFDM0_RxDetector3,
priv->framesync);
rtl92e_writeb(dev,
rOFDM0_RxDetector3,
priv->framesync);
reg_c38_State = RegC38_Default;
}
}
} else {
if (reg_c38_State) {
rtl92e_writeb(dev, rOFDM0_RxDetector3,
priv->framesync);
reg_c38_State = RegC38_Default;
}
}
}
if (priv->frame_sync_monitor) {
if (priv->reset_count != reset_cnt) {
rtl92e_writeb(dev, rOFDM0_RxDetector3,
priv->framesync);
reg_c38_State = RegC38_Default;
reset_cnt = priv->reset_count;
}
} else {
if (reg_c38_State) {
rtl92e_writeb(dev, rOFDM0_RxDetector3,
priv->framesync);
reg_c38_State = RegC38_Default;
}
if (priv->reset_count != reset_cnt) {
rtl92e_writeb(dev, rOFDM0_RxDetector3,
priv->framesync);
reg_c38_State = RegC38_Default;
reset_cnt = priv->reset_count;
}
}

6
drivers/staging/rtl8192e/rtl8192e/rtl_pci.c
View File

@ -39,7 +39,7 @@ bool rtl92e_check_adapter(struct pci_dev *pdev, struct net_device *dev)
revision_id = pdev->revision;
pci_read_config_word(pdev, 0x3C, &irq_line);
priv->card_8192 = priv->ops->nic_type;
priv->card_8192 = NIC_8192E;
if (device_id == 0x8192) {
switch (revision_id) {
@ -64,10 +64,10 @@ bool rtl92e_check_adapter(struct pci_dev *pdev, struct net_device *dev)
}
}
if (priv->ops->nic_type != priv->card_8192) {
if (priv->card_8192 != NIC_8192E) {
dev_info(&pdev->dev,
"Detect info(%x) and hardware info(%x) not match!\n",
priv->ops->nic_type, priv->card_8192);
NIC_8192E, priv->card_8192);
dev_info(&pdev->dev,
"Please select proper driver before install!!!!\n");
return false;

3
drivers/staging/rtl8192e/rtl8192e/rtl_ps.c
View File

@ -142,8 +142,7 @@ void rtl92e_ips_leave(struct net_device *dev)
void rtl92e_ips_leave_wq(void *data)
{
struct rtllib_device *ieee = container_of_work_rsl(data,
struct rtllib_device, ips_leave_wq);
struct rtllib_device *ieee = container_of(data, struct rtllib_device, ips_leave_wq);
struct net_device *dev = ieee->dev;
struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);

8
drivers/staging/rtl8192e/rtl8192e/rtl_wx.c
View File

@ -432,15 +432,11 @@ static int _rtl92e_wx_set_scan(struct net_device *dev,
if (priv->rtllib->rf_power_state != rf_off) {
priv->rtllib->actscanning = true;
if (ieee->ScanOperationBackupHandler)
ieee->ScanOperationBackupHandler(ieee->dev,
SCAN_OPT_BACKUP);
ieee->ScanOperationBackupHandler(ieee->dev, SCAN_OPT_BACKUP);
rtllib_start_scan_syncro(priv->rtllib, 0);
if (ieee->ScanOperationBackupHandler)
ieee->ScanOperationBackupHandler(ieee->dev,
SCAN_OPT_RESTORE);
ieee->ScanOperationBackupHandler(ieee->dev, SCAN_OPT_RESTORE);
}
ret = 0;
} else {

22
drivers/staging/rtl8192e/rtl8192e/r8192E_hwimg.c → drivers/staging/rtl8192e/rtl8192e/table.c
View File

@ -4,11 +4,9 @@
*
* Contact Information: wlanfae <wlanfae@realtek.com>
*/
#include "r8192E_hwimg.h"
#include "table.h"
u32 Rtl8192PciEPHY_REGArray[PHY_REGArrayLengthPciE] = {0x0,};
u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLengthPciE] = {
u32 RTL8192E_PHY_REG_1T2R_ARR[RTL8192E_PHY_REG_1T2R_ARR_LEN] = {
0x800, 0x00000000,
0x804, 0x00000001,
0x808, 0x0000fc00,
@ -159,7 +157,7 @@ u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLengthPciE] = {
0xe1c, 0x12121416,
};
u32 Rtl8192PciERadioA_Array[RadioA_ArrayLengthPciE] = {
u32 RTL8192E_RADIO_A_ARR[RTL8192E_RADIO_A_ARR_LEN] = {
0x019, 0x00000003,
0x000, 0x000000bf,
0x001, 0x00000ee0,
@ -285,7 +283,7 @@ u32 Rtl8192PciERadioA_Array[RadioA_ArrayLengthPciE] = {
0x007, 0x00000700,
};
u32 Rtl8192PciERadioB_Array[RadioB_ArrayLengthPciE] = {
u32 RTL8192E_RADIO_B_ARR[RTL8192E_RADIO_B_ARR_LEN] = {
0x019, 0x00000003,
0x000, 0x000000bf,
0x001, 0x000006e0,
@ -327,13 +325,7 @@ u32 Rtl8192PciERadioB_Array[RadioB_ArrayLengthPciE] = {
0x007, 0x00000700,
};
u32 Rtl8192PciERadioC_Array[RadioC_ArrayLengthPciE] = {
0x0, };
u32 Rtl8192PciERadioD_Array[RadioD_ArrayLengthPciE] = {
0x0, };
u32 Rtl8192PciEMACPHY_Array[] = {
u32 RTL8192E_MACPHY_ARR[] = {
0x03c, 0xffff0000, 0x00000f0f,
0x340, 0xffffffff, 0x161a1a1a,
0x344, 0xffffffff, 0x12121416,
@ -342,7 +334,7 @@ u32 Rtl8192PciEMACPHY_Array[] = {
0x318, 0x00000fff, 0x00000100,
};
u32 Rtl8192PciEMACPHY_Array_PG[] = {
u32 RTL8192E_MACPHY_ARR_PG[] = {
0x03c, 0xffff0000, 0x00000f0f,
0xe00, 0xffffffff, 0x06090909,
0xe04, 0xffffffff, 0x00030306,
@ -355,7 +347,7 @@ u32 Rtl8192PciEMACPHY_Array_PG[] = {
0x318, 0x00000fff, 0x00000800,
};
u32 Rtl8192PciEAGCTAB_Array[AGCTAB_ArrayLengthPciE] = {
u32 RTL8192E_AGCTAB_ARR[RTL8192E_AGCTAB_ARR_LEN] = {
0xc78, 0x7d000001,
0xc78, 0x7d010001,
0xc78, 0x7d020001,

27
drivers/staging/rtl8192e/rtl8192e/table.h Normal file
View File

@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
*
* Contact Information: wlanfae <wlanfae@realtek.com>
*/
#ifndef __INC_HAL8192PciE_FW_IMG_H
#define __INC_HAL8192PciE_FW_IMG_H
/*Created on 2008/11/18, 3: 7*/
#include <linux/types.h>
#define RTL8192E_PHY_REG_1T2R_ARR_LEN 296
extern u32 RTL8192E_PHY_REG_1T2R_ARR[RTL8192E_PHY_REG_1T2R_ARR_LEN];
#define RTL8192E_RADIO_A_ARR_LEN 246
extern u32 RTL8192E_RADIO_A_ARR[RTL8192E_RADIO_A_ARR_LEN];
#define RTL8192E_RADIO_B_ARR_LEN 78
extern u32 RTL8192E_RADIO_B_ARR[RTL8192E_RADIO_B_ARR_LEN];
#define RTL8192E_MACPHY_ARR_LEN 18
extern u32 RTL8192E_MACPHY_ARR[RTL8192E_MACPHY_ARR_LEN];
#define RTL8192E_MACPHY_ARR_PG_LEN 30
extern u32 RTL8192E_MACPHY_ARR_PG[RTL8192E_MACPHY_ARR_PG_LEN];
#define RTL8192E_AGCTAB_ARR_LEN 384
extern u32 RTL8192E_AGCTAB_ARR[RTL8192E_AGCTAB_ARR_LEN];
#endif

3
drivers/staging/rtl8192e/rtl819x_HT.h
View File

@ -162,9 +162,6 @@ struct rt_hi_throughput {
u8 IOTPeer;
u32 iot_action;
u8 iot_ra_func;
u8 bWAIotBroadcom;
u8 WAIotTH;
} __packed;
struct bss_ht {

3
drivers/staging/rtl8192e/rtl819x_TSProc.c
View File

@ -517,6 +517,7 @@ void TsStartAddBaProcess(struct rtllib_device *ieee, struct tx_ts_record *pTxTS)
netdev_dbg(ieee->dev, "Immediately Start ADDBA\n");
mod_timer(&pTxTS->TsAddBaTimer, jiffies + 10);
}
} else
} else {
netdev_dbg(ieee->dev, "BA timer is already added\n");
}
}

44
drivers/staging/rtl8192e/rtllib.h
View File

@ -62,24 +62,9 @@
#define IW_CUSTOM_MAX 256 /* In bytes */
#endif
#define skb_tail_pointer_rsl(skb) skb_tail_pointer(skb)
#define queue_delayed_work_rsl(x, y, z) queue_delayed_work(x, y, z)
#define INIT_DELAYED_WORK_RSL(x, y, z) INIT_DELAYED_WORK(x, y)
#define queue_work_rsl(x, y) queue_work(x, y)
#define INIT_WORK_RSL(x, y, z) INIT_WORK(x, y)
#define container_of_work_rsl(x, y, z) container_of(x, y, z)
#define container_of_dwork_rsl(x, y, z) \
container_of(to_delayed_work(x), y, z)
#define iwe_stream_add_event_rsl(info, start, stop, iwe, len) \
iwe_stream_add_event(info, start, stop, iwe, len)
#define iwe_stream_add_point_rsl(info, start, stop, iwe, p) \
iwe_stream_add_point(info, start, stop, iwe, p)
static inline void *netdev_priv_rsl(struct net_device *dev)
{
return netdev_priv(dev);
@ -115,7 +100,6 @@ static inline void *netdev_priv_rsl(struct net_device *dev)
((psc->CurPsLevel & _PS_FLAG) ? true : false)
#define RT_CLEAR_PS_LEVEL(psc, _PS_FLAG) \
(psc->CurPsLevel &= (~(_PS_FLAG)))
#define RT_SET_PS_LEVEL(psc, _PS_FLAG) (psc->CurPsLevel |= _PS_FLAG)
/* defined for skb cb field */
/* At most 28 byte */
@ -323,7 +307,6 @@ enum rt_op_mode {
RT_OP_MODE_NO_LINK,
};
#define aSifsTime \
(((priv->rtllib->current_network.mode == IEEE_A) \
|| (priv->rtllib->current_network.mode == IEEE_N_24G) \
@ -449,11 +432,6 @@ enum led_ctl_mode {
LED_CTL_START_TO_LINK = 8,
};
enum rt_rf_type_def {
RF_1T2R = 0,
RF_2T4R,
};
enum wireless_mode {
WIRELESS_MODE_UNKNOWN = 0x00,
WIRELESS_MODE_A = 0x01,
@ -669,7 +647,6 @@ struct rtllib_security {
u16 flags;
} __packed;
/* 802.11 data frame from AP
* ,-------------------------------------------------------------------.
* Bytes | 2 | 2 | 6 | 6 | 6 | 2 | 0..2312 | 4 |
@ -989,6 +966,7 @@ static inline const char *eap_get_type(int type)
return ((u32)type >= ARRAY_SIZE(eap_types)) ? "Unknown" :
eap_types[type];
}
static inline u8 Frame_QoSTID(u8 *buf)
{
struct rtllib_hdr_3addr *hdr;
@ -1000,7 +978,6 @@ static inline u8 Frame_QoSTID(u8 *buf)
(fc & RTLLIB_FCTL_FROMDS)) ? 30 : 24)))->field.tid;
}
struct eapol {
u8 snap[6];
u16 ethertype;
@ -1215,8 +1192,6 @@ struct bandwidth_autoswitch {
bool bautoswitch_enable;
};
#define REORDER_WIN_SIZE 128
#define REORDER_ENTRY_NUM 128
struct rx_reorder_entry {
@ -1224,6 +1199,7 @@ struct rx_reorder_entry {
u16 SeqNum;
struct rtllib_rxb *prxb;
};
enum fsync_state {
Default_Fsync,
HW_Fsync,
@ -1260,7 +1236,6 @@ struct rt_pwr_save_ctrl {
u8 LPSAwakeIntvl;
u32 CurPsLevel;
u32 RegRfPsLevel;
};
#define RT_RF_CHANGE_SOURCE u32
@ -1350,6 +1325,7 @@ struct sw_cam_table {
u8 key_index;
};
#define TOTAL_CAM_ENTRY 32
struct rate_adaptive {
u8 rate_adaptive_disabled;
@ -1388,7 +1364,6 @@ struct rt_intel_promisc_mode {
bool fltr_src_sta_frame;
};
/*************** DRIVER STATUS *****/
#define STATUS_SCANNING 0
/*************** DRIVER STATUS *****/
@ -1416,7 +1391,6 @@ struct rtllib_device {
size_t assocreq_ies_len, assocresp_ies_len;
bool bForcedBgMode;
u8 RF_Type;
u8 hwsec_active;
bool is_silent_reset;
@ -1457,7 +1431,6 @@ struct rtllib_device {
struct rx_reorder_entry RxReorderEntry[128];
struct list_head RxReorder_Unused_List;
/* Bookkeeping structures */
struct net_device_stats stats;
struct rtllib_softmac_stats softmac_stats;
@ -1754,7 +1727,6 @@ struct rtllib_device {
struct rtllib_assoc_response_frame *resp,
struct rtllib_network *network);
/* check whether Tx hw resource available */
short (*check_nic_enough_desc)(struct net_device *dev, int queue_index);
void (*SetBWModeHandler)(struct net_device *dev,
@ -1827,7 +1799,6 @@ struct rtllib_device {
*/
#define IEEE_SOFTMAC_BEACONS (1<<6)
static inline void *rtllib_priv(struct net_device *dev)
{
return ((struct rtllib_device *)netdev_priv(dev))->priv;
@ -1919,17 +1890,15 @@ static inline int rtllib_is_cck_rate(u8 rate)
return 0;
}
/* rtllib.c */
void free_rtllib(struct net_device *dev);
struct net_device *alloc_rtllib(int sizeof_priv);
/* rtllib_tx.c */
int rtllib_encrypt_fragment(
struct rtllib_device *ieee,
struct sk_buff *frag,
int hdr_len);
int rtllib_encrypt_fragment(struct rtllib_device *ieee,
struct sk_buff *frag,
int hdr_len);
netdev_tx_t rtllib_xmit(struct sk_buff *skb, struct net_device *dev);
void rtllib_txb_free(struct rtllib_txb *txb);
@ -2129,7 +2098,6 @@ static inline const char *escape_essid(const char *essid, u8 essid_len)
/* fun with the built-in rtllib stack... */
bool rtllib_MgntDisconnect(struct rtllib_device *rtllib, u8 asRsn);
/* For the function is more related to hardware setting, it's better to use the
* ieee handler to refer to it.
*/

32
drivers/staging/rtl8192e/rtllib_crypt_ccmp.c
View File

@ -34,9 +34,9 @@ struct rtllib_ccmp_data {
u8 tx_pn[CCMP_PN_LEN];
u8 rx_pn[CCMP_PN_LEN];
u32 dot11RSNAStatsCCMPFormatErrors;
u32 dot11RSNAStatsCCMPReplays;
u32 dot11RSNAStatsCCMPDecryptErrors;
u32 dot11rsna_stats_ccmp_format_errors;
u32 dot11rsna_stats_ccmp_replays;
u32 dot11rsna_stats_ccmp_decrypt_errors;
int key_idx;
@ -74,7 +74,6 @@ fail:
return NULL;
}
static void rtllib_ccmp_deinit(void *priv)
{
struct rtllib_ccmp_data *_priv = priv;
@ -84,7 +83,6 @@ static void rtllib_ccmp_deinit(void *priv)
kfree(priv);
}
static int ccmp_init_iv_and_aad(struct rtllib_hdr_4addr *hdr,
u8 *pn, u8 *iv, u8 *aad)
{
@ -150,8 +148,6 @@ static int ccmp_init_iv_and_aad(struct rtllib_hdr_4addr *hdr,
return aad_len;
}
static int rtllib_ccmp_encrypt(struct sk_buff *skb, int hdr_len, void *priv)
{
struct rtllib_ccmp_data *key = priv;
@ -220,7 +216,6 @@ static int rtllib_ccmp_encrypt(struct sk_buff *skb, int hdr_len, void *priv)
return 0;
}
static int rtllib_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv)
{
struct rtllib_ccmp_data *key = priv;
@ -231,7 +226,7 @@ static int rtllib_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv)
u8 pn[6];
if (skb->len < hdr_len + CCMP_HDR_LEN + CCMP_MIC_LEN) {
key->dot11RSNAStatsCCMPFormatErrors++;
key->dot11rsna_stats_ccmp_format_errors++;
return -1;
}
@ -243,7 +238,7 @@ static int rtllib_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv)
pr_debug("CCMP: received packet without ExtIV flag from %pM\n",
hdr->addr2);
}
key->dot11RSNAStatsCCMPFormatErrors++;
key->dot11rsna_stats_ccmp_format_errors++;
return -2;
}
keyidx >>= 6;
@ -268,7 +263,7 @@ static int rtllib_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv)
pn[5] = pos[0];
pos += 8;
if (memcmp(pn, key->rx_pn, CCMP_PN_LEN) <= 0) {
key->dot11RSNAStatsCCMPReplays++;
key->dot11rsna_stats_ccmp_replays++;
return -4;
}
if (!tcb_desc->bHwSec) {
@ -301,7 +296,7 @@ static int rtllib_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv)
pr_debug("CCMP: decrypt failed: STA= %pM\n",
hdr->addr2);
}
key->dot11RSNAStatsCCMPDecryptErrors++;
key->dot11rsna_stats_ccmp_decrypt_errors++;
return -5;
}
@ -315,7 +310,6 @@ static int rtllib_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv)
return keyidx;
}
static int rtllib_ccmp_set_key(void *key, int len, u8 *seq, void *priv)
{
struct rtllib_ccmp_data *data = priv;
@ -338,7 +332,7 @@ static int rtllib_ccmp_set_key(void *key, int len, u8 *seq, void *priv)
data->rx_pn[5] = seq[0];
}
if (crypto_aead_setauthsize(data->tfm, CCMP_MIC_LEN) ||
crypto_aead_setkey(data->tfm, data->key, CCMP_TK_LEN))
crypto_aead_setkey(data->tfm, data->key, CCMP_TK_LEN))
return -1;
} else if (len == 0) {
data->key_set = 0;
@ -349,7 +343,6 @@ static int rtllib_ccmp_set_key(void *key, int len, u8 *seq, void *priv)
return 0;
}
static int rtllib_ccmp_get_key(void *key, int len, u8 *seq, void *priv)
{
struct rtllib_ccmp_data *data = priv;
@ -373,7 +366,6 @@ static int rtllib_ccmp_get_key(void *key, int len, u8 *seq, void *priv)
return CCMP_TK_LEN;
}
static void rtllib_ccmp_print_stats(struct seq_file *m, void *priv)
{
struct rtllib_ccmp_data *ccmp = priv;
@ -382,9 +374,9 @@ static void rtllib_ccmp_print_stats(struct seq_file *m, void *priv)
"key[%d] alg=CCMP key_set=%d tx_pn=%pM rx_pn=%pM format_errors=%d replays=%d decrypt_errors=%d\n",
ccmp->key_idx, ccmp->key_set,
ccmp->tx_pn, ccmp->rx_pn,
ccmp->dot11RSNAStatsCCMPFormatErrors,
ccmp->dot11RSNAStatsCCMPReplays,
ccmp->dot11RSNAStatsCCMPDecryptErrors);
ccmp->dot11rsna_stats_ccmp_format_errors,
ccmp->dot11rsna_stats_ccmp_replays,
ccmp->dot11rsna_stats_ccmp_decrypt_errors);
}
static struct lib80211_crypto_ops rtllib_crypt_ccmp = {
@ -403,13 +395,11 @@ static struct lib80211_crypto_ops rtllib_crypt_ccmp = {
.owner = THIS_MODULE,
};
static int __init rtllib_crypto_ccmp_init(void)
{
return lib80211_register_crypto_ops(&rtllib_crypt_ccmp);
}
static void __exit rtllib_crypto_ccmp_exit(void)
{
lib80211_unregister_crypto_ops(&rtllib_crypt_ccmp);

80
drivers/staging/rtl8192e/rtllib_rx.c
View File

@ -154,7 +154,6 @@ rtllib_frag_cache_get(struct rtllib_device *ieee,
return skb;
}
/* Called only as a tasklet (software IRQ) */
static int rtllib_frag_cache_invalidate(struct rtllib_device *ieee,
struct rtllib_hdr_4addr *hdr)
@ -232,10 +231,12 @@ rtllib_rx_frame_mgmt(struct rtllib_device *ieee, struct sk_buff *skb,
static unsigned char rfc1042_header[] = {
0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00
};
/* Bridge-Tunnel header (for EtherTypes ETH_P_AARP and ETH_P_IPX) */
static unsigned char bridge_tunnel_header[] = {
0xaa, 0xaa, 0x03, 0x00, 0x00, 0xf8
};
/* No encapsulation header if EtherType < 0x600 (=length) */
/* Called by rtllib_rx_frame_decrypt */
@ -318,7 +319,6 @@ rtllib_rx_frame_decrypt(struct rtllib_device *ieee, struct sk_buff *skb,
return res;
}
/* Called only as a tasklet (software IRQ), by rtllib_rx */
static inline int
rtllib_rx_frame_decrypt_msdu(struct rtllib_device *ieee, struct sk_buff *skb,
@ -355,9 +355,8 @@ rtllib_rx_frame_decrypt_msdu(struct rtllib_device *ieee, struct sk_buff *skb,
return 0;
}
/* this function is stolen from ipw2200 driver*/
#define IEEE_PACKET_RETRY_TIME (5*HZ)
#define IEEE_PACKET_RETRY_TIME (5 * HZ)
static int is_duplicate_packet(struct rtllib_device *ieee,
struct rtllib_hdr_4addr *header)
{
@ -887,7 +886,6 @@ static u8 parse_subframe(struct rtllib_device *ieee, struct sk_buff *skb,
return rxb->nr_subframes;
}
static size_t rtllib_rx_get_hdrlen(struct rtllib_device *ieee,
struct sk_buff *skb,
struct rtllib_rx_stats *rx_stats)
@ -938,7 +936,7 @@ static int rtllib_rx_check_duplicate(struct rtllib_device *ieee,
if (GetTs(ieee, (struct ts_common_info **)&pRxTS, hdr->addr2,
(u8)Frame_QoSTID((u8 *)(skb->data)), RX_DIR, true)) {
if ((fc & (1<<11)) && (frag == pRxTS->rx_last_frag_num) &&
if ((fc & (1 << 11)) && (frag == pRxTS->rx_last_frag_num) &&
(WLAN_GET_SEQ_SEQ(sc) == pRxTS->rx_last_seq_num))
return -1;
pRxTS->rx_last_frag_num = frag;
@ -1169,7 +1167,6 @@ static int rtllib_rx_decrypt(struct rtllib_device *ieee, struct sk_buff *skb,
if (crypt && !(fc & RTLLIB_FCTL_WEP) && !ieee->open_wep) {
if (/*ieee->ieee802_1x &&*/
rtllib_is_eapol_frame(ieee, skb, hdrlen)) {
/* pass unencrypted EAPOL frames even if encryption is
* configured
*/
@ -1209,13 +1206,11 @@ static void rtllib_rx_check_leave_lps(struct rtllib_device *ieee, u8 unicast,
u8 nr_subframes)
{
if (unicast) {
if (ieee->state == RTLLIB_LINKED) {
if (((ieee->link_detect_info.NumRxUnicastOkInPeriod +
ieee->link_detect_info.NumTxOkInPeriod) > 8) ||
(ieee->link_detect_info.NumRxUnicastOkInPeriod > 2)) {
if (ieee->LeisurePSLeave)
ieee->LeisurePSLeave(ieee->dev);
ieee->LeisurePSLeave(ieee->dev);
}
}
}
@ -1555,7 +1550,6 @@ static u8 qos_oui[QOS_OUI_LEN] = { 0x00, 0x50, 0xF2 };
static int rtllib_verify_qos_info(struct rtllib_qos_information_element
*info_element, int sub_type)
{
if (info_element->elementID != QOS_ELEMENT_ID)
return -1;
if (info_element->qui_subtype != sub_type)
@ -1570,7 +1564,6 @@ static int rtllib_verify_qos_info(struct rtllib_qos_information_element
return 0;
}
/* Parse a QoS parameter element */
static int rtllib_read_qos_param_element(
struct rtllib_qos_parameter_info *element_param,
@ -1600,7 +1593,6 @@ static int rtllib_read_qos_info_element(
return rtllib_verify_qos_info(element_info, QOS_OUI_INFO_SUB_TYPE);
}
/* Write QoS parameters from the ac parameters. */
static int rtllib_qos_convert_ac_to_parameters(struct rtllib_qos_parameter_info *param_elm,
struct rtllib_qos_data *qos_data)
@ -1624,23 +1616,23 @@ static int rtllib_qos_convert_ac_to_parameters(struct rtllib_qos_parameter_info
case 1:
/* BIT(0) | BIT(3) */
if (acm)
qos_data->wmm_acm |= (0x01<<0)|(0x01<<3);
qos_data->wmm_acm |= (0x01 << 0) | (0x01 << 3);
break;
case 2:
/* BIT(4) | BIT(5) */
if (acm)
qos_data->wmm_acm |= (0x01<<4)|(0x01<<5);
qos_data->wmm_acm |= (0x01 << 4) | (0x01 << 5);
break;
case 3:
/* BIT(6) | BIT(7) */
if (acm)
qos_data->wmm_acm |= (0x01<<6)|(0x01<<7);
qos_data->wmm_acm |= (0x01 << 6) | (0x01 << 7);
break;
case 0:
default:
/* BIT(1) | BIT(2) */
if (acm)
qos_data->wmm_acm |= (0x01<<1)|(0x01<<2);
qos_data->wmm_acm |= (0x01 << 1) | (0x01 << 2);
break;
}
@ -1844,7 +1836,6 @@ static void rtllib_parse_mife_generic(struct rtllib_device *ieee,
}
}
if (*tmp_htinfo_len == 0) {
if (info_element->len >= 4 &&
info_element->data[0] == 0x00 &&
@ -1933,7 +1924,6 @@ static void rtllib_parse_mife_generic(struct rtllib_device *ieee,
info_element->data[2] == 0x96)
network->cisco_cap_exist = true;
if (info_element->len >= 3 &&
info_element->data[0] == 0x00 &&
info_element->data[1] == 0x0a &&
@ -1986,7 +1976,7 @@ static void rtllib_parse_mife_generic(struct rtllib_device *ieee,
info_element->data[3] == 0x04) {
netdev_dbg(ieee->dev, "MFIE_TYPE_WZC: %d bytes\n",
info_element->len);
network->wzc_ie_len = min(info_element->len+2, MAX_WZC_IE_LEN);
network->wzc_ie_len = min(info_element->len + 2, MAX_WZC_IE_LEN);
memcpy(network->wzc_ie, info_element, network->wzc_ie_len);
}
}
@ -2143,15 +2133,13 @@ int rtllib_parse_info_param(struct rtllib_device *ieee,
network->dtim_data = RTLLIB_DTIM_VALID;
if (info_element->data[2] & 1)
network->dtim_data |= RTLLIB_DTIM_MBCAST;
offset = (info_element->data[2] >> 1)*2;
offset = (info_element->data[2] >> 1) * 2;
if (ieee->assoc_id < 8*offset ||
ieee->assoc_id > 8*(offset + info_element->len - 3))
if (ieee->assoc_id < 8 * offset ||
ieee->assoc_id > 8 * (offset + info_element->len - 3))
break;
offset = (ieee->assoc_id / 8) - offset;
@ -2204,7 +2192,6 @@ int rtllib_parse_info_param(struct rtllib_device *ieee,
&tmp_htcap_len);
break;
case MFIE_TYPE_HT_INFO:
netdev_dbg(ieee->dev, "MFIE_TYPE_HT_INFO: %d bytes\n",
info_element->len);
@ -2367,7 +2354,7 @@ static inline int rtllib_network_init(
if (rtllib_is_empty_essid(network->ssid, network->ssid_len))
network->flags |= NETWORK_EMPTY_ESSID;
stats->signal = 30 + (stats->SignalStrength * 70) / 100;
stats->noise = rtllib_translate_todbm((u8)(100-stats->signal)) - 25;
stats->noise = rtllib_translate_todbm((u8)(100 - stats->signal)) - 25;
memcpy(&network->stats, stats, sizeof(network->stats));
@ -2393,7 +2380,6 @@ static inline int is_same_network(struct rtllib_network *src,
(dst->capability & WLAN_CAPABILITY_ESS)));
}
static inline void update_network(struct rtllib_device *ieee,
struct rtllib_network *dst,
struct rtllib_network *src)
@ -2556,22 +2542,22 @@ static inline void rtllib_process_probe_response(
"'%s' ( %pM ): %c%c%c%c %c%c%c%c-%c%c%c%c %c%c%c%c\n",
escape_essid(info_element->data, info_element->len),
beacon->header.addr3,
(le16_to_cpu(beacon->capability) & (1<<0xf)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1<<0xe)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1<<0xd)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1<<0xc)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1<<0xb)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1<<0xa)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1<<0x9)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1<<0x8)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1<<0x7)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1<<0x6)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1<<0x5)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1<<0x4)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1<<0x3)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1<<0x2)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1<<0x1)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1<<0x0)) ? '1' : '0');
(le16_to_cpu(beacon->capability) & (1 << 0xf)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1 << 0xe)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1 << 0xd)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1 << 0xc)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1 << 0xb)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1 << 0xa)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1 << 0x9)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1 << 0x8)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1 << 0x7)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1 << 0x6)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1 << 0x5)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1 << 0x4)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1 << 0x3)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1 << 0x2)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1 << 0x1)) ? '1' : '0',
(le16_to_cpu(beacon->capability) & (1 << 0x0)) ? '1' : '0');
if (rtllib_network_init(ieee, beacon, network, stats)) {
netdev_dbg(ieee->dev, "Dropped '%s' ( %pM) via %s.\n",
@ -2581,7 +2567,6 @@ static inline void rtllib_process_probe_response(
goto free_network;
}
if (!rtllib_legal_channel(ieee, network->channel))
goto free_network;
@ -2689,9 +2674,7 @@ static inline void rtllib_process_probe_response(
is_same_network(&ieee->current_network, network,
(network->ssid_len ? 1 : 0)) &&
(ieee->state == RTLLIB_LINKED)) {
if (ieee->handle_beacon != NULL)
ieee->handle_beacon(ieee->dev, beacon,
&ieee->current_network);
ieee->handle_beacon(ieee->dev, beacon, &ieee->current_network);
}
free_network:
kfree(network);
@ -2710,7 +2693,6 @@ static void rtllib_rx_mgt(struct rtllib_device *ieee,
ieee->last_rx_ps_time = jiffies;
switch (WLAN_FC_GET_STYPE(le16_to_cpu(header->frame_ctl))) {
case RTLLIB_STYPE_BEACON:
netdev_dbg(ieee->dev, "received BEACON (%d)\n",
WLAN_FC_GET_STYPE(le16_to_cpu(header->frame_ctl)));

47
drivers/staging/rtl8192e/rtllib_softmac.c
View File

@ -659,8 +659,7 @@ static void rtllib_beacons_stop(struct rtllib_device *ieee)
void rtllib_stop_send_beacons(struct rtllib_device *ieee)
{
if (ieee->stop_send_beacons)
ieee->stop_send_beacons(ieee->dev);
ieee->stop_send_beacons(ieee->dev);
if (ieee->softmac_features & IEEE_SOFTMAC_BEACONS)
rtllib_beacons_stop(ieee);
}
@ -669,8 +668,7 @@ EXPORT_SYMBOL(rtllib_stop_send_beacons);
void rtllib_start_send_beacons(struct rtllib_device *ieee)
{
if (ieee->start_send_beacons)
ieee->start_send_beacons(ieee->dev);
ieee->start_send_beacons(ieee->dev);
if (ieee->softmac_features & IEEE_SOFTMAC_BEACONS)
rtllib_beacons_start(ieee);
}
@ -729,8 +727,7 @@ EXPORT_SYMBOL(rtllib_act_scanning);
/* called with ieee->lock held */
static void rtllib_start_scan(struct rtllib_device *ieee)
{
if (ieee->rtllib_ips_leave_wq != NULL)
ieee->rtllib_ips_leave_wq(ieee->dev);
ieee->rtllib_ips_leave_wq(ieee->dev);
if (IS_DOT11D_ENABLE(ieee)) {
if (IS_COUNTRY_IE_VALID(ieee))
@ -1501,7 +1498,7 @@ static void rtllib_associate_step2(struct rtllib_device *ieee)
static void rtllib_associate_complete_wq(void *data)
{
struct rtllib_device *ieee = (struct rtllib_device *)
container_of_work_rsl(data,
container_of(data,
struct rtllib_device,
associate_complete_wq);
struct rt_pwr_save_ctrl *psc = &ieee->pwr_save_ctrl;
@ -1575,8 +1572,7 @@ static void rtllib_associate_procedure_wq(void *data)
struct rtllib_device,
associate_procedure_wq);
rtllib_stop_scan_syncro(ieee);
if (ieee->rtllib_ips_leave != NULL)
ieee->rtllib_ips_leave(ieee->dev);
ieee->rtllib_ips_leave(ieee->dev);
mutex_lock(&ieee->wx_mutex);
if (ieee->data_hard_stop)
@ -1585,8 +1581,7 @@ static void rtllib_associate_procedure_wq(void *data)
rtllib_stop_scan(ieee);
HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT);
if (ieee->rf_power_state == rf_off) {
if (ieee->rtllib_ips_leave_wq != NULL)
ieee->rtllib_ips_leave_wq(ieee->dev);
ieee->rtllib_ips_leave_wq(ieee->dev);
mutex_unlock(&ieee->wx_mutex);
return;
}
@ -2241,10 +2236,8 @@ rtllib_rx_assoc_resp(struct rtllib_device *ieee, struct sk_buff *skb,
memcpy(ieee->ht_info->PeerHTInfoBuf,
network->bssht.bd_ht_info_buf,
network->bssht.bd_ht_info_len);
if (ieee->handle_assoc_response != NULL)
ieee->handle_assoc_response(ieee->dev,
(struct rtllib_assoc_response_frame *)header,
network);
ieee->handle_assoc_response(ieee->dev,
(struct rtllib_assoc_response_frame *)header, network);
}
kfree(network);
@ -2856,8 +2849,7 @@ void rtllib_stop_protocol(struct rtllib_device *ieee, u8 shutdown)
if (shutdown) {
ieee->proto_started = 0;
ieee->proto_stoppping = 1;
if (ieee->rtllib_ips_leave != NULL)
ieee->rtllib_ips_leave(ieee->dev);
ieee->rtllib_ips_leave(ieee->dev);
}
rtllib_stop_send_beacons(ieee);
@ -3004,20 +2996,13 @@ int rtllib_softmac_init(struct rtllib_device *ieee)
timer_setup(&ieee->beacon_timer, rtllib_send_beacon_cb, 0);
INIT_DELAYED_WORK_RSL(&ieee->link_change_wq,
(void *)rtllib_link_change_wq, ieee);
INIT_DELAYED_WORK_RSL(&ieee->start_ibss_wq,
(void *)rtllib_start_ibss_wq, ieee);
INIT_WORK_RSL(&ieee->associate_complete_wq,
(void *)rtllib_associate_complete_wq, ieee);
INIT_DELAYED_WORK_RSL(&ieee->associate_procedure_wq,
(void *)rtllib_associate_procedure_wq, ieee);
INIT_DELAYED_WORK_RSL(&ieee->softmac_scan_wq,
(void *)rtllib_softmac_scan_wq, ieee);
INIT_DELAYED_WORK_RSL(&ieee->associate_retry_wq,
(void *)rtllib_associate_retry_wq, ieee);
INIT_WORK_RSL(&ieee->wx_sync_scan_wq, (void *)rtllib_wx_sync_scan_wq,
ieee);
INIT_DELAYED_WORK(&ieee->link_change_wq, (void *)rtllib_link_change_wq);
INIT_DELAYED_WORK(&ieee->start_ibss_wq, (void *)rtllib_start_ibss_wq);
INIT_WORK(&ieee->associate_complete_wq, (void *)rtllib_associate_complete_wq);
INIT_DELAYED_WORK(&ieee->associate_procedure_wq, (void *)rtllib_associate_procedure_wq);
INIT_DELAYED_WORK(&ieee->softmac_scan_wq, (void *)rtllib_softmac_scan_wq);
INIT_DELAYED_WORK(&ieee->associate_retry_wq, (void *)rtllib_associate_retry_wq);
INIT_WORK(&ieee->wx_sync_scan_wq, (void *)rtllib_wx_sync_scan_wq);
mutex_init(&ieee->wx_mutex);
mutex_init(&ieee->scan_mutex);

12
drivers/staging/rtl8192e/rtllib_softmac_wx.c
View File

@ -326,8 +326,7 @@ EXPORT_SYMBOL(rtllib_wx_set_mode);
void rtllib_wx_sync_scan_wq(void *data)
{
struct rtllib_device *ieee = container_of_work_rsl(data,
struct rtllib_device, wx_sync_scan_wq);
struct rtllib_device *ieee = container_of(data, struct rtllib_device, wx_sync_scan_wq);
short chan;
enum ht_extchnl_offset chan_offset = 0;
enum ht_channel_width bandwidth = 0;
@ -340,8 +339,7 @@ void rtllib_wx_sync_scan_wq(void *data)
chan = ieee->current_network.channel;
if (ieee->LeisurePSLeave)
ieee->LeisurePSLeave(ieee->dev);
ieee->LeisurePSLeave(ieee->dev);
/* notify AP to be in PS mode */
rtllib_sta_ps_send_null_frame(ieee, 1);
rtllib_sta_ps_send_null_frame(ieee, 1);
@ -356,8 +354,7 @@ void rtllib_wx_sync_scan_wq(void *data)
/* wait for ps packet to be kicked out successfully */
msleep(50);
if (ieee->ScanOperationBackupHandler)
ieee->ScanOperationBackupHandler(ieee->dev, SCAN_OPT_BACKUP);
ieee->ScanOperationBackupHandler(ieee->dev, SCAN_OPT_BACKUP);
if (ieee->ht_info->bCurrentHTSupport && ieee->ht_info->enable_ht &&
ieee->ht_info->bCurBW40MHz) {
@ -382,8 +379,7 @@ void rtllib_wx_sync_scan_wq(void *data)
ieee->set_chan(ieee->dev, chan);
}
if (ieee->ScanOperationBackupHandler)
ieee->ScanOperationBackupHandler(ieee->dev, SCAN_OPT_RESTORE);
ieee->ScanOperationBackupHandler(ieee->dev, SCAN_OPT_RESTORE);
ieee->state = RTLLIB_LINKED;
ieee->link_change(ieee->dev);

42
drivers/staging/rtl8192e/rtllib_wx.c
View File

@ -41,8 +41,7 @@ static inline char *rtl819x_translate_scan(struct rtllib_device *ieee,
iwe.cmd = SIOCGIWAP;
iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
ether_addr_copy(iwe.u.ap_addr.sa_data, network->bssid);
start = iwe_stream_add_event_rsl(info, start, stop,
&iwe, IW_EV_ADDR_LEN);
start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_ADDR_LEN);
/* Remaining entries will be displayed in the order we provide them */
/* Add the ESSID */
@ -50,16 +49,13 @@ static inline char *rtl819x_translate_scan(struct rtllib_device *ieee,
iwe.u.data.flags = 1;
if (network->ssid_len > 0) {
iwe.u.data.length = min_t(u8, network->ssid_len, 32);
start = iwe_stream_add_point_rsl(info, start, stop, &iwe,
network->ssid);
start = iwe_stream_add_point(info, start, stop, &iwe, network->ssid);
} else if (network->hidden_ssid_len == 0) {
iwe.u.data.length = sizeof("<hidden>");
start = iwe_stream_add_point_rsl(info, start, stop,
&iwe, "<hidden>");
start = iwe_stream_add_point(info, start, stop, &iwe, "<hidden>");
} else {
iwe.u.data.length = min_t(u8, network->hidden_ssid_len, 32);
start = iwe_stream_add_point_rsl(info, start, stop, &iwe,
network->hidden_ssid);
start = iwe_stream_add_point(info, start, stop, &iwe, network->hidden_ssid);
}
/* Add the protocol name */
iwe.cmd = SIOCGIWNAME;
@ -71,8 +67,7 @@ static inline char *rtl819x_translate_scan(struct rtllib_device *ieee,
}
*pname = '\0';
snprintf(iwe.u.name, IFNAMSIZ, "IEEE802.11%s", proto_name);
start = iwe_stream_add_event_rsl(info, start, stop,
&iwe, IW_EV_CHAR_LEN);
start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_CHAR_LEN);
/* Add mode */
iwe.cmd = SIOCGIWMODE;
if (network->capability &
@ -81,8 +76,7 @@ static inline char *rtl819x_translate_scan(struct rtllib_device *ieee,
iwe.u.mode = IW_MODE_MASTER;
else
iwe.u.mode = IW_MODE_ADHOC;
start = iwe_stream_add_event_rsl(info, start, stop,
&iwe, IW_EV_UINT_LEN);
start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_UINT_LEN);
}
/* Add frequency/channel */
@ -90,8 +84,7 @@ static inline char *rtl819x_translate_scan(struct rtllib_device *ieee,
iwe.u.freq.m = network->channel;
iwe.u.freq.e = 0;
iwe.u.freq.i = 0;
start = iwe_stream_add_event_rsl(info, start, stop, &iwe,
IW_EV_FREQ_LEN);
start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_FREQ_LEN);
/* Add encryption capability */
iwe.cmd = SIOCGIWENCODE;
@ -100,8 +93,7 @@ static inline char *rtl819x_translate_scan(struct rtllib_device *ieee,
else
iwe.u.data.flags = IW_ENCODE_DISABLED;
iwe.u.data.length = 0;
start = iwe_stream_add_point_rsl(info, start, stop,
&iwe, network->ssid);
start = iwe_stream_add_point(info, start, stop, &iwe, network->ssid);
/* Add basic and extended rates */
max_rate = 0;
p = custom;
@ -152,12 +144,11 @@ static inline char *rtl819x_translate_scan(struct rtllib_device *ieee,
iwe.u.bitrate.disabled = 0;
iwe.u.bitrate.fixed = 0;
iwe.u.bitrate.value = max_rate * 500000;
start = iwe_stream_add_event_rsl(info, start, stop, &iwe, IW_EV_PARAM_LEN);
start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_PARAM_LEN);
iwe.cmd = IWEVCUSTOM;
iwe.u.data.length = p - custom;
if (iwe.u.data.length)
start = iwe_stream_add_point_rsl(info, start, stop,
&iwe, custom);
start = iwe_stream_add_point(info, start, stop, &iwe, custom);
/* Add quality statistics */
/* TODO: Fix these values... */
iwe.cmd = IWEVQUAL;
@ -172,13 +163,13 @@ static inline char *rtl819x_translate_scan(struct rtllib_device *ieee,
if (!(network->stats.mask & RTLLIB_STATMASK_SIGNAL))
iwe.u.qual.updated |= IW_QUAL_QUAL_INVALID;
iwe.u.qual.updated = 7;
start = iwe_stream_add_event_rsl(info, start, stop, &iwe, IW_EV_QUAL_LEN);
start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_QUAL_LEN);
iwe.cmd = IWEVCUSTOM;
p = custom;
iwe.u.data.length = p - custom;
if (iwe.u.data.length)
start = iwe_stream_add_point_rsl(info, start, stop, &iwe, custom);
start = iwe_stream_add_point(info, start, stop, &iwe, custom);
memset(&iwe, 0, sizeof(iwe));
if (network->wpa_ie_len) {
@ -187,7 +178,7 @@ static inline char *rtl819x_translate_scan(struct rtllib_device *ieee,
memcpy(buf, network->wpa_ie, network->wpa_ie_len);
iwe.cmd = IWEVGENIE;
iwe.u.data.length = network->wpa_ie_len;
start = iwe_stream_add_point_rsl(info, start, stop, &iwe, buf);
start = iwe_stream_add_point(info, start, stop, &iwe, buf);
}
memset(&iwe, 0, sizeof(iwe));
if (network->rsn_ie_len) {
@ -196,7 +187,7 @@ static inline char *rtl819x_translate_scan(struct rtllib_device *ieee,
memcpy(buf, network->rsn_ie, network->rsn_ie_len);
iwe.cmd = IWEVGENIE;
iwe.u.data.length = network->rsn_ie_len;
start = iwe_stream_add_point_rsl(info, start, stop, &iwe, buf);
start = iwe_stream_add_point(info, start, stop, &iwe, buf);
}
/* add info for WZC */
@ -207,7 +198,7 @@ static inline char *rtl819x_translate_scan(struct rtllib_device *ieee,
memcpy(buf, network->wzc_ie, network->wzc_ie_len);
iwe.cmd = IWEVGENIE;
iwe.u.data.length = network->wzc_ie_len;
start = iwe_stream_add_point_rsl(info, start, stop, &iwe, buf);
start = iwe_stream_add_point(info, start, stop, &iwe, buf);
}
/* Add EXTRA: Age to display seconds since last beacon/probe response
@ -220,8 +211,7 @@ static inline char *rtl819x_translate_scan(struct rtllib_device *ieee,
(100 * (jiffies - network->last_scanned)) / HZ);
iwe.u.data.length = p - custom;
if (iwe.u.data.length)
start = iwe_stream_add_point_rsl(info, start, stop,
&iwe, custom);
start = iwe_stream_add_point(info, start, stop, &iwe, custom);
return start;
}

38
drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c
View File

@ -1958,43 +1958,6 @@ int ieee80211_parse_info_param(struct ieee80211_device *ieee,
return 0;
}
static inline u8 ieee80211_SignalStrengthTranslate(
u8 CurrSS
)
{
u8 RetSS;
// Step 1. Scale mapping.
if (CurrSS >= 71 && CurrSS <= 100) {
RetSS = 90 + ((CurrSS - 70) / 3);
} else if (CurrSS >= 41 && CurrSS <= 70) {
RetSS = 78 + ((CurrSS - 40) / 3);
} else if (CurrSS >= 31 && CurrSS <= 40) {
RetSS = 66 + (CurrSS - 30);
} else if (CurrSS >= 21 && CurrSS <= 30) {
RetSS = 54 + (CurrSS - 20);
} else if (CurrSS >= 5 && CurrSS <= 20) {
RetSS = 42 + (((CurrSS - 5) * 2) / 3);
} else if (CurrSS == 4) {
RetSS = 36;
} else if (CurrSS == 3) {
RetSS = 27;
} else if (CurrSS == 2) {
RetSS = 18;
} else if (CurrSS == 1) {
RetSS = 9;
} else {
RetSS = CurrSS;
}
//RT_TRACE(COMP_DBG, DBG_LOUD, ("##### After Mapping: LastSS: %d, CurrSS: %d, RetSS: %d\n", LastSS, CurrSS, RetSS));
// Step 2. Smoothing.
//RT_TRACE(COMP_DBG, DBG_LOUD, ("$$$$$ After Smoothing: LastSS: %d, CurrSS: %d, RetSS: %d\n", LastSS, CurrSS, RetSS));
return RetSS;
}
/* 0-100 index */
static long ieee80211_translate_todbm(u8 signal_strength_index)
{
@ -2095,7 +2058,6 @@ static inline int ieee80211_network_init(
network->flags |= NETWORK_EMPTY_ESSID;
stats->signal = 30 + (stats->SignalStrength * 70) / 100;
//stats->signal = ieee80211_SignalStrengthTranslate(stats->signal);
stats->noise = ieee80211_translate_todbm((u8)(100 - stats->signal)) - 25;
memcpy(&network->stats, stats, sizeof(network->stats));

244
drivers/staging/rtl8192u/r8192U_dm.c
View File

@ -1,19 +1,14 @@
// SPDX-License-Identifier: GPL-2.0
/*++
Copyright-c Realtek Semiconductor Corp. All rights reserved.
Module Name:
r8192U_dm.c
Abstract:
HW dynamic mechanism.
Major Change History:
When Who What
---------- --------------- -------------------------------
2008-05-14 amy create version 0 porting from windows code.
--*/
* Copyright-c Realtek Semiconductor Corp. All rights reserved.
*
* Module Name:
* r8192U_dm.c
*
* Abstract:
* HW dynamic mechanism.
*--
*/
#include "r8192U.h"
#include "r8192U_dm.h"
#include "r8192U_hw.h"
@ -54,12 +49,8 @@ static void dm_init_bandwidth_autoswitch(struct net_device *dev);
static void dm_bandwidth_autoswitch(struct net_device *dev);
/* DM --> TX power control */
/*static void dm_initialize_txpower_tracking(struct net_device *dev);*/
static void dm_check_txpower_tracking(struct net_device *dev);
/*static void dm_txpower_reset_recovery(struct net_device *dev);*/
/* DM --> Dynamic Init Gain by RSSI */
static void dm_dig_init(struct net_device *dev);
static void dm_ctrl_initgain_byrssi(struct net_device *dev);
@ -74,7 +65,6 @@ static void dm_init_ctstoself(struct net_device *dev);
/* DM --> EDCA turbo mode control */
static void dm_check_edca_turbo(struct net_device *dev);
/*static void dm_gpio_change_rf(struct net_device *dev);*/
/* DM --> Check PBC */
static void dm_check_pbc_gpio(struct net_device *dev);
@ -121,7 +111,6 @@ void init_hal_dm(struct net_device *dev)
/* Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code. */
dm_init_dynamic_txpower(dev);
init_rate_adaptive(dev);
/*dm_initialize_txpower_tracking(dev);*/
dm_dig_init(dev);
dm_init_edca_turbo(dev);
dm_init_bandwidth_autoswitch(dev);
@ -146,21 +135,6 @@ void dm_CheckRxAggregation(struct net_device *dev)
unsigned long curTxOkCnt = 0;
unsigned long curRxOkCnt = 0;
/*
if (pHalData->bForcedUsbRxAggr) {
if (pHalData->ForcedUsbRxAggrInfo == 0) {
if (pHalData->bCurrentRxAggrEnable) {
Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, FALSE);
}
} else {
if (!pHalData->bCurrentRxAggrEnable || (pHalData->ForcedUsbRxAggrInfo != pHalData->LastUsbRxAggrInfoSetting)) {
Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, TRUE);
}
}
return;
}
*/
curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
@ -194,10 +168,6 @@ void dm_CheckRxAggregation(struct net_device *dev)
void hal_dm_watchdog(struct net_device *dev)
{
/*struct r8192_priv *priv = ieee80211_priv(dev);*/
/*static u8 previous_bssid[6] ={0};*/
/*Add by amy 2008/05/15 ,porting from windows code.*/
dm_check_rate_adaptive(dev);
dm_dynamic_txpower(dev);
@ -274,12 +244,8 @@ void init_rate_adaptive(struct net_device *dev)
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 05/26/08 amy Create version 0 porting from windows code.
*
*---------------------------------------------------------------------------*/
*---------------------------------------------------------------------------
*/
static void dm_check_rate_adaptive(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
@ -304,7 +270,6 @@ static void dm_check_rate_adaptive(struct net_device *dev)
return;
if (priv->ieee80211->state == IEEE80211_LINKED) {
/*RT_TRACE(COMP_RATE, "dm_CheckRateAdaptive(): \t");*/
/* Check whether Short GI is enabled */
bshort_gi_enabled = (pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI40MHz) ||
@ -351,36 +316,27 @@ static void dm_check_rate_adaptive(struct net_device *dev)
(pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
}
/*DbgPrint("[DM] THresh H/L=%d/%d\n\r", RATR.HighRSSIThreshForRA, RATR.LowRSSIThreshForRA);*/
if (priv->undecorated_smoothed_pwdb >= (long)HighRSSIThreshForRA) {
/*DbgPrint("[DM] RSSI=%d STA=HIGH\n\r", pHalData->UndecoratedSmoothedPWDB);*/
pra->ratr_state = DM_RATR_STA_HIGH;
targetRATR = pra->upper_rssi_threshold_ratr;
} else if (priv->undecorated_smoothed_pwdb >= (long)LowRSSIThreshForRA) {
/*DbgPrint("[DM] RSSI=%d STA=Middle\n\r", pHalData->UndecoratedSmoothedPWDB);*/
pra->ratr_state = DM_RATR_STA_MIDDLE;
targetRATR = pra->middle_rssi_threshold_ratr;
} else {
/*DbgPrint("[DM] RSSI=%d STA=LOW\n\r", pHalData->UndecoratedSmoothedPWDB);*/
pra->ratr_state = DM_RATR_STA_LOW;
targetRATR = pra->low_rssi_threshold_ratr;
}
/* cosa add for test */
if (pra->ping_rssi_enable) {
/*pHalData->UndecoratedSmoothedPWDB = 19;*/
if (priv->undecorated_smoothed_pwdb < (long)(pra->ping_rssi_thresh_for_ra+5)) {
if ((priv->undecorated_smoothed_pwdb < (long)pra->ping_rssi_thresh_for_ra) ||
ping_rssi_state) {
/*DbgPrint("TestRSSI = %d, set RATR to 0x%x\n", pHalData->UndecoratedSmoothedPWDB, pRA->TestRSSIRATR);*/
pra->ratr_state = DM_RATR_STA_LOW;
targetRATR = pra->ping_rssi_ratr;
ping_rssi_state = 1;
}
/*else
DbgPrint("TestRSSI is between the range.\n");*/
} else {
/*DbgPrint("TestRSSI Recover to 0x%x\n", targetRATR);*/
ping_rssi_state = 0;
}
}
@ -502,7 +458,6 @@ static void dm_TXPowerTrackingCallback_TSSI(struct net_device *dev)
u32 Value;
u8 Pwr_Flag;
u16 Avg_TSSI_Meas, TSSI_13dBm, Avg_TSSI_Meas_from_driver = 0;
/*RT_STATUS rtStatus = RT_STATUS_SUCCESS;*/
bool rtStatus = true;
u32 delta = 0;
@ -524,7 +479,6 @@ static void dm_TXPowerTrackingCallback_TSSI(struct net_device *dev)
if (rtStatus == RT_STATUS_FAILURE)
RT_TRACE(COMP_POWER_TRACKING, "Set configuration with tx cmd queue fail!\n");
usleep_range(1000, 2000);
/*DbgPrint("hi, vivi, strange\n");*/
for (i = 0; i <= 30; i++) {
read_nic_byte(dev, 0x1ba, &Pwr_Flag);
@ -570,8 +524,6 @@ static void dm_TXPowerTrackingCallback_TSSI(struct net_device *dev)
TSSI_13dBm = priv->TSSI_13dBm;
RT_TRACE(COMP_POWER_TRACKING, "TSSI_13dBm = %d\n", TSSI_13dBm);
/*if (abs(Avg_TSSI_Meas_from_driver - TSSI_13dBm) <= E_FOR_TX_POWER_TRACK)*/
/* For MacOS-compatible */
if (Avg_TSSI_Meas_from_driver > TSSI_13dBm)
delta = Avg_TSSI_Meas_from_driver - TSSI_13dBm;
else
@ -675,7 +627,6 @@ static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device *dev)
}
}
priv->btxpower_trackingInit = true;
/*pHalData->TXPowercount = 0;*/
return;
}
@ -719,9 +670,6 @@ static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device *dev)
}
tmpCCK40Mindex = 0;
}
/*DbgPrint("%ddb, tmpOFDMindex = %d, tmpCCK20Mindex = %d, tmpCCK40Mindex = %d",
((u1Byte)tmpRegA - pHalData->ThermalMeter[0]),
tmpOFDMindex, tmpCCK20Mindex, tmpCCK40Mindex);*/
if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) /* 40M */
tmpCCKindex = tmpCCK40Mindex;
else
@ -741,7 +689,6 @@ static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device *dev)
}
if (CCKSwingNeedUpdate) {
/*DbgPrint("Update CCK Swing, CCK_index = %d\n", pHalData->CCK_index);*/
dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
}
if (priv->OFDM_index != tmpOFDMindex) {
@ -1312,7 +1259,6 @@ static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
static u8 TM_Trigger;
/*DbgPrint("dm_CheckTXPowerTracking()\n");*/
if (!priv->btxpower_tracking)
return;
if (priv->txpower_count <= 2) {
@ -1332,7 +1278,6 @@ static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev)
TM_Trigger = 1;
return;
}
/*DbgPrint("Schedule TxPowerTrackingWorkItem\n");*/
queue_delayed_work(priv->priv_wq, &priv->txpower_tracking_wq, 0);
TM_Trigger = 0;
}
@ -1340,7 +1285,6 @@ static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev)
static void dm_check_txpower_tracking(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
/*static u32 tx_power_track_counter = 0;*/
#ifdef RTL8190P
dm_CheckTXPowerTracking_TSSI(dev);
@ -1425,7 +1369,6 @@ static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH
RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
rCCK0_DebugPort, TempVal);
} else {
/*priv->CCKTxPowerAdjustCntNotCh14++; cosa add for debug.*/
/* Write 0xa22 0xa23 */
TempVal = CCKSwingTable_Ch14[priv->CCK_index][0] +
(CCKSwingTable_Ch14[priv->CCK_index][1]<<8);
@ -1508,10 +1451,7 @@ void dm_restore_dynamic_mechanism_state(struct net_device *dev)
ratr_value = reg_ratr;
if (priv->rf_type == RF_1T2R) { /* 1T2R, Spatial Stream 2 should be disabled */
ratr_value &= ~(RATE_ALL_OFDM_2SS);
/*DbgPrint("HW_VAR_TATR_0 from 0x%x ==> 0x%x\n", ((pu4Byte)(val))[0], ratr_value);*/
}
/*DbgPrint("set HW_VAR_TATR_0 = 0x%x\n", ratr_value);*/
/*cosa PlatformEFIOWrite4Byte(Adapter, RATR0, ((pu4Byte)(val))[0]);*/
write_nic_dword(dev, RATR0, ratr_value);
write_nic_byte(dev, UFWP, 1);
}
@ -1533,7 +1473,6 @@ static void dm_bb_initialgain_restore(struct net_device *dev)
return;
/* Disable Initial Gain */
/*PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);*/
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); /* Only clear byte 1 and rewrite. */
rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1);
rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1);
@ -1548,7 +1487,6 @@ static void dm_bb_initialgain_restore(struct net_device *dev)
RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc68 is %x\n", priv->initgain_backup.xdagccore1);
RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x\n", priv->initgain_backup.cca);
/* Enable Initial Gain */
/*PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x100);*/
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); /* Only clear byte 1 and rewrite. */
} /* dm_BBInitialGainRestore */
@ -1561,7 +1499,6 @@ static void dm_bb_initialgain_backup(struct net_device *dev)
if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
return;
/*PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);*/
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); /* Only clear byte 1 and rewrite. */
priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask);
priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask);
@ -1589,12 +1526,8 @@ static void dm_bb_initialgain_backup(struct net_device *dev)
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 05/15/2008 amy Create Version 0 porting from windows code.
*
*---------------------------------------------------------------------------*/
*---------------------------------------------------------------------------
*/
static void dm_dig_init(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
@ -1634,11 +1567,8 @@ static void dm_dig_init(struct net_device *dev)
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 05/27/2008 amy Create Version 0 porting from windows code.
*---------------------------------------------------------------------------*/
*---------------------------------------------------------------------------
*/
static void dm_ctrl_initgain_byrssi(struct net_device *dev)
{
if (!dm_digtable.dig_enable_flag)
@ -1663,7 +1593,6 @@ static void dm_ctrl_initgain_byrssi_by_driverrssi(
if (!dm_digtable.dig_enable_flag)
return;
/*DbgPrint("Dig by Sw Rssi\n");*/
if (dm_digtable.dig_algorithm_switch) /* if switched algorithm, we have to disable FW Dig. */
fw_dig = 0;
@ -1680,11 +1609,7 @@ static void dm_ctrl_initgain_byrssi_by_driverrssi(
else
dm_digtable.cur_connect_state = DIG_DISCONNECT;
/*DbgPrint("DM_DigTable.PreConnectState = %d, DM_DigTable.CurConnectState = %d\n",
DM_DigTable.PreConnectState, DM_DigTable.CurConnectState);*/
dm_digtable.rssi_val = priv->undecorated_smoothed_pwdb;
/*DbgPrint("DM_DigTable.Rssi_val = %d\n", DM_DigTable.Rssi_val);*/
dm_initial_gain(dev);
dm_pd_th(dev);
dm_cs_ratio(dev);
@ -1720,11 +1645,6 @@ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
(priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_thresh))
return;
/*DbgPrint("Dig by Fw False Alarm\n");*/
/*if (DM_DigTable.Dig_State == DM_STA_DIG_OFF)*/
/*DbgPrint("DIG Check\n\r RSSI=%d LOW=%d HIGH=%d STATE=%d",
pHalData->UndecoratedSmoothedPWDB, DM_DigTable.RssiLowThresh,
DM_DigTable.RssiHighThresh, DM_DigTable.Dig_State);*/
/* 1. When RSSI decrease, We have to judge if it is smaller than a threshold
* and then execute the step below.
*/
@ -1757,12 +1677,6 @@ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
* 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
*/
write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40);
else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
else
PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40);
*/
} else
write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
@ -1770,7 +1684,6 @@ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
write_nic_byte(dev, 0xa0a, 0x08);
/* 1.5 Higher EDCCA. */
/*PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x325);*/
return;
}
@ -1791,7 +1704,6 @@ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
reset_cnt = priv->reset_count;
dm_digtable.dig_state = DM_STA_DIG_ON;
/*DbgPrint("DIG ON\n\r");*/
/* 2.1 Set initial gain.
* 2008/02/26 MH SD3-Jerry suggest to prevent dirty environment.
@ -1814,13 +1726,6 @@ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
* 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
*/
write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
/*
else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
else
PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42);
*/
} else
write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
@ -1830,7 +1735,6 @@ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
/* 2.4 Lower EDCCA.
* 2008/01/11 MH 90/92 series are the same.
*/
/*PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x346);*/
/* 2.5 DIG On. */
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); /* Only clear byte 1 and rewrite. */
@ -1850,12 +1754,8 @@ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 05/28/2008 amy Create Version 0 porting from windows code.
*
*---------------------------------------------------------------------------*/
*---------------------------------------------------------------------------
*/
static void dm_ctrl_initgain_byrssi_highpwr(
struct net_device *dev)
{
@ -1881,11 +1781,6 @@ static void dm_ctrl_initgain_byrssi_highpwr(
/* 3.1 Higher PD_TH for OFDM for high power state. */
if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
*/
} else
write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
} else {
@ -1899,10 +1794,6 @@ static void dm_ctrl_initgain_byrssi_highpwr(
/* 3.2 Recover PD_TH for OFDM for normal power region. */
if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
*/
} else
write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
}
@ -1944,7 +1835,6 @@ static void dm_initial_gain(
dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
dm_digtable.pre_ig_value = 0;
}
/*DbgPrint("DM_DigTable.CurIGValue = 0x%x, DM_DigTable.PreIGValue = 0x%x\n", DM_DigTable.CurIGValue, DM_DigTable.PreIGValue);*/
/* if silent reset happened, we should rewrite the values back */
if (priv->reset_count != reset_cnt) {
@ -1960,7 +1850,6 @@ static void dm_initial_gain(
if ((dm_digtable.pre_ig_value != dm_digtable.cur_ig_value)
|| !initialized || force_write) {
initial_gain = (u8)dm_digtable.cur_ig_value;
/*DbgPrint("Write initial gain = 0x%x\n", initial_gain);*/
/* Set initial gain. */
write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
@ -2012,7 +1901,6 @@ static void dm_pd_th(
{
if ((dm_digtable.prepd_thstate != dm_digtable.curpd_thstate) ||
(initialized <= 3) || force_write) {
/*DbgPrint("Write PD_TH state = %d\n", DM_DigTable.CurPD_THState);*/
if (dm_digtable.curpd_thstate == DIG_PD_AT_LOW_POWER) {
/* Lower PD_TH for OFDM. */
if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
@ -2020,9 +1908,6 @@ static void dm_pd_th(
* 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
*/
write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
*/
} else
write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
} else if (dm_digtable.curpd_thstate == DIG_PD_AT_NORMAL_POWER) {
@ -2032,18 +1917,12 @@ static void dm_pd_th(
* 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
*/
write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
*/
} else
write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
} else if (dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER) {
/* Higher PD_TH for OFDM for high power state. */
if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
*/
} else
write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
}
@ -2090,7 +1969,6 @@ static void dm_cs_ratio(
{
if ((dm_digtable.precs_ratio_state != dm_digtable.curcs_ratio_state) ||
!initialized || force_write) {
/*DbgPrint("Write CS_ratio state = %d\n", DM_DigTable.CurCS_ratioState);*/
if (dm_digtable.curcs_ratio_state == DIG_CS_RATIO_LOWER) {
/* Lower CS ratio for CCK. */
write_nic_byte(dev, 0xa0a, 0x08);
@ -2119,7 +1997,6 @@ static void dm_check_edca_turbo(
{
struct r8192_priv *priv = ieee80211_priv(dev);
PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
/*PSTA_QOS pStaQos = pMgntInfo->pStaQos;*/
/* Keep past Tx/Rx packet count for RT-to-RT EDCA turbo. */
static unsigned long lastTxOkCnt;
@ -2136,20 +2013,16 @@ static void dm_check_edca_turbo(
if (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO)
goto dm_CheckEdcaTurbo_EXIT;
/*printk("========>%s():bis_any_nonbepkts is %d\n", __func__, priv->bis_any_nonbepkts);*/
/* Check the status for current condition. */
if (!priv->ieee80211->bis_any_nonbepkts) {
curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
/* For RT-AP, we needs to turn it on when Rx>Tx */
if (curRxOkCnt > 4*curTxOkCnt) {
/*printk("%s():curRxOkCnt > 4*curTxOkCnt\n");*/
if (!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) {
write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]);
priv->bis_cur_rdlstate = true;
}
} else {
/*printk("%s():curRxOkCnt < 4*curTxOkCnt\n");*/
if (priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) {
write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]);
priv->bis_cur_rdlstate = false;
@ -2249,7 +2122,6 @@ static void dm_ctstoself(struct net_device *dev)
curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
if (curRxOkCnt > 4*curTxOkCnt) { /* downlink, disable CTS to self */
pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
/*DbgPrint("dm_CTSToSelf() ==> CTS to self disabled -- downlink\n");*/
} else { /* uplink */
pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF;
}
@ -2269,12 +2141,8 @@ static void dm_ctstoself(struct net_device *dev)
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 05/28/2008 amy Create Version 0 porting from windows code.
*
*---------------------------------------------------------------------------*/
*---------------------------------------------------------------------------
*/
static void dm_check_pbc_gpio(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
@ -2303,18 +2171,13 @@ static void dm_check_pbc_gpio(struct net_device *dev)
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 01/30/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
*---------------------------------------------------------------------------
*/
void dm_rf_pathcheck_workitemcallback(struct work_struct *work)
{
struct delayed_work *dwork = to_delayed_work(work);
struct r8192_priv *priv = container_of(dwork, struct r8192_priv, rfpath_check_wq);
struct net_device *dev = priv->ieee80211->dev;
/*bool bactually_set = false;*/
u8 rfpath = 0, i;
/* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will
@ -2378,7 +2241,6 @@ static void dm_rxpath_sel_byrssi(struct net_device *dev)
if (priv->ieee80211->mode == WIRELESS_MODE_B) {
DM_RxPathSelTable.cck_method = CCK_RX_VERSION_2; /* pure B mode, fixed cck version2 */
/*DbgPrint("Pure B mode, use cck rx version2\n");*/
}
/* decide max/sec/min rssi index */
@ -2531,7 +2393,6 @@ static void dm_rxpath_sel_byrssi(struct net_device *dev)
if ((DM_RxPathSelTable.disabled_rf >> i) & 0x1) { /* disabled rf */
if (tmp_max_rssi >= DM_RxPathSelTable.rf_enable_rssi_th[i]) {
/* enable the BB Rx path */
/*DbgPrint("RF-%d is enabled.\n", 0x1<<i);*/
rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<i, 0x1); /* 0xc04[3:0] */
rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<i, 0x1); /* 0xd04[3:0] */
DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
@ -2552,12 +2413,8 @@ static void dm_rxpath_sel_byrssi(struct net_device *dev)
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 05/28/2008 amy Create Version 0 porting from windows code.
*
*---------------------------------------------------------------------------*/
*---------------------------------------------------------------------------
*/
static void dm_check_rx_path_selection(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
@ -2756,7 +2613,6 @@ void dm_check_fsync(struct net_device *dev)
#define RegC38_NonFsync_Other_AP 1
#define RegC38_Fsync_AP_BCM 2
struct r8192_priv *priv = ieee80211_priv(dev);
/*u32 framesyncC34;*/
static u8 reg_c38_State = RegC38_Default;
static u32 reset_cnt;
@ -2831,14 +2687,12 @@ void dm_check_fsync(struct net_device *dev)
if (reg_c38_State) {
write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
reg_c38_State = RegC38_Default;
/*DbgPrint("Fsync is idle, rssi>=40, write 0xc38 = 0x%x\n", pHalData->framesync);*/
}
}
} else {
if (reg_c38_State) {
write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
reg_c38_State = RegC38_Default;
/*DbgPrint("Fsync is idle, not connected, write 0xc38 = 0x%x\n", pHalData->framesync);*/
}
}
}
@ -2848,55 +2702,15 @@ void dm_check_fsync(struct net_device *dev)
write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
reg_c38_State = RegC38_Default;
reset_cnt = priv->reset_count;
/*DbgPrint("reg_c38_State = 0 for silent reset.\n");*/
}
} else {
if (reg_c38_State) {
write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
reg_c38_State = RegC38_Default;
/*DbgPrint("framesync no monitor, write 0xc38 = 0x%x\n", pHalData->framesync);*/
}
}
}
/*-----------------------------------------------------------------------------
* Function: dm_shadow_init()
*
* Overview: Store all NIC MAC/BB register content.
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 05/29/2008 amy Create Version 0 porting from windows code.
*
*---------------------------------------------------------------------------
*/
void dm_shadow_init(struct net_device *dev)
{
u8 page;
u16 offset;
for (page = 0; page < 5; page++)
for (offset = 0; offset < 256; offset++) {
read_nic_byte(dev, offset + page * 256, &dm_shadow[page][offset]);
/*DbgPrint("P-%d/O-%02x=%02x\r\n", page, offset, DM_Shadow[page][offset]);*/
}
for (page = 8; page < 11; page++)
for (offset = 0; offset < 256; offset++)
read_nic_byte(dev, offset + page * 256, &dm_shadow[page][offset]);
for (page = 12; page < 15; page++)
for (offset = 0; offset < 256; offset++)
read_nic_byte(dev, offset + page * 256, &dm_shadow[page][offset]);
} /* dm_shadow_init */
/*---------------------------Define function prototype------------------------*/
/*-----------------------------------------------------------------------------
* Function: DM_DynamicTxPower()
@ -2909,11 +2723,6 @@ void dm_shadow_init(struct net_device *dev)
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 03/06/2008 Jacken Create Version 0.
*
*---------------------------------------------------------------------------
*/
static void dm_init_dynamic_txpower(struct net_device *dev)
@ -2939,7 +2748,6 @@ static void dm_dynamic_txpower(struct net_device *dev)
priv->bDynamicTxLowPower = false;
return;
}
/*printk("priv->ieee80211->current_network.unknown_cap_exist is %d , priv->ieee80211->current_network.broadcom_cap_exist is %d\n", priv->ieee80211->current_network.unknown_cap_exist, priv->ieee80211->current_network.broadcom_cap_exist);*/
if ((priv->ieee80211->current_network.atheros_cap_exist) && (priv->ieee80211->mode == IEEE_G)) {
txhipower_threshold = TX_POWER_ATHEROAP_THRESH_HIGH;
txlowpower_threshold = TX_POWER_ATHEROAP_THRESH_LOW;
@ -2948,7 +2756,6 @@ static void dm_dynamic_txpower(struct net_device *dev)
txlowpower_threshold = TX_POWER_NEAR_FIELD_THRESH_LOW;
}
/*printk("=======>%s(): txhipower_threshold is %d, txlowpower_threshold is %d\n", __func__, txhipower_threshold, txlowpower_threshold);*/
RT_TRACE(COMP_TXAGC, "priv->undecorated_smoothed_pwdb = %ld\n", priv->undecorated_smoothed_pwdb);
if (priv->ieee80211->state == IEEE80211_LINKED) {
@ -2967,7 +2774,6 @@ static void dm_dynamic_txpower(struct net_device *dev)
priv->bDynamicTxLowPower = false;
}
} else {
/*pHalData->bTXPowerCtrlforNearFarRange = !pHalData->bTXPowerCtrlforNearFarRange;*/
priv->bDynamicTxHighPower = false;
priv->bDynamicTxLowPower = false;
}
@ -2994,14 +2800,10 @@ static void dm_check_txrateandretrycount(struct net_device *dev)
struct r8192_priv *priv = ieee80211_priv(dev);
struct ieee80211_device *ieee = priv->ieee80211;
/* for 11n tx rate */
/*priv->stats.CurrentShowTxate = read_nic_byte(dev, CURRENT_TX_RATE_REG);*/
read_nic_byte(dev, CURRENT_TX_RATE_REG, &ieee->softmac_stats.CurrentShowTxate);
/*printk("=============>tx_rate_reg:%x\n", ieee->softmac_stats.CurrentShowTxate);*/
/* for initial tx rate */
/*priv->stats.last_packet_rate = read_nic_byte(dev, INITIAL_TX_RATE_REG);*/
read_nic_byte(dev, INITIAL_TX_RATE_REG, &ieee->softmac_stats.last_packet_rate);
/* for tx retry count */
/*priv->stats.txretrycount = read_nic_dword(dev, TX_RETRY_COUNT_REG);*/
read_nic_dword(dev, TX_RETRY_COUNT_REG, &ieee->softmac_stats.txretrycount);
}

1
drivers/staging/rtl8192u/r8192U_dm.h
View File

@ -168,7 +168,6 @@ void dm_rf_operation_test_callback(unsigned long data);
void dm_rf_pathcheck_workitemcallback(struct work_struct *work);
void dm_fsync_work_callback(struct work_struct *work);
void dm_cck_txpower_adjust(struct net_device *dev, bool binch14);
void dm_shadow_init(struct net_device *dev);
void dm_initialize_txpower_tracking(struct net_device *dev);
/*--------------------------Exported Function prototype---------------------*/

87
drivers/staging/rtl8192u/r819xU_phy.c
View File

@ -1044,93 +1044,6 @@ static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
}
}
/******************************************************************************
* function: This function sets RF state on or off
* input: net_device *dev
* RT_RF_POWER_STATE eRFPowerState //Power State to set
* output: none
* return: none
* notice:
*****************************************************************************/
bool rtl8192_SetRFPowerState(struct net_device *dev,
RT_RF_POWER_STATE eRFPowerState)
{
bool bResult = true;
struct r8192_priv *priv = ieee80211_priv(dev);
if (eRFPowerState == priv->ieee80211->eRFPowerState)
return false;
if (priv->SetRFPowerStateInProgress)
return false;
priv->SetRFPowerStateInProgress = true;
switch (priv->rf_chip) {
case RF_8256:
switch (eRFPowerState) {
case eRfOn:
/* RF-A, RF-B */
/* enable RF-Chip A/B - 0x860[4] */
rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4),
0x1);
/* analog to digital on - 0x88c[9:8] */
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300,
0x3);
/* digital to analog on - 0x880[4:3] */
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
0x3);
/* rx antenna on - 0xc04[1:0] */
rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);
/* rx antenna on - 0xd04[1:0] */
rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);
/* analog to digital part2 on - 0x880[6:5] */
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
0x3);
break;
case eRfSleep:
break;
case eRfOff:
/* RF-A, RF-B */
/* disable RF-Chip A/B - 0x860[4] */
rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4),
0x0);
/* analog to digital off, for power save */
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00,
0x0); /* 0x88c[11:8] */
/* digital to analog off, for power save - 0x880[4:3] */
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
0x0);
/* rx antenna off - 0xc04[3:0] */
rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
/* rx antenna off - 0xd04[3:0] */
rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
/* analog to digital part2 off, for power save */
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
0x0); /* 0x880[6:5] */
break;
default:
bResult = false;
RT_TRACE(COMP_ERR, "%s(): unknown state to set: 0x%X\n",
__func__, eRFPowerState);
break;
}
break;
default:
RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip);
break;
}
priv->SetRFPowerStateInProgress = false;
return bResult;
}
/******************************************************************************
* function: This function sets command table variable (struct sw_chnl_cmd).
* input: sw_chnl_cmd *CmdTable //table to be set

2
drivers/staging/rtl8192u/r819xU_phy.h
View File

@ -74,8 +74,6 @@ void rtl8192_SetBWMode(struct net_device *dev,
enum ht_extension_chan_offset offset);
void rtl8192_SwChnl_WorkItem(struct net_device *dev);
void rtl8192_SetBWModeWorkItem(struct net_device *dev);
bool rtl8192_SetRFPowerState(struct net_device *dev,
RT_RF_POWER_STATE eRFPowerState);
void InitialGain819xUsb(struct net_device *dev, u8 Operation);
void InitialGainOperateWorkItemCallBack(struct work_struct *work);

1
drivers/staging/rtl8712/rtl8712_efuse.h
View File

@ -23,6 +23,7 @@ struct PGPKT_STRUCT {
u8 word_en;
u8 data[PGPKT_DATA_SIZE];
};
/*--------------------------------------------------------------------------*/
u8 r8712_efuse_reg_init(struct _adapter *padapter);
void r8712_efuse_reg_uninit(struct _adapter *padapter);

97
drivers/staging/rtl8712/rtl871x_mlme.c
View File

@ -663,7 +663,7 @@ void r8712_joinbss_event_callback(struct _adapter *adapter, u8 *pbuf)
if (!pnetwork)
return;
memcpy((u8 *)pnetwork + 16, (u8 *)pbuf + 8,
sizeof(struct wlan_network) - 16);
sizeof(struct wlan_network) - 16);
} else {
pnetwork = (struct wlan_network *)pbuf;
}
@ -674,36 +674,36 @@ void r8712_joinbss_event_callback(struct _adapter *adapter, u8 *pbuf)
pnetwork->network_type = le32_to_cpu(pnetwork->network_type);
pnetwork->network.Length = le32_to_cpu(pnetwork->network.Length);
pnetwork->network.Ssid.SsidLength =
le32_to_cpu(pnetwork->network.Ssid.SsidLength);
le32_to_cpu(pnetwork->network.Ssid.SsidLength);
pnetwork->network.Privacy = le32_to_cpu(pnetwork->network.Privacy);
pnetwork->network.Rssi = le32_to_cpu(pnetwork->network.Rssi);
pnetwork->network.NetworkTypeInUse =
le32_to_cpu(pnetwork->network.NetworkTypeInUse);
le32_to_cpu(pnetwork->network.NetworkTypeInUse);
pnetwork->network.Configuration.ATIMWindow =
le32_to_cpu(pnetwork->network.Configuration.ATIMWindow);
le32_to_cpu(pnetwork->network.Configuration.ATIMWindow);
pnetwork->network.Configuration.BeaconPeriod =
le32_to_cpu(pnetwork->network.Configuration.BeaconPeriod);
le32_to_cpu(pnetwork->network.Configuration.BeaconPeriod);
pnetwork->network.Configuration.DSConfig =
le32_to_cpu(pnetwork->network.Configuration.DSConfig);
le32_to_cpu(pnetwork->network.Configuration.DSConfig);
pnetwork->network.Configuration.FHConfig.DwellTime =
le32_to_cpu(pnetwork->network.Configuration.FHConfig.DwellTime);
le32_to_cpu(pnetwork->network.Configuration.FHConfig.DwellTime);
pnetwork->network.Configuration.FHConfig.HopPattern =
le32_to_cpu(pnetwork->network.Configuration.FHConfig.HopPattern);
le32_to_cpu(pnetwork->network.Configuration.FHConfig.HopPattern);
pnetwork->network.Configuration.FHConfig.HopSet =
le32_to_cpu(pnetwork->network.Configuration.FHConfig.HopSet);
le32_to_cpu(pnetwork->network.Configuration.FHConfig.HopSet);
pnetwork->network.Configuration.FHConfig.Length =
le32_to_cpu(pnetwork->network.Configuration.FHConfig.Length);
le32_to_cpu(pnetwork->network.Configuration.FHConfig.Length);
pnetwork->network.Configuration.Length =
le32_to_cpu(pnetwork->network.Configuration.Length);
le32_to_cpu(pnetwork->network.Configuration.Length);
pnetwork->network.InfrastructureMode =
le32_to_cpu(pnetwork->network.InfrastructureMode);
le32_to_cpu(pnetwork->network.InfrastructureMode);
pnetwork->network.IELength = le32_to_cpu(pnetwork->network.IELength);
#endif
the_same_macaddr = !memcmp(pnetwork->network.MacAddress,
cur_network->network.MacAddress, ETH_ALEN);
cur_network->network.MacAddress, ETH_ALEN);
pnetwork->network.Length =
r8712_get_wlan_bssid_ex_sz(&pnetwork->network);
r8712_get_wlan_bssid_ex_sz(&pnetwork->network);
spin_lock_irqsave(&pmlmepriv->lock, irqL);
if (pnetwork->network.Length > sizeof(struct wlan_bssid_ex))
goto ignore_joinbss_callback;
@ -713,24 +713,24 @@ void r8712_joinbss_event_callback(struct _adapter *adapter, u8 *pbuf)
if (check_fwstate(pmlmepriv, _FW_LINKED)) {
if (the_same_macaddr) {
ptarget_wlan =
r8712_find_network(&pmlmepriv->scanned_queue,
cur_network->network.MacAddress);
r8712_find_network(&pmlmepriv->scanned_queue,
cur_network->network.MacAddress);
} else {
pcur_wlan =
r8712_find_network(&pmlmepriv->scanned_queue,
cur_network->network.MacAddress);
r8712_find_network(&pmlmepriv->scanned_queue,
cur_network->network.MacAddress);
if (pcur_wlan)
pcur_wlan->fixed = false;
pcur_sta = r8712_get_stainfo(pstapriv,
cur_network->network.MacAddress);
cur_network->network.MacAddress);
spin_lock_irqsave(&pstapriv->sta_hash_lock, irqL2);
r8712_free_stainfo(adapter, pcur_sta);
spin_unlock_irqrestore(&(pstapriv->sta_hash_lock), irqL2);
ptarget_wlan =
r8712_find_network(&pmlmepriv->scanned_queue,
pnetwork->network.MacAddress);
r8712_find_network(&pmlmepriv->scanned_queue,
pnetwork->network.MacAddress);
if (ptarget_wlan)
ptarget_wlan->fixed = true;
}
@ -745,7 +745,7 @@ void r8712_joinbss_event_callback(struct _adapter *adapter, u8 *pbuf)
if (check_fwstate(pmlmepriv,
_FW_UNDER_LINKING))
pmlmepriv->fw_state ^=
_FW_UNDER_LINKING;
_FW_UNDER_LINKING;
goto ignore_joinbss_callback;
}
@ -753,16 +753,16 @@ void r8712_joinbss_event_callback(struct _adapter *adapter, u8 *pbuf)
if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
if (the_same_macaddr) {
ptarget_sta =
r8712_get_stainfo(pstapriv,
pnetwork->network.MacAddress);
r8712_get_stainfo(pstapriv,
pnetwork->network.MacAddress);
if (!ptarget_sta)
ptarget_sta =
r8712_alloc_stainfo(pstapriv,
pnetwork->network.MacAddress);
r8712_alloc_stainfo(pstapriv,
pnetwork->network.MacAddress);
} else {
ptarget_sta =
r8712_alloc_stainfo(pstapriv,
pnetwork->network.MacAddress);
r8712_alloc_stainfo(pstapriv,
pnetwork->network.MacAddress);
}
if (ptarget_sta) /*update ptarget_sta*/ {
ptarget_sta->aid = pnetwork->join_res;
@ -773,27 +773,28 @@ void r8712_joinbss_event_callback(struct _adapter *adapter, u8 *pbuf)
adapter->securitypriv.busetkipkey = false;
adapter->securitypriv.bgrpkey_handshake = false;
ptarget_sta->ieee8021x_blocked = true;
ptarget_sta->XPrivacy = adapter->
securitypriv.PrivacyAlgrthm;
ptarget_sta->XPrivacy =
adapter->securitypriv.PrivacyAlgrthm;
memset((u8 *)&ptarget_sta->x_UncstKey,
0,
sizeof(union Keytype));
0,
sizeof(union Keytype));
memset((u8 *)&ptarget_sta->tkiprxmickey,
0,
sizeof(union Keytype));
0,
sizeof(union Keytype));
memset((u8 *)&ptarget_sta->tkiptxmickey,
0,
sizeof(union Keytype));
memset((u8 *)&ptarget_sta->txpn, 0,
sizeof(union pn48));
memset((u8 *)&ptarget_sta->rxpn, 0,
sizeof(union pn48));
0,
sizeof(union Keytype));
memset((u8 *)&ptarget_sta->txpn,
0,
sizeof(union pn48));
memset((u8 *)&ptarget_sta->rxpn,
0,
sizeof(union pn48));
}
} else {
if (check_fwstate(pmlmepriv,
_FW_UNDER_LINKING))
if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING))
pmlmepriv->fw_state ^=
_FW_UNDER_LINKING;
_FW_UNDER_LINKING;
goto ignore_joinbss_callback;
}
}
@ -815,12 +816,12 @@ void r8712_joinbss_event_callback(struct _adapter *adapter, u8 *pbuf)
break;
}
r8712_update_protection(adapter,
(cur_network->network.IEs) +
sizeof(struct NDIS_802_11_FIXED_IEs),
(cur_network->network.IELength));
(cur_network->network.IEs) +
sizeof(struct NDIS_802_11_FIXED_IEs),
(cur_network->network.IELength));
/*TODO: update HT_Capability*/
update_ht_cap(adapter, cur_network->network.IEs,
cur_network->network.IELength);
cur_network->network.IELength);
/*indicate connect*/
if (check_fwstate(pmlmepriv, WIFI_STATION_STATE))
r8712_indicate_connect(adapter);
@ -831,7 +832,7 @@ void r8712_joinbss_event_callback(struct _adapter *adapter, u8 *pbuf)
} else {
if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) {
mod_timer(&pmlmepriv->assoc_timer,
jiffies + msecs_to_jiffies(1));
jiffies + msecs_to_jiffies(1));
_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
}
}

17
drivers/staging/rtl8723bs/core/rtw_mlme.c
View File

@ -32,8 +32,6 @@ int rtw_init_mlme_priv(struct adapter *padapter)
INIT_LIST_HEAD(&pmlmepriv->scanned_queue.queue);
spin_lock_init(&pmlmepriv->scanned_queue.lock);
set_scanned_network_val(pmlmepriv, 0);
memset(&pmlmepriv->assoc_ssid, 0, sizeof(struct ndis_802_11_ssid));
pbuf = vzalloc(array_size(MAX_BSS_CNT, sizeof(struct wlan_network)));
@ -161,8 +159,6 @@ struct wlan_network *rtw_alloc_network(struct mlme_priv *pmlmepriv)
pnetwork->aid = 0;
pnetwork->join_res = 0;
pmlmepriv->num_of_scanned++;
exit:
spin_unlock_bh(&free_queue->lock);
@ -198,8 +194,6 @@ void _rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwor
list_add_tail(&(pnetwork->list), &(free_queue->queue));
pmlmepriv->num_of_scanned--;
spin_unlock_bh(&free_queue->lock);
}
@ -220,8 +214,6 @@ void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *
list_add_tail(&(pnetwork->list), get_list_head(free_queue));
pmlmepriv->num_of_scanned--;
/* spin_unlock_irqrestore(&free_queue->lock, irqL); */
}
@ -863,7 +855,6 @@ static void free_scanqueue(struct mlme_priv *pmlmepriv)
list_del_init(plist);
list_add_tail(plist, &free_queue->queue);
plist = ptemp;
pmlmepriv->num_of_scanned--;
}
spin_unlock_bh(&free_queue->lock);
@ -1549,7 +1540,7 @@ void _rtw_join_timeout_handler(struct timer_list *t)
if (adapter->bDriverStopped || adapter->bSurpriseRemoved)
return;
spin_lock_irq(&pmlmepriv->lock);
spin_lock_bh(&pmlmepriv->lock);
if (rtw_to_roam(adapter) > 0) { /* join timeout caused by roaming */
while (1) {
@ -1577,7 +1568,7 @@ void _rtw_join_timeout_handler(struct timer_list *t)
}
spin_unlock_irq(&pmlmepriv->lock);
spin_unlock_bh(&pmlmepriv->lock);
}
/*
@ -1590,11 +1581,11 @@ void rtw_scan_timeout_handler(struct timer_list *t)
mlmepriv.scan_to_timer);
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
spin_lock_irq(&pmlmepriv->lock);
spin_lock_bh(&pmlmepriv->lock);
_clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY);
spin_unlock_irq(&pmlmepriv->lock);
spin_unlock_bh(&pmlmepriv->lock);
rtw_indicate_scan_done(adapter, true);
}

8
drivers/staging/rtl8723bs/hal/hal_btcoex.c
View File

@ -1177,14 +1177,6 @@ bool hal_btcoex_IsBtDisabled(struct adapter *padapter)
return false;
}
void hal_btcoex_SetChipType(struct adapter *padapter, u8 chipType)
{
struct hal_com_data *pHalData;
pHalData = GET_HAL_DATA(padapter);
}
void hal_btcoex_SetPgAntNum(struct adapter *padapter, u8 antNum)
{
struct hal_com_data *pHalData;

108
drivers/staging/rtl8723bs/hal/hal_com.c
View File

@ -859,22 +859,6 @@ bool eqNByte(u8 *str1, u8 *str2, u32 num)
return true;
}
/* */
/* Description: */
/* Translate a character to hex digit. */
/* */
u32 MapCharToHexDigit(char chTmp)
{
if (chTmp >= '0' && chTmp <= '9')
return chTmp - '0';
else if (chTmp >= 'a' && chTmp <= 'f')
return 10 + (chTmp - 'a');
else if (chTmp >= 'A' && chTmp <= 'F')
return 10 + (chTmp - 'A');
else
return 0;
}
bool GetU1ByteIntegerFromStringInDecimal(char *Str, u8 *pInt)
{
u16 i = 0;
@ -893,45 +877,6 @@ bool GetU1ByteIntegerFromStringInDecimal(char *Str, u8 *pInt)
return true;
}
/* <20121004, Kordan> For example,
* ParseQualifiedString(inString, 0, outString, '[', ']') gets "Kordan" from
* a string "Hello [Kordan]".
* If RightQualifier does not exist, it will hang in the while loop
*/
bool ParseQualifiedString(
char *In, u32 *Start, char *Out, char LeftQualifier, char RightQualifier
)
{
u32 i = 0, j = 0;
char c = In[(*Start)++];
if (c != LeftQualifier)
return false;
i = (*Start);
while ((c = In[(*Start)++]) != RightQualifier)
; /* find ']' */
j = (*Start) - 2;
strncpy((char *)Out, (const char *)(In+i), j-i+1);
return true;
}
bool isAllSpaceOrTab(u8 *data, u8 size)
{
u8 cnt = 0, NumOfSpaceAndTab = 0;
while (size > cnt) {
if (data[cnt] == ' ' || data[cnt] == '\t' || data[cnt] == '\0')
++NumOfSpaceAndTab;
++cnt;
}
return size == NumOfSpaceAndTab;
}
void rtw_hal_check_rxfifo_full(struct adapter *adapter)
{
struct dvobj_priv *psdpriv = adapter->dvobj;
@ -952,60 +897,7 @@ void rtw_hal_check_rxfifo_full(struct adapter *adapter)
}
}
void linked_info_dump(struct adapter *padapter, u8 benable)
{
struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
if (padapter->bLinkInfoDump == benable)
return;
if (benable) {
pwrctrlpriv->org_power_mgnt = pwrctrlpriv->power_mgnt;/* keep org value */
rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
pwrctrlpriv->ips_org_mode = pwrctrlpriv->ips_mode;/* keep org value */
rtw_pm_set_ips(padapter, IPS_NONE);
} else {
rtw_pm_set_ips(padapter, pwrctrlpriv->ips_org_mode);
rtw_pm_set_lps(padapter, pwrctrlpriv->ips_org_mode);
}
padapter->bLinkInfoDump = benable;
}
#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
void rtw_get_raw_rssi_info(void *sel, struct adapter *padapter)
{
u8 isCCKrate, rf_path;
struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
netdev_dbg(padapter->pnetdev,
"RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n",
HDATA_RATE(psample_pkt_rssi->data_rate),
psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all);
isCCKrate = psample_pkt_rssi->data_rate <= DESC_RATE11M;
if (isCCKrate)
psample_pkt_rssi->mimo_signal_strength[0] = psample_pkt_rssi->pwdball;
for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
netdev_dbg(padapter->pnetdev,
"RF_PATH_%d =>signal_strength:%d(%%), signal_quality:%d(%%)\n",
rf_path,
psample_pkt_rssi->mimo_signal_strength[rf_path],
psample_pkt_rssi->mimo_signal_quality[rf_path]);
if (!isCCKrate) {
netdev_dbg(padapter->pnetdev,
"\trx_ofdm_pwr:%d(dBm), rx_ofdm_snr:%d(dB)\n",
psample_pkt_rssi->ofdm_pwr[rf_path],
psample_pkt_rssi->ofdm_snr[rf_path]);
}
}
}
void rtw_dump_raw_rssi_info(struct adapter *padapter)
{
u8 isCCKrate, rf_path;

1
drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c
View File

@ -2304,7 +2304,6 @@ void Hal_EfuseParseBTCoexistInfo_8723B(
}
hal_btcoex_SetBTCoexist(padapter, pHalData->EEPROMBluetoothCoexist);
hal_btcoex_SetChipType(padapter, pHalData->EEPROMBluetoothType);
hal_btcoex_SetPgAntNum(padapter, pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1);
if (pHalData->EEPROMBluetoothAntNum == Ant_x1)
hal_btcoex_SetSingleAntPath(padapter, pHalData->ant_path);

6
drivers/staging/rtl8723bs/include/drv_types.h
View File

@ -305,7 +305,11 @@ struct sdio_data intf_data;
};
#define dvobj_to_pwrctl(dvobj) (&(dvobj->pwrctl_priv))
#define pwrctl_to_dvobj(pwrctl) container_of(pwrctl, struct dvobj_priv, pwrctl_priv)
static inline struct dvobj_priv *pwrctl_to_dvobj(struct pwrctrl_priv *pwrctl_priv)
{
return container_of(pwrctl_priv, struct dvobj_priv, pwrctl_priv);
}
static inline struct device *dvobj_to_dev(struct dvobj_priv *dvobj)
{

1
drivers/staging/rtl8723bs/include/hal_btcoex.h
View File

@ -23,7 +23,6 @@ struct bt_coexist {
void hal_btcoex_SetBTCoexist(struct adapter *padapter, u8 bBtExist);
bool hal_btcoex_IsBtExist(struct adapter *padapter);
bool hal_btcoex_IsBtDisabled(struct adapter *);
void hal_btcoex_SetChipType(struct adapter *padapter, u8 chipType);
void hal_btcoex_SetPgAntNum(struct adapter *padapter, u8 antNum);
void hal_btcoex_SetSingleAntPath(struct adapter *padapter, u8 singleAntPath);

9
drivers/staging/rtl8723bs/include/hal_com.h
View File

@ -147,18 +147,9 @@ u8 GetHalDefVar(struct adapter *adapter, enum hal_def_variable variable,
bool eqNByte(u8 *str1, u8 *str2, u32 num);
u32 MapCharToHexDigit(char chTmp);
bool ParseQualifiedString(char *In, u32 *Start, char *Out, char LeftQualifier,
char RightQualifier);
bool GetU1ByteIntegerFromStringInDecimal(char *str, u8 *in);
bool isAllSpaceOrTab(u8 *data, u8 size);
void linked_info_dump(struct adapter *padapter, u8 benable);
#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
void rtw_get_raw_rssi_info(void *sel, struct adapter *padapter);
void rtw_store_phy_info(struct adapter *padapter, union recv_frame *prframe);
void rtw_dump_raw_rssi_info(struct adapter *padapter);
#endif

47
drivers/staging/rtl8723bs/include/ieee80211.h
View File

@ -174,7 +174,7 @@ struct ieee_param {
u8 reserved[32];
u8 data[];
} wpa_ie;
struct{
struct{
int command;
int reason_code;
} mlme;
@ -271,10 +271,10 @@ struct eapol {
#define P80211_OUI_LEN 3
struct ieee80211_snap_hdr {
u8 dsap; /* always 0xAA */
u8 ssap; /* always 0xAA */
u8 ctrl; /* always 0x03 */
u8 oui[P80211_OUI_LEN]; /* organizational universal id */
u8 dsap; /* always 0xAA */
u8 ssap; /* always 0xAA */
u8 ctrl; /* always 0x03 */
u8 oui[P80211_OUI_LEN]; /* organizational universal id */
} __attribute__ ((packed));
#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr)
@ -342,12 +342,13 @@ struct ieee80211_snap_hdr {
#define IEEE80211_OFDM_RATE_48MB_MASK (1<<10)
#define IEEE80211_OFDM_RATE_54MB_MASK (1<<11)
#define IEEE80211_CCK_RATES_MASK 0x0000000F
#define IEEE80211_CCK_RATES_MASK 0x0000000F
#define IEEE80211_CCK_BASIC_RATES_MASK (IEEE80211_CCK_RATE_1MB_MASK | \
IEEE80211_CCK_RATE_2MB_MASK)
#define IEEE80211_CCK_DEFAULT_RATES_MASK (IEEE80211_CCK_BASIC_RATES_MASK | \
IEEE80211_CCK_RATE_5MB_MASK | \
IEEE80211_CCK_RATE_11MB_MASK)
#define IEEE80211_CCK_DEFAULT_RATES_MASK \
(IEEE80211_CCK_BASIC_RATES_MASK | \
IEEE80211_CCK_RATE_5MB_MASK | \
IEEE80211_CCK_RATE_11MB_MASK)
#define IEEE80211_OFDM_RATES_MASK 0x00000FF0
#define IEEE80211_OFDM_BASIC_RATES_MASK (IEEE80211_OFDM_RATE_6MB_MASK | \
@ -359,8 +360,9 @@ struct ieee80211_snap_hdr {
IEEE80211_OFDM_RATE_36MB_MASK | \
IEEE80211_OFDM_RATE_48MB_MASK | \
IEEE80211_OFDM_RATE_54MB_MASK)
#define IEEE80211_DEFAULT_RATES_MASK (IEEE80211_OFDM_DEFAULT_RATES_MASK | \
IEEE80211_CCK_DEFAULT_RATES_MASK)
#define IEEE80211_DEFAULT_RATES_MASK \
(IEEE80211_OFDM_DEFAULT_RATES_MASK | \
IEEE80211_CCK_DEFAULT_RATES_MASK)
#define IEEE80211_NUM_OFDM_RATES 8
#define IEEE80211_NUM_CCK_RATES 4
@ -509,7 +511,7 @@ join_res:
static inline int is_multicast_mac_addr(const u8 *addr)
{
return ((addr[0] != 0xff) && (0x01 & addr[0]));
return ((addr[0] != 0xff) && (0x01 & addr[0]));
}
static inline int is_broadcast_mac_addr(const u8 *addr)
@ -612,17 +614,18 @@ enum {
* @RTW_IEEE80211_CHAN_NO_HT40MINUS: extension channel below this channel
* is not permitted.
*/
enum rtw_ieee80211_channel_flags {
RTW_IEEE80211_CHAN_DISABLED = 1<<0,
RTW_IEEE80211_CHAN_PASSIVE_SCAN = 1<<1,
RTW_IEEE80211_CHAN_NO_IBSS = 1<<2,
RTW_IEEE80211_CHAN_RADAR = 1<<3,
RTW_IEEE80211_CHAN_NO_HT40PLUS = 1<<4,
RTW_IEEE80211_CHAN_NO_HT40MINUS = 1<<5,
};
enum rtw_ieee80211_channel_flags {
RTW_IEEE80211_CHAN_DISABLED = 1<<0,
RTW_IEEE80211_CHAN_PASSIVE_SCAN = 1<<1,
RTW_IEEE80211_CHAN_NO_IBSS = 1<<2,
RTW_IEEE80211_CHAN_RADAR = 1<<3,
RTW_IEEE80211_CHAN_NO_HT40PLUS = 1<<4,
RTW_IEEE80211_CHAN_NO_HT40MINUS = 1<<5,
};
#define RTW_IEEE80211_CHAN_NO_HT40 \
(RTW_IEEE80211_CHAN_NO_HT40PLUS | RTW_IEEE80211_CHAN_NO_HT40MINUS)
#define RTW_IEEE80211_CHAN_NO_HT40 \
(RTW_IEEE80211_CHAN_NO_HT40PLUS | \
RTW_IEEE80211_CHAN_NO_HT40MINUS)
/* Represent channel details, subset of ieee80211_channel */
struct rtw_ieee80211_channel {

20
drivers/staging/rtl8723bs/include/rtw_mlme.h
View File

@ -303,7 +303,6 @@ struct mlme_priv {
struct __queue free_bss_pool;
struct __queue scanned_queue;
u8 *free_bss_buf;
u32 num_of_scanned;
struct ndis_802_11_ssid assoc_ssid;
u8 assoc_bssid[6];
@ -490,25 +489,6 @@ static inline void _clr_fwstate_(struct mlme_priv *pmlmepriv, signed int state)
pmlmepriv->bScanInProcess = false;
}
/*
* No Limit on the calling context,
* therefore set it to be the critical section...
*/
static inline void clr_fwstate(struct mlme_priv *pmlmepriv, signed int state)
{
spin_lock_bh(&pmlmepriv->lock);
if (check_fwstate(pmlmepriv, state) == true)
pmlmepriv->fw_state ^= state;
spin_unlock_bh(&pmlmepriv->lock);
}
static inline void set_scanned_network_val(struct mlme_priv *pmlmepriv, signed int val)
{
spin_lock_bh(&pmlmepriv->lock);
pmlmepriv->num_of_scanned = val;
spin_unlock_bh(&pmlmepriv->lock);
}
extern u16 rtw_get_capability(struct wlan_bssid_ex *bss);
extern void rtw_update_scanned_network(struct adapter *adapter, struct wlan_bssid_ex *target);
extern void rtw_disconnect_hdl_under_linked(struct adapter *adapter, struct sta_info *psta, u8 free_assoc);

9
drivers/staging/rtl8723bs/include/rtw_recv.h
View File

@ -398,8 +398,7 @@ static inline u8 *recvframe_pull(union recv_frame *precvframe, signed int sz)
precvframe->u.hdr.rx_data += sz;
if (precvframe->u.hdr.rx_data > precvframe->u.hdr.rx_tail)
{
if (precvframe->u.hdr.rx_data > precvframe->u.hdr.rx_tail) {
precvframe->u.hdr.rx_data -= sz;
return NULL;
}
@ -425,8 +424,7 @@ static inline u8 *recvframe_put(union recv_frame *precvframe, signed int sz)
precvframe->u.hdr.rx_tail += sz;
if (precvframe->u.hdr.rx_tail > precvframe->u.hdr.rx_end)
{
if (precvframe->u.hdr.rx_tail > precvframe->u.hdr.rx_end) {
precvframe->u.hdr.rx_tail = prev_rx_tail;
return NULL;
}
@ -451,8 +449,7 @@ static inline u8 *recvframe_pull_tail(union recv_frame *precvframe, signed int s
precvframe->u.hdr.rx_tail -= sz;
if (precvframe->u.hdr.rx_tail < precvframe->u.hdr.rx_data)
{
if (precvframe->u.hdr.rx_tail < precvframe->u.hdr.rx_data) {
precvframe->u.hdr.rx_tail += sz;
return NULL;
}

7
drivers/staging/rts5208/xd.c
View File

@ -31,13 +31,6 @@ static inline void xd_set_err_code(struct rtsx_chip *chip, u8 err_code)
xd_card->err_code = err_code;
}
static inline int xd_check_err_code(struct rtsx_chip *chip, u8 err_code)
{
struct xd_info *xd_card = &chip->xd_card;
return (xd_card->err_code == err_code);
}
static int xd_set_init_para(struct rtsx_chip *chip)
{
struct xd_info *xd_card = &chip->xd_card;

6
drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
View File

@ -1976,7 +1976,7 @@ cleanup_mmal:
return ret;
}
static int bcm2835_mmal_remove(struct platform_device *pdev)
static void bcm2835_mmal_remove(struct platform_device *pdev)
{
int camera;
struct vchiq_mmal_instance *instance = gdev[0]->instance;
@ -1986,13 +1986,11 @@ static int bcm2835_mmal_remove(struct platform_device *pdev)
gdev[camera] = NULL;
}
vchiq_mmal_finalise(instance);
return 0;
}
static struct platform_driver bcm2835_camera_driver = {
.probe = bcm2835_mmal_probe,
.remove = bcm2835_mmal_remove,
.remove_new = bcm2835_mmal_remove,
.driver = {
.name = "bcm2835-camera",
},

6
drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
View File

@ -1849,14 +1849,12 @@ error_exit:
return err;
}
static int vchiq_remove(struct platform_device *pdev)
static void vchiq_remove(struct platform_device *pdev)
{
platform_device_unregister(bcm2835_audio);
platform_device_unregister(bcm2835_camera);
vchiq_debugfs_deinit();
vchiq_deregister_chrdev();
return 0;
}
static struct platform_driver vchiq_driver = {
@ -1865,7 +1863,7 @@ static struct platform_driver vchiq_driver = {
.of_match_table = vchiq_of_match,
},
.probe = vchiq_probe,
.remove = vchiq_remove,
.remove_new = vchiq_remove,
};
static int __init vchiq_driver_init(void)

3
drivers/staging/vme_user/Kconfig
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
menuconfig VME_BUS
bool "VME bridge support"
depends on STAGING && PCI
depends on PCI
help
If you say Y here you get support for the VME bridge Framework.
@ -28,7 +28,6 @@ comment "VME Device Drivers"
config VME_USER
tristate "VME user space access driver"
depends on STAGING && VME_BUS
help
If you say Y here you want to be able to access a limited number of
VME windows in a manner at least semi-compatible with the interface

5
drivers/staging/vme_user/vme_fake.c
View File

@ -329,7 +329,6 @@ err_aspace:
err_dwidth:
err_window:
return retval;
}
/*
@ -638,7 +637,6 @@ static noinline_for_stack void fake_vmewrite8(struct fake_driver *bridge,
}
fake_lm_check(bridge, addr, aspace, cycle);
}
static noinline_for_stack void fake_vmewrite16(struct fake_driver *bridge,
@ -669,7 +667,6 @@ static noinline_for_stack void fake_vmewrite16(struct fake_driver *bridge,
}
fake_lm_check(bridge, addr, aspace, cycle);
}
static noinline_for_stack void fake_vmewrite32(struct fake_driver *bridge,
@ -700,7 +697,6 @@ static noinline_for_stack void fake_vmewrite32(struct fake_driver *bridge,
}
fake_lm_check(bridge, addr, aspace, cycle);
}
static ssize_t fake_master_write(struct vme_master_resource *image, void *buf,
@ -1234,7 +1230,6 @@ err_driver:
kfree(fake_bridge);
err_struct:
return retval;
}
static void __exit fake_exit(void)

13
drivers/staging/vme_user/vme_tsi148.c
View File

@ -737,7 +737,7 @@ static int tsi148_alloc_resource(struct vme_master_resource *image,
return 0;
if (!image->bus_resource.name) {
image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC);
image->bus_resource.name = kmalloc(VMENAMSIZ + 3, GFP_ATOMIC);
if (!image->bus_resource.name) {
retval = -ENOMEM;
goto err_name;
@ -983,7 +983,7 @@ static int tsi148_master_set(struct vme_master_resource *image, int enabled,
goto err_aspace;
}
temp_ctl &= ~(3<<4);
temp_ctl &= ~(3 << 4);
if (cycle & VME_SUPER)
temp_ctl |= TSI148_LCSR_OTAT_SUP;
if (cycle & VME_PROG)
@ -1023,7 +1023,6 @@ err_gran:
err_res:
err_window:
return retval;
}
/*
@ -1741,7 +1740,6 @@ static int tsi148_dma_list_add(struct vme_dma_list *list,
list);
prev->descriptor.dnlau = cpu_to_be32(address_high);
prev->descriptor.dnlal = cpu_to_be32(address_low);
}
return 0;
@ -1773,7 +1771,6 @@ static int tsi148_dma_busy(struct vme_bridge *tsi148_bridge, int channel)
return 0;
else
return 1;
}
/*
@ -2187,14 +2184,14 @@ static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge,
/* Ensure that the CR/CSR is configured at the correct offset */
cbar = ioread32be(bridge->base + TSI148_CBAR);
cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3;
cbar = (cbar & TSI148_CRCSR_CBAR_M) >> 3;
vstat = tsi148_slot_get(tsi148_bridge);
if (cbar != vstat) {
cbar = vstat;
dev_info(tsi148_bridge->parent, "Setting CR/CSR offset\n");
iowrite32be(cbar<<3, bridge->base + TSI148_CBAR);
iowrite32be(cbar << 3, bridge->base + TSI148_CBAR);
}
dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar);
@ -2220,7 +2217,6 @@ static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge,
}
return 0;
}
static void tsi148_crcsr_exit(struct vme_bridge *tsi148_bridge,
@ -2530,7 +2526,6 @@ err_driver:
kfree(tsi148_bridge);
err_struct:
return retval;
}
static void tsi148_remove(struct pci_dev *pdev)

528
drivers/staging/vme_user/vme_tsi148.h
View File

@ -536,22 +536,22 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
/*
* PFCS Register Set
*/
#define TSI148_PCFS_CMMD_SERR (1<<8) /* SERR_L out pin ssys err */
#define TSI148_PCFS_CMMD_PERR (1<<6) /* PERR_L out pin parity */
#define TSI148_PCFS_CMMD_MSTR (1<<2) /* PCI bus master */
#define TSI148_PCFS_CMMD_MEMSP (1<<1) /* PCI mem space access */
#define TSI148_PCFS_CMMD_IOSP (1<<0) /* PCI I/O space enable */
#define TSI148_PCFS_CMMD_SERR BIT(8) /* SERR_L out pin ssys err */
#define TSI148_PCFS_CMMD_PERR BIT(6) /* PERR_L out pin parity */
#define TSI148_PCFS_CMMD_MSTR BIT(2) /* PCI bus master */
#define TSI148_PCFS_CMMD_MEMSP BIT(1) /* PCI mem space access */
#define TSI148_PCFS_CMMD_IOSP BIT(0) /* PCI I/O space enable */
#define TSI148_PCFS_STAT_RCPVE (1<<15) /* Detected Parity Error */
#define TSI148_PCFS_STAT_SIGSE (1<<14) /* Signalled System Error */
#define TSI148_PCFS_STAT_RCVMA (1<<13) /* Received Master Abort */
#define TSI148_PCFS_STAT_RCVTA (1<<12) /* Received Target Abort */
#define TSI148_PCFS_STAT_SIGTA (1<<11) /* Signalled Target Abort */
#define TSI148_PCFS_STAT_RCPVE BIT(15) /* Detected Parity Error */
#define TSI148_PCFS_STAT_SIGSE BIT(14) /* Signalled System Error */
#define TSI148_PCFS_STAT_RCVMA BIT(13) /* Received Master Abort */
#define TSI148_PCFS_STAT_RCVTA BIT(12) /* Received Target Abort */
#define TSI148_PCFS_STAT_SIGTA BIT(11) /* Signalled Target Abort */
#define TSI148_PCFS_STAT_SELTIM (3<<9) /* DELSEL Timing */
#define TSI148_PCFS_STAT_DPAR (1<<8) /* Data Parity Err Reported */
#define TSI148_PCFS_STAT_FAST (1<<7) /* Fast back-to-back Cap */
#define TSI148_PCFS_STAT_P66M (1<<5) /* 66 MHz Capable */
#define TSI148_PCFS_STAT_CAPL (1<<4) /* Capab List - address $34 */
#define TSI148_PCFS_STAT_DPAR BIT(8) /* Data Parity Err Reported */
#define TSI148_PCFS_STAT_FAST BIT(7) /* Fast back-to-back Cap */
#define TSI148_PCFS_STAT_P66M BIT(5) /* 66 MHz Capable */
#define TSI148_PCFS_STAT_CAPL BIT(4) /* Capab List - address $34 */
/*
* Revision ID/Class Code Registers (CRG +$008)
@ -572,17 +572,17 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
* Memory Base Address Lower Reg (CRG + $010)
*/
#define TSI148_PCFS_MBARL_BASEL_M (0xFFFFF<<12) /* Base Addr Lower Mask */
#define TSI148_PCFS_MBARL_PRE (1<<3) /* Prefetch */
#define TSI148_PCFS_MBARL_PRE BIT(3) /* Prefetch */
#define TSI148_PCFS_MBARL_MTYPE_M (3<<1) /* Memory Type Mask */
#define TSI148_PCFS_MBARL_IOMEM (1<<0) /* I/O Space Indicator */
#define TSI148_PCFS_MBARL_IOMEM BIT(0) /* I/O Space Indicator */
/*
* Message Signaled Interrupt Capabilities Register (CRG + $040)
*/
#define TSI148_PCFS_MSICAP_64BAC (1<<7) /* 64-bit Address Capable */
#define TSI148_PCFS_MSICAP_64BAC BIT(7) /* 64-bit Address Capable */
#define TSI148_PCFS_MSICAP_MME_M (7<<4) /* Multiple Msg Enable Mask */
#define TSI148_PCFS_MSICAP_MMC_M (7<<1) /* Multiple Msg Capable Mask */
#define TSI148_PCFS_MSICAP_MSIEN (1<<0) /* Msg signaled INT Enable */
#define TSI148_PCFS_MSICAP_MSIEN BIT(0) /* Msg signaled INT Enable */
/*
* Message Address Lower Register (CRG +$044)
@ -599,22 +599,22 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
*/
#define TSI148_PCFS_PCIXCAP_MOST_M (7<<4) /* Max outstanding Split Tran */
#define TSI148_PCFS_PCIXCAP_MMRBC_M (3<<2) /* Max Mem Read byte cnt */
#define TSI148_PCFS_PCIXCAP_ERO (1<<1) /* Enable Relaxed Ordering */
#define TSI148_PCFS_PCIXCAP_DPERE (1<<0) /* Data Parity Recover Enable */
#define TSI148_PCFS_PCIXCAP_ERO BIT(1) /* Enable Relaxed Ordering */
#define TSI148_PCFS_PCIXCAP_DPERE BIT(0) /* Data Parity Recover Enable */
/*
* PCI-X Status Register (CRG +$054)
*/
#define TSI148_PCFS_PCIXSTAT_RSCEM (1<<29) /* Received Split Comp Error */
#define TSI148_PCFS_PCIXSTAT_RSCEM BIT(29) /* Received Split Comp Error */
#define TSI148_PCFS_PCIXSTAT_DMCRS_M (7<<26) /* max Cumulative Read Size */
#define TSI148_PCFS_PCIXSTAT_DMOST_M (7<<23) /* max outstanding Split Trans
*/
#define TSI148_PCFS_PCIXSTAT_DMMRC_M (3<<21) /* max mem read byte count */
#define TSI148_PCFS_PCIXSTAT_DC (1<<20) /* Device Complexity */
#define TSI148_PCFS_PCIXSTAT_USC (1<<19) /* Unexpected Split comp */
#define TSI148_PCFS_PCIXSTAT_SCD (1<<18) /* Split completion discard */
#define TSI148_PCFS_PCIXSTAT_133C (1<<17) /* 133MHz capable */
#define TSI148_PCFS_PCIXSTAT_64D (1<<16) /* 64 bit device */
#define TSI148_PCFS_PCIXSTAT_DC BIT(20) /* Device Complexity */
#define TSI148_PCFS_PCIXSTAT_USC BIT(19) /* Unexpected Split comp */
#define TSI148_PCFS_PCIXSTAT_SCD BIT(18) /* Split completion discard */
#define TSI148_PCFS_PCIXSTAT_133C BIT(17) /* 133MHz capable */
#define TSI148_PCFS_PCIXSTAT_64D BIT(16) /* 64 bit device */
#define TSI148_PCFS_PCIXSTAT_BN_M (0xFF<<8) /* Bus number */
#define TSI148_PCFS_PCIXSTAT_DN_M (0x1F<<3) /* Device number */
#define TSI148_PCFS_PCIXSTAT_FN_M (7<<0) /* Function Number */
@ -646,23 +646,23 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
/*
* Outbound Translation Attribute
*/
#define TSI148_LCSR_OTAT_EN (1<<31) /* Window Enable */
#define TSI148_LCSR_OTAT_MRPFD (1<<18) /* Prefetch Disable */
#define TSI148_LCSR_OTAT_EN BIT(31) /* Window Enable */
#define TSI148_LCSR_OTAT_MRPFD BIT(18) /* Prefetch Disable */
#define TSI148_LCSR_OTAT_PFS_M (3<<16) /* Prefetch Size Mask */
#define TSI148_LCSR_OTAT_PFS_2 (0<<16) /* 2 Cache Lines P Size */
#define TSI148_LCSR_OTAT_PFS_4 (1<<16) /* 4 Cache Lines P Size */
#define TSI148_LCSR_OTAT_PFS_4 BIT(16) /* 4 Cache Lines P Size */
#define TSI148_LCSR_OTAT_PFS_8 (2<<16) /* 8 Cache Lines P Size */
#define TSI148_LCSR_OTAT_PFS_16 (3<<16) /* 16 Cache Lines P Size */
#define TSI148_LCSR_OTAT_2eSSTM_M (7<<11) /* 2eSST Xfer Rate Mask */
#define TSI148_LCSR_OTAT_2eSSTM_160 (0<<11) /* 160MB/s 2eSST Xfer Rate */
#define TSI148_LCSR_OTAT_2eSSTM_267 (1<<11) /* 267MB/s 2eSST Xfer Rate */
#define TSI148_LCSR_OTAT_2eSSTM_267 BIT(11) /* 267MB/s 2eSST Xfer Rate */
#define TSI148_LCSR_OTAT_2eSSTM_320 (2<<11) /* 320MB/s 2eSST Xfer Rate */
#define TSI148_LCSR_OTAT_TM_M (7<<8) /* Xfer Protocol Mask */
#define TSI148_LCSR_OTAT_TM_SCT (0<<8) /* SCT Xfer Protocol */
#define TSI148_LCSR_OTAT_TM_BLT (1<<8) /* BLT Xfer Protocol */
#define TSI148_LCSR_OTAT_TM_BLT BIT(8) /* BLT Xfer Protocol */
#define TSI148_LCSR_OTAT_TM_MBLT (2<<8) /* MBLT Xfer Protocol */
#define TSI148_LCSR_OTAT_TM_2eVME (3<<8) /* 2eVME Xfer Protocol */
#define TSI148_LCSR_OTAT_TM_2eSST (4<<8) /* 2eSST Xfer Protocol */
@ -670,14 +670,14 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
#define TSI148_LCSR_OTAT_DBW_M (3<<6) /* Max Data Width */
#define TSI148_LCSR_OTAT_DBW_16 (0<<6) /* 16-bit Data Width */
#define TSI148_LCSR_OTAT_DBW_32 (1<<6) /* 32-bit Data Width */
#define TSI148_LCSR_OTAT_DBW_32 BIT(6) /* 32-bit Data Width */
#define TSI148_LCSR_OTAT_SUP (1<<5) /* Supervisory Access */
#define TSI148_LCSR_OTAT_PGM (1<<4) /* Program Access */
#define TSI148_LCSR_OTAT_SUP BIT(5) /* Supervisory Access */
#define TSI148_LCSR_OTAT_PGM BIT(4) /* Program Access */
#define TSI148_LCSR_OTAT_AMODE_M (0xf<<0) /* Address Mode Mask */
#define TSI148_LCSR_OTAT_AMODE_A16 (0<<0) /* A16 Address Space */
#define TSI148_LCSR_OTAT_AMODE_A24 (1<<0) /* A24 Address Space */
#define TSI148_LCSR_OTAT_AMODE_A24 BIT(0) /* A24 Address Space */
#define TSI148_LCSR_OTAT_AMODE_A32 (2<<0) /* A32 Address Space */
#define TSI148_LCSR_OTAT_AMODE_A64 (4<<0) /* A32 Address Space */
#define TSI148_LCSR_OTAT_AMODE_CRCSR (5<<0) /* CR/CSR Address Space */
@ -689,17 +689,17 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
/*
* VME Master Control Register CRG+$234
*/
#define TSI148_LCSR_VMCTRL_VSA (1<<27) /* VMEbus Stop Ack */
#define TSI148_LCSR_VMCTRL_VS (1<<26) /* VMEbus Stop */
#define TSI148_LCSR_VMCTRL_DHB (1<<25) /* Device Has Bus */
#define TSI148_LCSR_VMCTRL_DWB (1<<24) /* Device Wants Bus */
#define TSI148_LCSR_VMCTRL_VSA BIT(27) /* VMEbus Stop Ack */
#define TSI148_LCSR_VMCTRL_VS BIT(26) /* VMEbus Stop */
#define TSI148_LCSR_VMCTRL_DHB BIT(25) /* Device Has Bus */
#define TSI148_LCSR_VMCTRL_DWB BIT(24) /* Device Wants Bus */
#define TSI148_LCSR_VMCTRL_RMWEN (1<<20) /* RMW Enable */
#define TSI148_LCSR_VMCTRL_RMWEN BIT(20) /* RMW Enable */
#define TSI148_LCSR_VMCTRL_ATO_M (7<<16) /* Master Access Time-out Mask
*/
#define TSI148_LCSR_VMCTRL_ATO_32 (0<<16) /* 32 us */
#define TSI148_LCSR_VMCTRL_ATO_128 (1<<16) /* 128 us */
#define TSI148_LCSR_VMCTRL_ATO_128 BIT(16) /* 128 us */
#define TSI148_LCSR_VMCTRL_ATO_512 (2<<16) /* 512 us */
#define TSI148_LCSR_VMCTRL_ATO_2M (3<<16) /* 2 ms */
#define TSI148_LCSR_VMCTRL_ATO_8M (4<<16) /* 8 ms */
@ -709,7 +709,7 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
#define TSI148_LCSR_VMCTRL_VTOFF_M (7<<12) /* VMEbus Master Time off */
#define TSI148_LCSR_VMCTRL_VTOFF_0 (0<<12) /* 0us */
#define TSI148_LCSR_VMCTRL_VTOFF_1 (1<<12) /* 1us */
#define TSI148_LCSR_VMCTRL_VTOFF_1 BIT(12) /* 1us */
#define TSI148_LCSR_VMCTRL_VTOFF_2 (2<<12) /* 2us */
#define TSI148_LCSR_VMCTRL_VTOFF_4 (3<<12) /* 4us */
#define TSI148_LCSR_VMCTRL_VTOFF_8 (4<<12) /* 8us */
@ -719,7 +719,7 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
#define TSI148_LCSR_VMCTRL_VTON_M (7<<8) /* VMEbus Master Time On */
#define TSI148_LCSR_VMCTRL_VTON_4 (0<<8) /* 8us */
#define TSI148_LCSR_VMCTRL_VTON_8 (1<<8) /* 8us */
#define TSI148_LCSR_VMCTRL_VTON_8 BIT(8) /* 8us */
#define TSI148_LCSR_VMCTRL_VTON_16 (2<<8) /* 16us */
#define TSI148_LCSR_VMCTRL_VTON_32 (3<<8) /* 32us */
#define TSI148_LCSR_VMCTRL_VTON_64 (4<<8) /* 64us */
@ -730,22 +730,22 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
#define TSI148_LCSR_VMCTRL_VREL_M (3<<3) /* VMEbus Master Rel Mode Mask
*/
#define TSI148_LCSR_VMCTRL_VREL_T_D (0<<3) /* Time on or Done */
#define TSI148_LCSR_VMCTRL_VREL_T_R_D (1<<3) /* Time on and REQ or Done */
#define TSI148_LCSR_VMCTRL_VREL_T_R_D BIT(3) /* Time on and REQ or Done */
#define TSI148_LCSR_VMCTRL_VREL_T_B_D (2<<3) /* Time on and BCLR or Done */
#define TSI148_LCSR_VMCTRL_VREL_T_D_R (3<<3) /* Time on or Done and REQ */
#define TSI148_LCSR_VMCTRL_VFAIR (1<<2) /* VMEbus Master Fair Mode */
#define TSI148_LCSR_VMCTRL_VFAIR BIT(2) /* VMEbus Master Fair Mode */
#define TSI148_LCSR_VMCTRL_VREQL_M (3<<0) /* VMEbus Master Req Level Mask
*/
/*
* VMEbus Control Register CRG+$238
*/
#define TSI148_LCSR_VCTRL_LRE (1<<31) /* Late Retry Enable */
#define TSI148_LCSR_VCTRL_LRE BIT(31) /* Late Retry Enable */
#define TSI148_LCSR_VCTRL_DLT_M (0xF<<24) /* Deadlock Timer */
#define TSI148_LCSR_VCTRL_DLT_OFF (0<<24) /* Deadlock Timer Off */
#define TSI148_LCSR_VCTRL_DLT_16 (1<<24) /* 16 VCLKS */
#define TSI148_LCSR_VCTRL_DLT_16 BIT(24) /* 16 VCLKS */
#define TSI148_LCSR_VCTRL_DLT_32 (2<<24) /* 32 VCLKS */
#define TSI148_LCSR_VCTRL_DLT_64 (3<<24) /* 64 VCLKS */
#define TSI148_LCSR_VCTRL_DLT_128 (4<<24) /* 128 VCLKS */
@ -758,22 +758,22 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
#define TSI148_LCSR_VCTRL_DLT_16384 (0xB<<24) /* 16384 VCLKS */
#define TSI148_LCSR_VCTRL_DLT_32768 (0xC<<24) /* 32768 VCLKS */
#define TSI148_LCSR_VCTRL_NERBB (1<<20) /* No Early Release of Bus Busy
#define TSI148_LCSR_VCTRL_NERBB BIT(20) /* No Early Release of Bus Busy
*/
#define TSI148_LCSR_VCTRL_SRESET (1<<17) /* System Reset */
#define TSI148_LCSR_VCTRL_LRESET (1<<16) /* Local Reset */
#define TSI148_LCSR_VCTRL_SRESET BIT(17) /* System Reset */
#define TSI148_LCSR_VCTRL_LRESET BIT(16) /* Local Reset */
#define TSI148_LCSR_VCTRL_SFAILAI (1<<15) /* SYSFAIL Auto Slot ID */
#define TSI148_LCSR_VCTRL_SFAILAI BIT(15) /* SYSFAIL Auto Slot ID */
#define TSI148_LCSR_VCTRL_BID_M (0x1F<<8) /* Broadcast ID Mask */
#define TSI148_LCSR_VCTRL_ATOEN (1<<7) /* Arbiter Time-out Enable */
#define TSI148_LCSR_VCTRL_ROBIN (1<<6) /* VMEbus Round Robin */
#define TSI148_LCSR_VCTRL_ATOEN BIT(7) /* Arbiter Time-out Enable */
#define TSI148_LCSR_VCTRL_ROBIN BIT(6) /* VMEbus Round Robin */
#define TSI148_LCSR_VCTRL_GTO_M (7<<0) /* VMEbus Global Time-out Mask
*/
#define TSI148_LCSR_VCTRL_GTO_8 (0<<0) /* 8 us */
#define TSI148_LCSR_VCTRL_GTO_16 (1<<0) /* 16 us */
#define TSI148_LCSR_VCTRL_GTO_16 BIT(0) /* 16 us */
#define TSI148_LCSR_VCTRL_GTO_32 (2<<0) /* 32 us */
#define TSI148_LCSR_VCTRL_GTO_64 (3<<0) /* 64 us */
#define TSI148_LCSR_VCTRL_GTO_128 (4<<0) /* 128 us */
@ -784,48 +784,48 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
/*
* VMEbus Status Register CRG + $23C
*/
#define TSI148_LCSR_VSTAT_CPURST (1<<15) /* Clear power up reset */
#define TSI148_LCSR_VSTAT_BRDFL (1<<14) /* Board fail */
#define TSI148_LCSR_VSTAT_PURSTS (1<<12) /* Power up reset status */
#define TSI148_LCSR_VSTAT_BDFAILS (1<<11) /* Board Fail Status */
#define TSI148_LCSR_VSTAT_SYSFAILS (1<<10) /* System Fail Status */
#define TSI148_LCSR_VSTAT_ACFAILS (1<<9) /* AC fail status */
#define TSI148_LCSR_VSTAT_SCONS (1<<8) /* System Cont Status */
#define TSI148_LCSR_VSTAT_GAP (1<<5) /* Geographic Addr Parity */
#define TSI148_LCSR_VSTAT_CPURST BIT(15) /* Clear power up reset */
#define TSI148_LCSR_VSTAT_BRDFL BIT(14) /* Board fail */
#define TSI148_LCSR_VSTAT_PURSTS BIT(12) /* Power up reset status */
#define TSI148_LCSR_VSTAT_BDFAILS BIT(11) /* Board Fail Status */
#define TSI148_LCSR_VSTAT_SYSFAILS BIT(10) /* System Fail Status */
#define TSI148_LCSR_VSTAT_ACFAILS BIT(9) /* AC fail status */
#define TSI148_LCSR_VSTAT_SCONS BIT(8) /* System Cont Status */
#define TSI148_LCSR_VSTAT_GAP BIT(5) /* Geographic Addr Parity */
#define TSI148_LCSR_VSTAT_GA_M (0x1F<<0) /* Geographic Addr Mask */
/*
* PCI Configuration Status Register CRG+$240
*/
#define TSI148_LCSR_PSTAT_REQ64S (1<<6) /* Request 64 status set */
#define TSI148_LCSR_PSTAT_M66ENS (1<<5) /* M66ENS 66Mhz enable */
#define TSI148_LCSR_PSTAT_FRAMES (1<<4) /* Frame Status */
#define TSI148_LCSR_PSTAT_IRDYS (1<<3) /* IRDY status */
#define TSI148_LCSR_PSTAT_DEVSELS (1<<2) /* DEVL status */
#define TSI148_LCSR_PSTAT_STOPS (1<<1) /* STOP status */
#define TSI148_LCSR_PSTAT_TRDYS (1<<0) /* TRDY status */
#define TSI148_LCSR_PSTAT_REQ64S BIT(6) /* Request 64 status set */
#define TSI148_LCSR_PSTAT_M66ENS BIT(5) /* M66ENS 66Mhz enable */
#define TSI148_LCSR_PSTAT_FRAMES BIT(4) /* Frame Status */
#define TSI148_LCSR_PSTAT_IRDYS BIT(3) /* IRDY status */
#define TSI148_LCSR_PSTAT_DEVSELS BIT(2) /* DEVL status */
#define TSI148_LCSR_PSTAT_STOPS BIT(1) /* STOP status */
#define TSI148_LCSR_PSTAT_TRDYS BIT(0) /* TRDY status */
/*
* VMEbus Exception Attributes Register CRG + $268
*/
#define TSI148_LCSR_VEAT_VES (1<<31) /* Status */
#define TSI148_LCSR_VEAT_VEOF (1<<30) /* Overflow */
#define TSI148_LCSR_VEAT_VESCL (1<<29) /* Status Clear */
#define TSI148_LCSR_VEAT_2EOT (1<<21) /* 2e Odd Termination */
#define TSI148_LCSR_VEAT_2EST (1<<20) /* 2e Slave terminated */
#define TSI148_LCSR_VEAT_BERR (1<<19) /* Bus Error */
#define TSI148_LCSR_VEAT_LWORD (1<<18) /* LWORD_ signal state */
#define TSI148_LCSR_VEAT_WRITE (1<<17) /* WRITE_ signal state */
#define TSI148_LCSR_VEAT_IACK (1<<16) /* IACK_ signal state */
#define TSI148_LCSR_VEAT_DS1 (1<<15) /* DS1_ signal state */
#define TSI148_LCSR_VEAT_DS0 (1<<14) /* DS0_ signal state */
#define TSI148_LCSR_VEAT_VES BIT(31) /* Status */
#define TSI148_LCSR_VEAT_VEOF BIT(30) /* Overflow */
#define TSI148_LCSR_VEAT_VESCL BIT(29) /* Status Clear */
#define TSI148_LCSR_VEAT_2EOT BIT(21) /* 2e Odd Termination */
#define TSI148_LCSR_VEAT_2EST BIT(20) /* 2e Slave terminated */
#define TSI148_LCSR_VEAT_BERR BIT(19) /* Bus Error */
#define TSI148_LCSR_VEAT_LWORD BIT(18) /* LWORD_ signal state */
#define TSI148_LCSR_VEAT_WRITE BIT(17) /* WRITE_ signal state */
#define TSI148_LCSR_VEAT_IACK BIT(16) /* IACK_ signal state */
#define TSI148_LCSR_VEAT_DS1 BIT(15) /* DS1_ signal state */
#define TSI148_LCSR_VEAT_DS0 BIT(14) /* DS0_ signal state */
#define TSI148_LCSR_VEAT_AM_M (0x3F<<8) /* Address Mode Mask */
#define TSI148_LCSR_VEAT_XAM_M (0xFF<<0) /* Master AMode Mask */
/*
* VMEbus PCI Error Diagnostics PCI/X Attributes Register CRG + $280
*/
#define TSI148_LCSR_EDPAT_EDPCL (1<<29)
#define TSI148_LCSR_EDPAT_EDPCL BIT(29)
/*
* Inbound Translation Starting Address Lower
@ -851,36 +851,36 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
/*
* Inbound Translation Attribute
*/
#define TSI148_LCSR_ITAT_EN (1<<31) /* Window Enable */
#define TSI148_LCSR_ITAT_TH (1<<18) /* Prefetch Threshold */
#define TSI148_LCSR_ITAT_EN BIT(31) /* Window Enable */
#define TSI148_LCSR_ITAT_TH BIT(18) /* Prefetch Threshold */
#define TSI148_LCSR_ITAT_VFS_M (3<<16) /* Virtual FIFO Size Mask */
#define TSI148_LCSR_ITAT_VFS_64 (0<<16) /* 64 bytes Virtual FIFO Size */
#define TSI148_LCSR_ITAT_VFS_128 (1<<16) /* 128 bytes Virtual FIFO Sz */
#define TSI148_LCSR_ITAT_VFS_128 BIT(16) /* 128 bytes Virtual FIFO Sz */
#define TSI148_LCSR_ITAT_VFS_256 (2<<16) /* 256 bytes Virtual FIFO Sz */
#define TSI148_LCSR_ITAT_VFS_512 (3<<16) /* 512 bytes Virtual FIFO Sz */
#define TSI148_LCSR_ITAT_2eSSTM_M (7<<12) /* 2eSST Xfer Rate Mask */
#define TSI148_LCSR_ITAT_2eSSTM_160 (0<<12) /* 160MB/s 2eSST Xfer Rate */
#define TSI148_LCSR_ITAT_2eSSTM_267 (1<<12) /* 267MB/s 2eSST Xfer Rate */
#define TSI148_LCSR_ITAT_2eSSTM_267 BIT(12) /* 267MB/s 2eSST Xfer Rate */
#define TSI148_LCSR_ITAT_2eSSTM_320 (2<<12) /* 320MB/s 2eSST Xfer Rate */
#define TSI148_LCSR_ITAT_2eSSTB (1<<11) /* 2eSST Bcast Xfer Protocol */
#define TSI148_LCSR_ITAT_2eSST (1<<10) /* 2eSST Xfer Protocol */
#define TSI148_LCSR_ITAT_2eVME (1<<9) /* 2eVME Xfer Protocol */
#define TSI148_LCSR_ITAT_MBLT (1<<8) /* MBLT Xfer Protocol */
#define TSI148_LCSR_ITAT_BLT (1<<7) /* BLT Xfer Protocol */
#define TSI148_LCSR_ITAT_2eSSTB BIT(11) /* 2eSST Bcast Xfer Protocol */
#define TSI148_LCSR_ITAT_2eSST BIT(10) /* 2eSST Xfer Protocol */
#define TSI148_LCSR_ITAT_2eVME BIT(9) /* 2eVME Xfer Protocol */
#define TSI148_LCSR_ITAT_MBLT BIT(8) /* MBLT Xfer Protocol */
#define TSI148_LCSR_ITAT_BLT BIT(7) /* BLT Xfer Protocol */
#define TSI148_LCSR_ITAT_AS_M (7<<4) /* Address Space Mask */
#define TSI148_LCSR_ITAT_AS_A16 (0<<4) /* A16 Address Space */
#define TSI148_LCSR_ITAT_AS_A24 (1<<4) /* A24 Address Space */
#define TSI148_LCSR_ITAT_AS_A24 BIT(4) /* A24 Address Space */
#define TSI148_LCSR_ITAT_AS_A32 (2<<4) /* A32 Address Space */
#define TSI148_LCSR_ITAT_AS_A64 (4<<4) /* A64 Address Space */
#define TSI148_LCSR_ITAT_SUPR (1<<3) /* Supervisor Access */
#define TSI148_LCSR_ITAT_NPRIV (1<<2) /* Non-Priv (User) Access */
#define TSI148_LCSR_ITAT_PGM (1<<1) /* Program Access */
#define TSI148_LCSR_ITAT_DATA (1<<0) /* Data Access */
#define TSI148_LCSR_ITAT_SUPR BIT(3) /* Supervisor Access */
#define TSI148_LCSR_ITAT_NPRIV BIT(2) /* Non-Priv (User) Access */
#define TSI148_LCSR_ITAT_PGM BIT(1) /* Program Access */
#define TSI148_LCSR_ITAT_DATA BIT(0) /* Data Access */
/*
* GCSR Base Address Lower Address CRG +$404
@ -890,18 +890,18 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
/*
* GCSR Attribute Register CRG + $408
*/
#define TSI148_LCSR_GCSRAT_EN (1<<7) /* Enable access to GCSR */
#define TSI148_LCSR_GCSRAT_EN BIT(7) /* Enable access to GCSR */
#define TSI148_LCSR_GCSRAT_AS_M (7<<4) /* Address Space Mask */
#define TSI148_LCSR_GCSRAT_AS_A16 (0<<4) /* Address Space 16 */
#define TSI148_LCSR_GCSRAT_AS_A24 (1<<4) /* Address Space 24 */
#define TSI148_LCSR_GCSRAT_AS_A24 BIT(4) /* Address Space 24 */
#define TSI148_LCSR_GCSRAT_AS_A32 (2<<4) /* Address Space 32 */
#define TSI148_LCSR_GCSRAT_AS_A64 (4<<4) /* Address Space 64 */
#define TSI148_LCSR_GCSRAT_SUPR (1<<3) /* Sup set -GCSR decoder */
#define TSI148_LCSR_GCSRAT_NPRIV (1<<2) /* Non-Privliged set - CGSR */
#define TSI148_LCSR_GCSRAT_PGM (1<<1) /* Program set - GCSR decoder */
#define TSI148_LCSR_GCSRAT_DATA (1<<0) /* DATA set GCSR decoder */
#define TSI148_LCSR_GCSRAT_SUPR BIT(3) /* Sup set -GCSR decoder */
#define TSI148_LCSR_GCSRAT_NPRIV BIT(2) /* Non-Privliged set - CGSR */
#define TSI148_LCSR_GCSRAT_PGM BIT(1) /* Program set - GCSR decoder */
#define TSI148_LCSR_GCSRAT_DATA BIT(0) /* DATA set GCSR decoder */
/*
* CRG Base Address Lower Address CRG + $410
@ -911,18 +911,18 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
/*
* CRG Attribute Register CRG + $414
*/
#define TSI148_LCSR_CRGAT_EN (1<<7) /* Enable PRG Access */
#define TSI148_LCSR_CRGAT_EN BIT(7) /* Enable PRG Access */
#define TSI148_LCSR_CRGAT_AS_M (7<<4) /* Address Space */
#define TSI148_LCSR_CRGAT_AS_A16 (0<<4) /* Address Space 16 */
#define TSI148_LCSR_CRGAT_AS_A24 (1<<4) /* Address Space 24 */
#define TSI148_LCSR_CRGAT_AS_A24 BIT(4) /* Address Space 24 */
#define TSI148_LCSR_CRGAT_AS_A32 (2<<4) /* Address Space 32 */
#define TSI148_LCSR_CRGAT_AS_A64 (4<<4) /* Address Space 64 */
#define TSI148_LCSR_CRGAT_SUPR (1<<3) /* Supervisor Access */
#define TSI148_LCSR_CRGAT_NPRIV (1<<2) /* Non-Privliged(User) Access */
#define TSI148_LCSR_CRGAT_PGM (1<<1) /* Program Access */
#define TSI148_LCSR_CRGAT_DATA (1<<0) /* Data Access */
#define TSI148_LCSR_CRGAT_SUPR BIT(3) /* Supervisor Access */
#define TSI148_LCSR_CRGAT_NPRIV BIT(2) /* Non-Privliged(User) Access */
#define TSI148_LCSR_CRGAT_PGM BIT(1) /* Program Access */
#define TSI148_LCSR_CRGAT_DATA BIT(0) /* Data Access */
/*
* CR/CSR Offset Lower Register CRG + $41C
@ -932,7 +932,7 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
/*
* CR/CSR Attribute register CRG + $420
*/
#define TSI148_LCSR_CRAT_EN (1<<7) /* Enable access to CR/CSR */
#define TSI148_LCSR_CRAT_EN BIT(7) /* Enable access to CR/CSR */
/*
* Location Monitor base address lower register CRG + $428
@ -942,18 +942,18 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
/*
* Location Monitor Attribute Register CRG + $42C
*/
#define TSI148_LCSR_LMAT_EN (1<<7) /* Enable Location Monitor */
#define TSI148_LCSR_LMAT_EN BIT(7) /* Enable Location Monitor */
#define TSI148_LCSR_LMAT_AS_M (7<<4) /* Address Space MASK */
#define TSI148_LCSR_LMAT_AS_A16 (0<<4) /* A16 */
#define TSI148_LCSR_LMAT_AS_A24 (1<<4) /* A24 */
#define TSI148_LCSR_LMAT_AS_A24 BIT(4) /* A24 */
#define TSI148_LCSR_LMAT_AS_A32 (2<<4) /* A32 */
#define TSI148_LCSR_LMAT_AS_A64 (4<<4) /* A64 */
#define TSI148_LCSR_LMAT_SUPR (1<<3) /* Supervisor Access */
#define TSI148_LCSR_LMAT_NPRIV (1<<2) /* Non-Priv (User) Access */
#define TSI148_LCSR_LMAT_PGM (1<<1) /* Program Access */
#define TSI148_LCSR_LMAT_DATA (1<<0) /* Data Access */
#define TSI148_LCSR_LMAT_SUPR BIT(3) /* Supervisor Access */
#define TSI148_LCSR_LMAT_NPRIV BIT(2) /* Non-Priv (User) Access */
#define TSI148_LCSR_LMAT_PGM BIT(1) /* Program Access */
#define TSI148_LCSR_LMAT_DATA BIT(0) /* Data Access */
/*
* Broadcast Pulse Generator Timer Register CRG + $438
@ -969,34 +969,34 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
* VMEbus Interrupt Control Register CRG + $43C
*/
#define TSI148_LCSR_VICR_CNTS_M (3<<22) /* Cntr Source MASK */
#define TSI148_LCSR_VICR_CNTS_DIS (1<<22) /* Cntr Disable */
#define TSI148_LCSR_VICR_CNTS_DIS BIT(22) /* Cntr Disable */
#define TSI148_LCSR_VICR_CNTS_IRQ1 (2<<22) /* IRQ1 to Cntr */
#define TSI148_LCSR_VICR_CNTS_IRQ2 (3<<22) /* IRQ2 to Cntr */
#define TSI148_LCSR_VICR_EDGIS_M (3<<20) /* Edge interrupt MASK */
#define TSI148_LCSR_VICR_EDGIS_DIS (1<<20) /* Edge interrupt Disable */
#define TSI148_LCSR_VICR_EDGIS_DIS BIT(20) /* Edge interrupt Disable */
#define TSI148_LCSR_VICR_EDGIS_IRQ1 (2<<20) /* IRQ1 to Edge */
#define TSI148_LCSR_VICR_EDGIS_IRQ2 (3<<20) /* IRQ2 to Edge */
#define TSI148_LCSR_VICR_IRQIF_M (3<<18) /* IRQ1* Function MASK */
#define TSI148_LCSR_VICR_IRQIF_NORM (1<<18) /* Normal */
#define TSI148_LCSR_VICR_IRQIF_NORM BIT(18) /* Normal */
#define TSI148_LCSR_VICR_IRQIF_PULSE (2<<18) /* Pulse Generator */
#define TSI148_LCSR_VICR_IRQIF_PROG (3<<18) /* Programmable Clock */
#define TSI148_LCSR_VICR_IRQIF_1U (4<<18) /* 1us Clock */
#define TSI148_LCSR_VICR_IRQ2F_M (3<<16) /* IRQ2* Function MASK */
#define TSI148_LCSR_VICR_IRQ2F_NORM (1<<16) /* Normal */
#define TSI148_LCSR_VICR_IRQ2F_NORM BIT(16) /* Normal */
#define TSI148_LCSR_VICR_IRQ2F_PULSE (2<<16) /* Pulse Generator */
#define TSI148_LCSR_VICR_IRQ2F_PROG (3<<16) /* Programmable Clock */
#define TSI148_LCSR_VICR_IRQ2F_1U (4<<16) /* 1us Clock */
#define TSI148_LCSR_VICR_BIP (1<<15) /* Broadcast Interrupt Pulse */
#define TSI148_LCSR_VICR_BIP BIT(15) /* Broadcast Interrupt Pulse */
#define TSI148_LCSR_VICR_IRQC (1<<12) /* VMEbus IRQ Clear */
#define TSI148_LCSR_VICR_IRQS (1<<11) /* VMEbus IRQ Status */
#define TSI148_LCSR_VICR_IRQC BIT(12) /* VMEbus IRQ Clear */
#define TSI148_LCSR_VICR_IRQS BIT(11) /* VMEbus IRQ Status */
#define TSI148_LCSR_VICR_IRQL_M (7<<8) /* VMEbus SW IRQ Level Mask */
#define TSI148_LCSR_VICR_IRQL_1 (1<<8) /* VMEbus SW IRQ Level 1 */
#define TSI148_LCSR_VICR_IRQL_1 BIT(8) /* VMEbus SW IRQ Level 1 */
#define TSI148_LCSR_VICR_IRQL_2 (2<<8) /* VMEbus SW IRQ Level 2 */
#define TSI148_LCSR_VICR_IRQL_3 (3<<8) /* VMEbus SW IRQ Level 3 */
#define TSI148_LCSR_VICR_IRQL_4 (4<<8) /* VMEbus SW IRQ Level 4 */
@ -1014,29 +1014,29 @@ static const int TSI148_LCSR_VICR_IRQL[8] = { 0, TSI148_LCSR_VICR_IRQL_1,
/*
* Interrupt Enable Register CRG + $440
*/
#define TSI148_LCSR_INTEN_DMA1EN (1<<25) /* DMAC 1 */
#define TSI148_LCSR_INTEN_DMA0EN (1<<24) /* DMAC 0 */
#define TSI148_LCSR_INTEN_LM3EN (1<<23) /* Location Monitor 3 */
#define TSI148_LCSR_INTEN_LM2EN (1<<22) /* Location Monitor 2 */
#define TSI148_LCSR_INTEN_LM1EN (1<<21) /* Location Monitor 1 */
#define TSI148_LCSR_INTEN_LM0EN (1<<20) /* Location Monitor 0 */
#define TSI148_LCSR_INTEN_MB3EN (1<<19) /* Mail Box 3 */
#define TSI148_LCSR_INTEN_MB2EN (1<<18) /* Mail Box 2 */
#define TSI148_LCSR_INTEN_MB1EN (1<<17) /* Mail Box 1 */
#define TSI148_LCSR_INTEN_MB0EN (1<<16) /* Mail Box 0 */
#define TSI148_LCSR_INTEN_PERREN (1<<13) /* PCI/X Error */
#define TSI148_LCSR_INTEN_VERREN (1<<12) /* VMEbus Error */
#define TSI148_LCSR_INTEN_VIEEN (1<<11) /* VMEbus IRQ Edge */
#define TSI148_LCSR_INTEN_IACKEN (1<<10) /* IACK */
#define TSI148_LCSR_INTEN_SYSFLEN (1<<9) /* System Fail */
#define TSI148_LCSR_INTEN_ACFLEN (1<<8) /* AC Fail */
#define TSI148_LCSR_INTEN_IRQ7EN (1<<7) /* IRQ7 */
#define TSI148_LCSR_INTEN_IRQ6EN (1<<6) /* IRQ6 */
#define TSI148_LCSR_INTEN_IRQ5EN (1<<5) /* IRQ5 */
#define TSI148_LCSR_INTEN_IRQ4EN (1<<4) /* IRQ4 */
#define TSI148_LCSR_INTEN_IRQ3EN (1<<3) /* IRQ3 */
#define TSI148_LCSR_INTEN_IRQ2EN (1<<2) /* IRQ2 */
#define TSI148_LCSR_INTEN_IRQ1EN (1<<1) /* IRQ1 */
#define TSI148_LCSR_INTEN_DMA1EN BIT(25) /* DMAC 1 */
#define TSI148_LCSR_INTEN_DMA0EN BIT(24) /* DMAC 0 */
#define TSI148_LCSR_INTEN_LM3EN BIT(23) /* Location Monitor 3 */
#define TSI148_LCSR_INTEN_LM2EN BIT(22) /* Location Monitor 2 */
#define TSI148_LCSR_INTEN_LM1EN BIT(21) /* Location Monitor 1 */
#define TSI148_LCSR_INTEN_LM0EN BIT(20) /* Location Monitor 0 */
#define TSI148_LCSR_INTEN_MB3EN BIT(19) /* Mail Box 3 */
#define TSI148_LCSR_INTEN_MB2EN BIT(18) /* Mail Box 2 */
#define TSI148_LCSR_INTEN_MB1EN BIT(17) /* Mail Box 1 */
#define TSI148_LCSR_INTEN_MB0EN BIT(16) /* Mail Box 0 */
#define TSI148_LCSR_INTEN_PERREN BIT(13) /* PCI/X Error */
#define TSI148_LCSR_INTEN_VERREN BIT(12) /* VMEbus Error */
#define TSI148_LCSR_INTEN_VIEEN BIT(11) /* VMEbus IRQ Edge */
#define TSI148_LCSR_INTEN_IACKEN BIT(10) /* IACK */
#define TSI148_LCSR_INTEN_SYSFLEN BIT(9) /* System Fail */
#define TSI148_LCSR_INTEN_ACFLEN BIT(8) /* AC Fail */
#define TSI148_LCSR_INTEN_IRQ7EN BIT(7) /* IRQ7 */
#define TSI148_LCSR_INTEN_IRQ6EN BIT(6) /* IRQ6 */
#define TSI148_LCSR_INTEN_IRQ5EN BIT(5) /* IRQ5 */
#define TSI148_LCSR_INTEN_IRQ4EN BIT(4) /* IRQ4 */
#define TSI148_LCSR_INTEN_IRQ3EN BIT(3) /* IRQ3 */
#define TSI148_LCSR_INTEN_IRQ2EN BIT(2) /* IRQ2 */
#define TSI148_LCSR_INTEN_IRQ1EN BIT(1) /* IRQ1 */
static const int TSI148_LCSR_INTEN_LMEN[4] = { TSI148_LCSR_INTEN_LM0EN,
TSI148_LCSR_INTEN_LM1EN,
@ -1054,29 +1054,29 @@ static const int TSI148_LCSR_INTEN_IRQEN[7] = { TSI148_LCSR_INTEN_IRQ1EN,
/*
* Interrupt Enable Out Register CRG + $444
*/
#define TSI148_LCSR_INTEO_DMA1EO (1<<25) /* DMAC 1 */
#define TSI148_LCSR_INTEO_DMA0EO (1<<24) /* DMAC 0 */
#define TSI148_LCSR_INTEO_LM3EO (1<<23) /* Loc Monitor 3 */
#define TSI148_LCSR_INTEO_LM2EO (1<<22) /* Loc Monitor 2 */
#define TSI148_LCSR_INTEO_LM1EO (1<<21) /* Loc Monitor 1 */
#define TSI148_LCSR_INTEO_LM0EO (1<<20) /* Location Monitor 0 */
#define TSI148_LCSR_INTEO_MB3EO (1<<19) /* Mail Box 3 */
#define TSI148_LCSR_INTEO_MB2EO (1<<18) /* Mail Box 2 */
#define TSI148_LCSR_INTEO_MB1EO (1<<17) /* Mail Box 1 */
#define TSI148_LCSR_INTEO_MB0EO (1<<16) /* Mail Box 0 */
#define TSI148_LCSR_INTEO_PERREO (1<<13) /* PCI/X Error */
#define TSI148_LCSR_INTEO_VERREO (1<<12) /* VMEbus Error */
#define TSI148_LCSR_INTEO_VIEEO (1<<11) /* VMEbus IRQ Edge */
#define TSI148_LCSR_INTEO_IACKEO (1<<10) /* IACK */
#define TSI148_LCSR_INTEO_SYSFLEO (1<<9) /* System Fail */
#define TSI148_LCSR_INTEO_ACFLEO (1<<8) /* AC Fail */
#define TSI148_LCSR_INTEO_IRQ7EO (1<<7) /* IRQ7 */
#define TSI148_LCSR_INTEO_IRQ6EO (1<<6) /* IRQ6 */
#define TSI148_LCSR_INTEO_IRQ5EO (1<<5) /* IRQ5 */
#define TSI148_LCSR_INTEO_IRQ4EO (1<<4) /* IRQ4 */
#define TSI148_LCSR_INTEO_IRQ3EO (1<<3) /* IRQ3 */
#define TSI148_LCSR_INTEO_IRQ2EO (1<<2) /* IRQ2 */
#define TSI148_LCSR_INTEO_IRQ1EO (1<<1) /* IRQ1 */
#define TSI148_LCSR_INTEO_DMA1EO BIT(25) /* DMAC 1 */
#define TSI148_LCSR_INTEO_DMA0EO BIT(24) /* DMAC 0 */
#define TSI148_LCSR_INTEO_LM3EO BIT(23) /* Loc Monitor 3 */
#define TSI148_LCSR_INTEO_LM2EO BIT(22) /* Loc Monitor 2 */
#define TSI148_LCSR_INTEO_LM1EO BIT(21) /* Loc Monitor 1 */
#define TSI148_LCSR_INTEO_LM0EO BIT(20) /* Location Monitor 0 */
#define TSI148_LCSR_INTEO_MB3EO BIT(19) /* Mail Box 3 */
#define TSI148_LCSR_INTEO_MB2EO BIT(18) /* Mail Box 2 */
#define TSI148_LCSR_INTEO_MB1EO BIT(17) /* Mail Box 1 */
#define TSI148_LCSR_INTEO_MB0EO BIT(16) /* Mail Box 0 */
#define TSI148_LCSR_INTEO_PERREO BIT(13) /* PCI/X Error */
#define TSI148_LCSR_INTEO_VERREO BIT(12) /* VMEbus Error */
#define TSI148_LCSR_INTEO_VIEEO BIT(11) /* VMEbus IRQ Edge */
#define TSI148_LCSR_INTEO_IACKEO BIT(10) /* IACK */
#define TSI148_LCSR_INTEO_SYSFLEO BIT(9) /* System Fail */
#define TSI148_LCSR_INTEO_ACFLEO BIT(8) /* AC Fail */
#define TSI148_LCSR_INTEO_IRQ7EO BIT(7) /* IRQ7 */
#define TSI148_LCSR_INTEO_IRQ6EO BIT(6) /* IRQ6 */
#define TSI148_LCSR_INTEO_IRQ5EO BIT(5) /* IRQ5 */
#define TSI148_LCSR_INTEO_IRQ4EO BIT(4) /* IRQ4 */
#define TSI148_LCSR_INTEO_IRQ3EO BIT(3) /* IRQ3 */
#define TSI148_LCSR_INTEO_IRQ2EO BIT(2) /* IRQ2 */
#define TSI148_LCSR_INTEO_IRQ1EO BIT(1) /* IRQ1 */
static const int TSI148_LCSR_INTEO_LMEO[4] = { TSI148_LCSR_INTEO_LM0EO,
TSI148_LCSR_INTEO_LM1EO,
@ -1094,29 +1094,29 @@ static const int TSI148_LCSR_INTEO_IRQEO[7] = { TSI148_LCSR_INTEO_IRQ1EO,
/*
* Interrupt Status Register CRG + $448
*/
#define TSI148_LCSR_INTS_DMA1S (1<<25) /* DMA 1 */
#define TSI148_LCSR_INTS_DMA0S (1<<24) /* DMA 0 */
#define TSI148_LCSR_INTS_LM3S (1<<23) /* Location Monitor 3 */
#define TSI148_LCSR_INTS_LM2S (1<<22) /* Location Monitor 2 */
#define TSI148_LCSR_INTS_LM1S (1<<21) /* Location Monitor 1 */
#define TSI148_LCSR_INTS_LM0S (1<<20) /* Location Monitor 0 */
#define TSI148_LCSR_INTS_MB3S (1<<19) /* Mail Box 3 */
#define TSI148_LCSR_INTS_MB2S (1<<18) /* Mail Box 2 */
#define TSI148_LCSR_INTS_MB1S (1<<17) /* Mail Box 1 */
#define TSI148_LCSR_INTS_MB0S (1<<16) /* Mail Box 0 */
#define TSI148_LCSR_INTS_PERRS (1<<13) /* PCI/X Error */
#define TSI148_LCSR_INTS_VERRS (1<<12) /* VMEbus Error */
#define TSI148_LCSR_INTS_VIES (1<<11) /* VMEbus IRQ Edge */
#define TSI148_LCSR_INTS_IACKS (1<<10) /* IACK */
#define TSI148_LCSR_INTS_SYSFLS (1<<9) /* System Fail */
#define TSI148_LCSR_INTS_ACFLS (1<<8) /* AC Fail */
#define TSI148_LCSR_INTS_IRQ7S (1<<7) /* IRQ7 */
#define TSI148_LCSR_INTS_IRQ6S (1<<6) /* IRQ6 */
#define TSI148_LCSR_INTS_IRQ5S (1<<5) /* IRQ5 */
#define TSI148_LCSR_INTS_IRQ4S (1<<4) /* IRQ4 */
#define TSI148_LCSR_INTS_IRQ3S (1<<3) /* IRQ3 */
#define TSI148_LCSR_INTS_IRQ2S (1<<2) /* IRQ2 */
#define TSI148_LCSR_INTS_IRQ1S (1<<1) /* IRQ1 */
#define TSI148_LCSR_INTS_DMA1S BIT(25) /* DMA 1 */
#define TSI148_LCSR_INTS_DMA0S BIT(24) /* DMA 0 */
#define TSI148_LCSR_INTS_LM3S BIT(23) /* Location Monitor 3 */
#define TSI148_LCSR_INTS_LM2S BIT(22) /* Location Monitor 2 */
#define TSI148_LCSR_INTS_LM1S BIT(21) /* Location Monitor 1 */
#define TSI148_LCSR_INTS_LM0S BIT(20) /* Location Monitor 0 */
#define TSI148_LCSR_INTS_MB3S BIT(19) /* Mail Box 3 */
#define TSI148_LCSR_INTS_MB2S BIT(18) /* Mail Box 2 */
#define TSI148_LCSR_INTS_MB1S BIT(17) /* Mail Box 1 */
#define TSI148_LCSR_INTS_MB0S BIT(16) /* Mail Box 0 */
#define TSI148_LCSR_INTS_PERRS BIT(13) /* PCI/X Error */
#define TSI148_LCSR_INTS_VERRS BIT(12) /* VMEbus Error */
#define TSI148_LCSR_INTS_VIES BIT(11) /* VMEbus IRQ Edge */
#define TSI148_LCSR_INTS_IACKS BIT(10) /* IACK */
#define TSI148_LCSR_INTS_SYSFLS BIT(9) /* System Fail */
#define TSI148_LCSR_INTS_ACFLS BIT(8) /* AC Fail */
#define TSI148_LCSR_INTS_IRQ7S BIT(7) /* IRQ7 */
#define TSI148_LCSR_INTS_IRQ6S BIT(6) /* IRQ6 */
#define TSI148_LCSR_INTS_IRQ5S BIT(5) /* IRQ5 */
#define TSI148_LCSR_INTS_IRQ4S BIT(4) /* IRQ4 */
#define TSI148_LCSR_INTS_IRQ3S BIT(3) /* IRQ3 */
#define TSI148_LCSR_INTS_IRQ2S BIT(2) /* IRQ2 */
#define TSI148_LCSR_INTS_IRQ1S BIT(1) /* IRQ1 */
static const int TSI148_LCSR_INTS_LMS[4] = { TSI148_LCSR_INTS_LM0S,
TSI148_LCSR_INTS_LM1S,
@ -1131,22 +1131,22 @@ static const int TSI148_LCSR_INTS_MBS[4] = { TSI148_LCSR_INTS_MB0S,
/*
* Interrupt Clear Register CRG + $44C
*/
#define TSI148_LCSR_INTC_DMA1C (1<<25) /* DMA 1 */
#define TSI148_LCSR_INTC_DMA0C (1<<24) /* DMA 0 */
#define TSI148_LCSR_INTC_LM3C (1<<23) /* Location Monitor 3 */
#define TSI148_LCSR_INTC_LM2C (1<<22) /* Location Monitor 2 */
#define TSI148_LCSR_INTC_LM1C (1<<21) /* Location Monitor 1 */
#define TSI148_LCSR_INTC_LM0C (1<<20) /* Location Monitor 0 */
#define TSI148_LCSR_INTC_MB3C (1<<19) /* Mail Box 3 */
#define TSI148_LCSR_INTC_MB2C (1<<18) /* Mail Box 2 */
#define TSI148_LCSR_INTC_MB1C (1<<17) /* Mail Box 1 */
#define TSI148_LCSR_INTC_MB0C (1<<16) /* Mail Box 0 */
#define TSI148_LCSR_INTC_PERRC (1<<13) /* VMEbus Error */
#define TSI148_LCSR_INTC_VERRC (1<<12) /* VMEbus Access Time-out */
#define TSI148_LCSR_INTC_VIEC (1<<11) /* VMEbus IRQ Edge */
#define TSI148_LCSR_INTC_IACKC (1<<10) /* IACK */
#define TSI148_LCSR_INTC_SYSFLC (1<<9) /* System Fail */
#define TSI148_LCSR_INTC_ACFLC (1<<8) /* AC Fail */
#define TSI148_LCSR_INTC_DMA1C BIT(25) /* DMA 1 */
#define TSI148_LCSR_INTC_DMA0C BIT(24) /* DMA 0 */
#define TSI148_LCSR_INTC_LM3C BIT(23) /* Location Monitor 3 */
#define TSI148_LCSR_INTC_LM2C BIT(22) /* Location Monitor 2 */
#define TSI148_LCSR_INTC_LM1C BIT(21) /* Location Monitor 1 */
#define TSI148_LCSR_INTC_LM0C BIT(20) /* Location Monitor 0 */
#define TSI148_LCSR_INTC_MB3C BIT(19) /* Mail Box 3 */
#define TSI148_LCSR_INTC_MB2C BIT(18) /* Mail Box 2 */
#define TSI148_LCSR_INTC_MB1C BIT(17) /* Mail Box 1 */
#define TSI148_LCSR_INTC_MB0C BIT(16) /* Mail Box 0 */
#define TSI148_LCSR_INTC_PERRC BIT(13) /* VMEbus Error */
#define TSI148_LCSR_INTC_VERRC BIT(12) /* VMEbus Access Time-out */
#define TSI148_LCSR_INTC_VIEC BIT(11) /* VMEbus IRQ Edge */
#define TSI148_LCSR_INTC_IACKC BIT(10) /* IACK */
#define TSI148_LCSR_INTC_SYSFLC BIT(9) /* System Fail */
#define TSI148_LCSR_INTC_ACFLC BIT(8) /* AC Fail */
static const int TSI148_LCSR_INTC_LMC[4] = { TSI148_LCSR_INTC_LM0C,
TSI148_LCSR_INTC_LM1C,
@ -1192,15 +1192,15 @@ static const int TSI148_LCSR_INTC_MBC[4] = { TSI148_LCSR_INTC_MB0C,
/*
* DMA Control (0-1) Registers CRG + $500
*/
#define TSI148_LCSR_DCTL_ABT (1<<27) /* Abort */
#define TSI148_LCSR_DCTL_PAU (1<<26) /* Pause */
#define TSI148_LCSR_DCTL_DGO (1<<25) /* DMA Go */
#define TSI148_LCSR_DCTL_ABT BIT(27) /* Abort */
#define TSI148_LCSR_DCTL_PAU BIT(26) /* Pause */
#define TSI148_LCSR_DCTL_DGO BIT(25) /* DMA Go */
#define TSI148_LCSR_DCTL_MOD (1<<23) /* Mode */
#define TSI148_LCSR_DCTL_MOD BIT(23) /* Mode */
#define TSI148_LCSR_DCTL_VBKS_M (7<<12) /* VMEbus block Size MASK */
#define TSI148_LCSR_DCTL_VBKS_32 (0<<12) /* VMEbus block Size 32 */
#define TSI148_LCSR_DCTL_VBKS_64 (1<<12) /* VMEbus block Size 64 */
#define TSI148_LCSR_DCTL_VBKS_64 BIT(12) /* VMEbus block Size 64 */
#define TSI148_LCSR_DCTL_VBKS_128 (2<<12) /* VMEbus block Size 128 */
#define TSI148_LCSR_DCTL_VBKS_256 (3<<12) /* VMEbus block Size 256 */
#define TSI148_LCSR_DCTL_VBKS_512 (4<<12) /* VMEbus block Size 512 */
@ -1210,7 +1210,7 @@ static const int TSI148_LCSR_INTC_MBC[4] = { TSI148_LCSR_INTC_MB0C,
#define TSI148_LCSR_DCTL_VBOT_M (7<<8) /* VMEbus back-off MASK */
#define TSI148_LCSR_DCTL_VBOT_0 (0<<8) /* VMEbus back-off 0us */
#define TSI148_LCSR_DCTL_VBOT_1 (1<<8) /* VMEbus back-off 1us */
#define TSI148_LCSR_DCTL_VBOT_1 BIT(8) /* VMEbus back-off 1us */
#define TSI148_LCSR_DCTL_VBOT_2 (2<<8) /* VMEbus back-off 2us */
#define TSI148_LCSR_DCTL_VBOT_4 (3<<8) /* VMEbus back-off 4us */
#define TSI148_LCSR_DCTL_VBOT_8 (4<<8) /* VMEbus back-off 8us */
@ -1220,7 +1220,7 @@ static const int TSI148_LCSR_INTC_MBC[4] = { TSI148_LCSR_INTC_MB0C,
#define TSI148_LCSR_DCTL_PBKS_M (7<<4) /* PCI block size MASK */
#define TSI148_LCSR_DCTL_PBKS_32 (0<<4) /* PCI block size 32 bytes */
#define TSI148_LCSR_DCTL_PBKS_64 (1<<4) /* PCI block size 64 bytes */
#define TSI148_LCSR_DCTL_PBKS_64 BIT(4) /* PCI block size 64 bytes */
#define TSI148_LCSR_DCTL_PBKS_128 (2<<4) /* PCI block size 128 bytes */
#define TSI148_LCSR_DCTL_PBKS_256 (3<<4) /* PCI block size 256 bytes */
#define TSI148_LCSR_DCTL_PBKS_512 (4<<4) /* PCI block size 512 bytes */
@ -1230,7 +1230,7 @@ static const int TSI148_LCSR_INTC_MBC[4] = { TSI148_LCSR_INTC_MB0C,
#define TSI148_LCSR_DCTL_PBOT_M (7<<0) /* PCI back off MASK */
#define TSI148_LCSR_DCTL_PBOT_0 (0<<0) /* PCI back off 0us */
#define TSI148_LCSR_DCTL_PBOT_1 (1<<0) /* PCI back off 1us */
#define TSI148_LCSR_DCTL_PBOT_1 BIT(0) /* PCI back off 1us */
#define TSI148_LCSR_DCTL_PBOT_2 (2<<0) /* PCI back off 2us */
#define TSI148_LCSR_DCTL_PBOT_4 (3<<0) /* PCI back off 3us */
#define TSI148_LCSR_DCTL_PBOT_8 (4<<0) /* PCI back off 4us */
@ -1241,14 +1241,14 @@ static const int TSI148_LCSR_INTC_MBC[4] = { TSI148_LCSR_INTC_MB0C,
/*
* DMA Status Registers (0-1) CRG + $504
*/
#define TSI148_LCSR_DSTA_SMA (1<<31) /* PCI Signalled Master Abt */
#define TSI148_LCSR_DSTA_RTA (1<<30) /* PCI Received Target Abt */
#define TSI148_LCSR_DSTA_MRC (1<<29) /* PCI Max Retry Count */
#define TSI148_LCSR_DSTA_VBE (1<<28) /* VMEbus error */
#define TSI148_LCSR_DSTA_ABT (1<<27) /* Abort */
#define TSI148_LCSR_DSTA_PAU (1<<26) /* Pause */
#define TSI148_LCSR_DSTA_DON (1<<25) /* Done */
#define TSI148_LCSR_DSTA_BSY (1<<24) /* Busy */
#define TSI148_LCSR_DSTA_SMA BIT(31) /* PCI Signalled Master Abt */
#define TSI148_LCSR_DSTA_RTA BIT(30) /* PCI Received Target Abt */
#define TSI148_LCSR_DSTA_MRC BIT(29) /* PCI Max Retry Count */
#define TSI148_LCSR_DSTA_VBE BIT(28) /* VMEbus error */
#define TSI148_LCSR_DSTA_ABT BIT(27) /* Abort */
#define TSI148_LCSR_DSTA_PAU BIT(26) /* Pause */
#define TSI148_LCSR_DSTA_DON BIT(25) /* Done */
#define TSI148_LCSR_DSTA_BSY BIT(24) /* Busy */
/*
* DMA Current Link Address Lower (0-1)
@ -1260,20 +1260,20 @@ static const int TSI148_LCSR_INTC_MBC[4] = { TSI148_LCSR_INTC_MB0C,
*/
#define TSI148_LCSR_DSAT_TYP_M (3<<28) /* Source Bus Type */
#define TSI148_LCSR_DSAT_TYP_PCI (0<<28) /* PCI Bus */
#define TSI148_LCSR_DSAT_TYP_VME (1<<28) /* VMEbus */
#define TSI148_LCSR_DSAT_TYP_VME BIT(28) /* VMEbus */
#define TSI148_LCSR_DSAT_TYP_PAT (2<<28) /* Data Pattern */
#define TSI148_LCSR_DSAT_PSZ (1<<25) /* Pattern Size */
#define TSI148_LCSR_DSAT_NIN (1<<24) /* No Increment */
#define TSI148_LCSR_DSAT_PSZ BIT(25) /* Pattern Size */
#define TSI148_LCSR_DSAT_NIN BIT(24) /* No Increment */
#define TSI148_LCSR_DSAT_2eSSTM_M (3<<11) /* 2eSST Trans Rate Mask */
#define TSI148_LCSR_DSAT_2eSSTM_160 (0<<11) /* 160 MB/s */
#define TSI148_LCSR_DSAT_2eSSTM_267 (1<<11) /* 267 MB/s */
#define TSI148_LCSR_DSAT_2eSSTM_267 BIT(11) /* 267 MB/s */
#define TSI148_LCSR_DSAT_2eSSTM_320 (2<<11) /* 320 MB/s */
#define TSI148_LCSR_DSAT_TM_M (7<<8) /* Bus Transfer Protocol Mask */
#define TSI148_LCSR_DSAT_TM_SCT (0<<8) /* SCT */
#define TSI148_LCSR_DSAT_TM_BLT (1<<8) /* BLT */
#define TSI148_LCSR_DSAT_TM_BLT BIT(8) /* BLT */
#define TSI148_LCSR_DSAT_TM_MBLT (2<<8) /* MBLT */
#define TSI148_LCSR_DSAT_TM_2eVME (3<<8) /* 2eVME */
#define TSI148_LCSR_DSAT_TM_2eSST (4<<8) /* 2eSST */
@ -1281,14 +1281,14 @@ static const int TSI148_LCSR_INTC_MBC[4] = { TSI148_LCSR_INTC_MB0C,
#define TSI148_LCSR_DSAT_DBW_M (3<<6) /* Max Data Width MASK */
#define TSI148_LCSR_DSAT_DBW_16 (0<<6) /* 16 Bits */
#define TSI148_LCSR_DSAT_DBW_32 (1<<6) /* 32 Bits */
#define TSI148_LCSR_DSAT_DBW_32 BIT(6) /* 32 Bits */
#define TSI148_LCSR_DSAT_SUP (1<<5) /* Supervisory Mode */
#define TSI148_LCSR_DSAT_PGM (1<<4) /* Program Mode */
#define TSI148_LCSR_DSAT_SUP BIT(5) /* Supervisory Mode */
#define TSI148_LCSR_DSAT_PGM BIT(4) /* Program Mode */
#define TSI148_LCSR_DSAT_AMODE_M (0xf<<0) /* Address Space Mask */
#define TSI148_LCSR_DSAT_AMODE_A16 (0<<0) /* A16 */
#define TSI148_LCSR_DSAT_AMODE_A24 (1<<0) /* A24 */
#define TSI148_LCSR_DSAT_AMODE_A24 BIT(0) /* A24 */
#define TSI148_LCSR_DSAT_AMODE_A32 (2<<0) /* A32 */
#define TSI148_LCSR_DSAT_AMODE_A64 (4<<0) /* A64 */
#define TSI148_LCSR_DSAT_AMODE_CRCSR (5<<0) /* CR/CSR */
@ -1301,16 +1301,16 @@ static const int TSI148_LCSR_INTC_MBC[4] = { TSI148_LCSR_INTC_MB0C,
* DMA Destination Attribute Registers (0-1)
*/
#define TSI148_LCSR_DDAT_TYP_PCI (0<<28) /* Destination PCI Bus */
#define TSI148_LCSR_DDAT_TYP_VME (1<<28) /* Destination VMEbus */
#define TSI148_LCSR_DDAT_TYP_VME BIT(28) /* Destination VMEbus */
#define TSI148_LCSR_DDAT_2eSSTM_M (3<<11) /* 2eSST Transfer Rate Mask */
#define TSI148_LCSR_DDAT_2eSSTM_160 (0<<11) /* 160 MB/s */
#define TSI148_LCSR_DDAT_2eSSTM_267 (1<<11) /* 267 MB/s */
#define TSI148_LCSR_DDAT_2eSSTM_267 BIT(11) /* 267 MB/s */
#define TSI148_LCSR_DDAT_2eSSTM_320 (2<<11) /* 320 MB/s */
#define TSI148_LCSR_DDAT_TM_M (7<<8) /* Bus Transfer Protocol Mask */
#define TSI148_LCSR_DDAT_TM_SCT (0<<8) /* SCT */
#define TSI148_LCSR_DDAT_TM_BLT (1<<8) /* BLT */
#define TSI148_LCSR_DDAT_TM_BLT BIT(8) /* BLT */
#define TSI148_LCSR_DDAT_TM_MBLT (2<<8) /* MBLT */
#define TSI148_LCSR_DDAT_TM_2eVME (3<<8) /* 2eVME */
#define TSI148_LCSR_DDAT_TM_2eSST (4<<8) /* 2eSST */
@ -1318,14 +1318,14 @@ static const int TSI148_LCSR_INTC_MBC[4] = { TSI148_LCSR_INTC_MB0C,
#define TSI148_LCSR_DDAT_DBW_M (3<<6) /* Max Data Width MASK */
#define TSI148_LCSR_DDAT_DBW_16 (0<<6) /* 16 Bits */
#define TSI148_LCSR_DDAT_DBW_32 (1<<6) /* 32 Bits */
#define TSI148_LCSR_DDAT_DBW_32 BIT(6) /* 32 Bits */
#define TSI148_LCSR_DDAT_SUP (1<<5) /* Supervisory/User Access */
#define TSI148_LCSR_DDAT_PGM (1<<4) /* Program/Data Access */
#define TSI148_LCSR_DDAT_SUP BIT(5) /* Supervisory/User Access */
#define TSI148_LCSR_DDAT_PGM BIT(4) /* Program/Data Access */
#define TSI148_LCSR_DDAT_AMODE_M (0xf<<0) /* Address Space Mask */
#define TSI148_LCSR_DDAT_AMODE_A16 (0<<0) /* A16 */
#define TSI148_LCSR_DDAT_AMODE_A24 (1<<0) /* A24 */
#define TSI148_LCSR_DDAT_AMODE_A24 BIT(0) /* A24 */
#define TSI148_LCSR_DDAT_AMODE_A32 (2<<0) /* A32 */
#define TSI148_LCSR_DDAT_AMODE_A64 (4<<0) /* A64 */
#define TSI148_LCSR_DDAT_AMODE_CRCSR (5<<0) /* CRC/SR */
@ -1338,7 +1338,7 @@ static const int TSI148_LCSR_INTC_MBC[4] = { TSI148_LCSR_INTC_MB0C,
* DMA Next Link Address Lower
*/
#define TSI148_LCSR_DNLAL_DNLAL_M (0x3FFFFFF<<6) /* Address Mask */
#define TSI148_LCSR_DNLAL_LLA (1<<0) /* Last Link Address Indicator */
#define TSI148_LCSR_DNLAL_LLA BIT(0) /* Last Link Address Indicator */
/*
* DMA 2eSST Broadcast Select
@ -1352,22 +1352,22 @@ static const int TSI148_LCSR_INTC_MBC[4] = { TSI148_LCSR_INTC_MB0C,
/*
* GCSR Control and Status Register CRG + $604
*/
#define TSI148_GCSR_GCTRL_LRST (1<<15) /* Local Reset */
#define TSI148_GCSR_GCTRL_SFAILEN (1<<14) /* System Fail enable */
#define TSI148_GCSR_GCTRL_BDFAILS (1<<13) /* Board Fail Status */
#define TSI148_GCSR_GCTRL_SCON (1<<12) /* System Copntroller */
#define TSI148_GCSR_GCTRL_MEN (1<<11) /* Module Enable (READY) */
#define TSI148_GCSR_GCTRL_LRST BIT(15) /* Local Reset */
#define TSI148_GCSR_GCTRL_SFAILEN BIT(14) /* System Fail enable */
#define TSI148_GCSR_GCTRL_BDFAILS BIT(13) /* Board Fail Status */
#define TSI148_GCSR_GCTRL_SCON BIT(12) /* System Copntroller */
#define TSI148_GCSR_GCTRL_MEN BIT(11) /* Module Enable (READY) */
#define TSI148_GCSR_GCTRL_LMI3S (1<<7) /* Loc Monitor 3 Int Status */
#define TSI148_GCSR_GCTRL_LMI2S (1<<6) /* Loc Monitor 2 Int Status */
#define TSI148_GCSR_GCTRL_LMI1S (1<<5) /* Loc Monitor 1 Int Status */
#define TSI148_GCSR_GCTRL_LMI0S (1<<4) /* Loc Monitor 0 Int Status */
#define TSI148_GCSR_GCTRL_MBI3S (1<<3) /* Mail box 3 Int Status */
#define TSI148_GCSR_GCTRL_MBI2S (1<<2) /* Mail box 2 Int Status */
#define TSI148_GCSR_GCTRL_MBI1S (1<<1) /* Mail box 1 Int Status */
#define TSI148_GCSR_GCTRL_MBI0S (1<<0) /* Mail box 0 Int Status */
#define TSI148_GCSR_GCTRL_LMI3S BIT(7) /* Loc Monitor 3 Int Status */
#define TSI148_GCSR_GCTRL_LMI2S BIT(6) /* Loc Monitor 2 Int Status */
#define TSI148_GCSR_GCTRL_LMI1S BIT(5) /* Loc Monitor 1 Int Status */
#define TSI148_GCSR_GCTRL_LMI0S BIT(4) /* Loc Monitor 0 Int Status */
#define TSI148_GCSR_GCTRL_MBI3S BIT(3) /* Mail box 3 Int Status */
#define TSI148_GCSR_GCTRL_MBI2S BIT(2) /* Mail box 2 Int Status */
#define TSI148_GCSR_GCTRL_MBI1S BIT(1) /* Mail box 1 Int Status */
#define TSI148_GCSR_GCTRL_MBI0S BIT(0) /* Mail box 0 Int Status */
#define TSI148_GCSR_GAP (1<<5) /* Geographic Addr Parity */
#define TSI148_GCSR_GAP BIT(5) /* Geographic Addr Parity */
#define TSI148_GCSR_GA_M (0x1F<<0) /* Geographic Address Mask */
/*
@ -1377,20 +1377,20 @@ static const int TSI148_LCSR_INTC_MBC[4] = { TSI148_LCSR_INTC_MB0C,
/*
* CR/CSR Bit Clear Register CRG + $FF4
*/
#define TSI148_CRCSR_CSRBCR_LRSTC (1<<7) /* Local Reset Clear */
#define TSI148_CRCSR_CSRBCR_SFAILC (1<<6) /* System Fail Enable Clear */
#define TSI148_CRCSR_CSRBCR_BDFAILS (1<<5) /* Board Fail Status */
#define TSI148_CRCSR_CSRBCR_MENC (1<<4) /* Module Enable Clear */
#define TSI148_CRCSR_CSRBCR_BERRSC (1<<3) /* Bus Error Status Clear */
#define TSI148_CRCSR_CSRBCR_LRSTC BIT(7) /* Local Reset Clear */
#define TSI148_CRCSR_CSRBCR_SFAILC BIT(6) /* System Fail Enable Clear */
#define TSI148_CRCSR_CSRBCR_BDFAILS BIT(5) /* Board Fail Status */
#define TSI148_CRCSR_CSRBCR_MENC BIT(4) /* Module Enable Clear */
#define TSI148_CRCSR_CSRBCR_BERRSC BIT(3) /* Bus Error Status Clear */
/*
* CR/CSR Bit Set Register CRG+$FF8
*/
#define TSI148_CRCSR_CSRBSR_LISTS (1<<7) /* Local Reset Clear */
#define TSI148_CRCSR_CSRBSR_SFAILS (1<<6) /* System Fail Enable Clear */
#define TSI148_CRCSR_CSRBSR_BDFAILS (1<<5) /* Board Fail Status */
#define TSI148_CRCSR_CSRBSR_MENS (1<<4) /* Module Enable Clear */
#define TSI148_CRCSR_CSRBSR_BERRS (1<<3) /* Bus Error Status Clear */
#define TSI148_CRCSR_CSRBSR_LISTS BIT(7) /* Local Reset Clear */
#define TSI148_CRCSR_CSRBSR_SFAILS BIT(6) /* System Fail Enable Clear */
#define TSI148_CRCSR_CSRBSR_BDFAILS BIT(5) /* Board Fail Status */
#define TSI148_CRCSR_CSRBSR_MENS BIT(4) /* Module Enable Clear */
#define TSI148_CRCSR_CSRBSR_BERRS BIT(3) /* Bus Error Status Clear */
/*
* CR/CSR Base Address Register CRG + FFC

44
drivers/staging/vt6655/baseband.c
View File

@ -2171,50 +2171,6 @@ bb_software_reset(struct vnt_private *priv)
bb_write_embedded(priv, 0x9C, 0);
}
/*
* Description: Baseband Power Save Mode ON
*
* Parameters:
* In:
* iobase - I/O base address
* Out:
* none
*
* Return Value: none
*
*/
void
bb_power_save_mode_on(struct vnt_private *priv)
{
unsigned char by_org_data;
bb_read_embedded(priv, 0x0D, &by_org_data);
by_org_data |= BIT(0);
bb_write_embedded(priv, 0x0D, by_org_data);
}
/*
* Description: Baseband Power Save Mode OFF
*
* Parameters:
* In:
* iobase - I/O base address
* Out:
* none
*
* Return Value: none
*
*/
void
bb_power_save_mode_off(struct vnt_private *priv)
{
unsigned char by_org_data;
bb_read_embedded(priv, 0x0D, &by_org_data);
by_org_data &= ~(BIT(0));
bb_write_embedded(priv, 0x0D, by_org_data);
}
/*
* Description: Set Tx Antenna mode
*

2
drivers/staging/vt6655/baseband.h
View File

@ -63,8 +63,6 @@ void bb_set_vga_gain_offset(struct vnt_private *priv, unsigned char by_data);
/* VT3253 Baseband */
bool bb_vt3253_init(struct vnt_private *priv);
void bb_software_reset(struct vnt_private *priv);
void bb_power_save_mode_on(struct vnt_private *priv);
void bb_power_save_mode_off(struct vnt_private *priv);
void bb_set_tx_antenna_mode(struct vnt_private *priv,
unsigned char by_antenna_mode);
void bb_set_rx_antenna_mode(struct vnt_private *priv,

21
drivers/staging/vt6656/card.c
View File

@ -11,7 +11,6 @@
* vnt_add_basic_rate - Add to BasicRateSet
* vnt_ofdm_min_rate - Check if any OFDM rate is in BasicRateSet
* vnt_get_tsf_offset - Calculate TSFOffset
* vnt_get_current_tsf - Read Current NIC TSF counter
* vnt_get_next_tbtt - Calculate Next Beacon TSF counter
* vnt_reset_next_tbtt - Set NIC Beacon time
* vnt_update_next_tbtt - Sync. NIC Beacon time
@ -230,26 +229,6 @@ int vnt_adjust_tsf(struct vnt_private *priv, u8 rx_rate,
MESSAGE_REQUEST_TSF, 0, 8, data);
}
/*
* Description: Read NIC TSF counter
* Get local TSF counter
*
* Parameters:
* In:
* priv - The adapter to be read
* Out:
* current_tsf - Current TSF counter
*
* Return Value: true if success; otherwise false
*
*/
bool vnt_get_current_tsf(struct vnt_private *priv, u64 *current_tsf)
{
*current_tsf = priv->current_tsf;
return true;
}
/*
* Description: Clear NIC TSF counter
* Clear local TSF counter

1
drivers/staging/vt6656/card.h
View File

@ -30,7 +30,6 @@ void vnt_update_top_rates(struct vnt_private *priv);
bool vnt_ofdm_min_rate(struct vnt_private *priv);
int vnt_adjust_tsf(struct vnt_private *priv, u8 rx_rate,
u64 time_stamp, u64 local_tsf);
bool vnt_get_current_tsf(struct vnt_private *priv, u64 *current_tsf);
bool vnt_clear_current_tsf(struct vnt_private *priv);
int vnt_reset_next_tbtt(struct vnt_private *priv, u16 beacon_interval);
int vnt_update_next_tbtt(struct vnt_private *priv, u64 tsf,

8
drivers/staging/wlan-ng/prism2fw.c
View File

@ -689,6 +689,7 @@ static int plugimage(struct imgchunk *fchunk, unsigned int nfchunks,
for (i = 0; i < ns3plug; i++) {
pstart = s3plug[i].addr;
pend = s3plug[i].addr + s3plug[i].len;
j = -1;
/* find the matching PDR (or filename) */
if (s3plug[i].itemcode != 0xffffffffUL) { /* not filename */
for (j = 0; j < pda->nrec; j++) {
@ -696,8 +697,6 @@ static int plugimage(struct imgchunk *fchunk, unsigned int nfchunks,
le16_to_cpu(pda->rec[j]->code))
break;
}
} else {
j = -1;
}
if (j >= pda->nrec && j != -1) { /* if no matching PDR, fail */
pr_warn("warning: Failed to find PDR for plugrec 0x%04x.\n",
@ -1008,12 +1007,11 @@ static int writeimage(struct wlandevice *wlandev, struct imgchunk *fchunk,
rstmsg = kzalloc(sizeof(*rstmsg), GFP_KERNEL);
rwrmsg = kzalloc(sizeof(*rwrmsg), GFP_KERNEL);
if (!rstmsg || !rwrmsg) {
kfree(rstmsg);
kfree(rwrmsg);
netdev_err(wlandev->netdev,
"%s: no memory for firmware download, aborting download\n",
__func__);
return -ENOMEM;
result = -ENOMEM;
goto free_result;
}
/* Initialize the messages */