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ARM: OMAP1: dmtimer: conversion to platform devices
Convert OMAP1 dmtimers into a platform devices and then registers with device model framework so that it can be bound to corresponding driver. Signed-off-by: Thara Gopinath <thara@ti.com> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Cousson, Benoit <b-cousson@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tarun Kanti DebBarma
Tony Lindgren
parent
318c3e15cd
commit
97933d6ced
@ -4,7 +4,7 @@
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# Common support
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obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o
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obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o
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obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o timer.o
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obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
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173
arch/arm/mach-omap1/timer.c
Normal file
173
arch/arm/mach-omap1/timer.c
Normal file
@ -0,0 +1,173 @@
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/**
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* OMAP1 Dual-Mode Timers - platform device registration
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*
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* Contains first level initialization routines which internally
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* generates timer device information and registers with linux
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* device model. It also has low level function to chnage the timer
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* input clock source.
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*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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* Tarun Kanti DebBarma <tarun.kanti@ti.com>
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* Thara Gopinath <thara@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <mach/irqs.h>
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#include <plat/dmtimer.h>
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#define OMAP1610_GPTIMER1_BASE 0xfffb1400
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#define OMAP1610_GPTIMER2_BASE 0xfffb1c00
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#define OMAP1610_GPTIMER3_BASE 0xfffb2400
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#define OMAP1610_GPTIMER4_BASE 0xfffb2c00
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#define OMAP1610_GPTIMER5_BASE 0xfffb3400
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#define OMAP1610_GPTIMER6_BASE 0xfffb3c00
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#define OMAP1610_GPTIMER7_BASE 0xfffb7400
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#define OMAP1610_GPTIMER8_BASE 0xfffbd400
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#define OMAP1_DM_TIMER_COUNT 8
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static int omap1_dm_timer_set_src(struct platform_device *pdev,
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int source)
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{
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int n = (pdev->id - 1) << 1;
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u32 l;
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l = __raw_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
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l |= source << n;
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__raw_writel(l, MOD_CONF_CTRL_1);
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return 0;
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}
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int __init omap1_dm_timer_init(void)
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{
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int i;
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int ret;
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struct dmtimer_platform_data *pdata;
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struct platform_device *pdev;
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if (!cpu_is_omap16xx())
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return 0;
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for (i = 1; i <= OMAP1_DM_TIMER_COUNT; i++) {
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struct resource res[2];
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u32 base, irq;
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switch (i) {
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case 1:
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base = OMAP1610_GPTIMER1_BASE;
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irq = INT_1610_GPTIMER1;
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break;
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case 2:
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base = OMAP1610_GPTIMER2_BASE;
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irq = INT_1610_GPTIMER2;
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break;
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case 3:
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base = OMAP1610_GPTIMER3_BASE;
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irq = INT_1610_GPTIMER3;
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break;
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case 4:
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base = OMAP1610_GPTIMER4_BASE;
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irq = INT_1610_GPTIMER4;
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break;
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case 5:
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base = OMAP1610_GPTIMER5_BASE;
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irq = INT_1610_GPTIMER5;
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break;
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case 6:
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base = OMAP1610_GPTIMER6_BASE;
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irq = INT_1610_GPTIMER6;
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break;
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case 7:
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base = OMAP1610_GPTIMER7_BASE;
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irq = INT_1610_GPTIMER7;
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break;
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case 8:
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base = OMAP1610_GPTIMER8_BASE;
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irq = INT_1610_GPTIMER8;
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break;
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default:
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/*
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* not supposed to reach here.
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* this is to remove warning.
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*/
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return -EINVAL;
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}
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pdev = platform_device_alloc("omap_timer", i);
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if (!pdev) {
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pr_err("%s: Failed to device alloc for dmtimer%d\n",
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__func__, i);
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return -ENOMEM;
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}
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memset(res, 0, 2 * sizeof(struct resource));
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res[0].start = base;
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res[0].end = base + 0x46;
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res[0].flags = IORESOURCE_MEM;
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res[1].start = irq;
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res[1].end = irq;
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res[1].flags = IORESOURCE_IRQ;
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ret = platform_device_add_resources(pdev, res,
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ARRAY_SIZE(res));
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if (ret) {
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dev_err(&pdev->dev, "%s: Failed to add resources.\n",
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__func__);
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goto err_free_pdev;
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}
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pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
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if (!pdata) {
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dev_err(&pdev->dev, "%s: Failed to allocate pdata.\n",
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__func__);
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ret = -ENOMEM;
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goto err_free_pdata;
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}
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pdata->set_timer_src = omap1_dm_timer_set_src;
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pdata->needs_manual_reset = 1;
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ret = platform_device_add_data(pdev, pdata, sizeof(*pdata));
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if (ret) {
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dev_err(&pdev->dev, "%s: Failed to add platform data.\n",
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__func__);
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goto err_free_pdata;
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}
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ret = platform_device_add(pdev);
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if (ret) {
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dev_err(&pdev->dev, "%s: Failed to add platform device.\n",
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__func__);
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goto err_free_pdata;
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}
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dev_dbg(&pdev->dev, " Registered.\n");
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}
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return 0;
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err_free_pdata:
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kfree(pdata);
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err_free_pdev:
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platform_device_unregister(pdev);
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return ret;
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}
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arch_initcall(omap1_dm_timer_init);
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@ -3,6 +3,12 @@
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*
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* OMAP Dual-Mode Timers
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*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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* Tarun Kanti DebBarma <tarun.kanti@ti.com>
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* Thara Gopinath <thara@ti.com>
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*
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* dmtimer adaptation to platform_driver.
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*
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* Copyright (C) 2005 Nokia Corporation
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* OMAP2 support by Juha Yrjola
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* API improvements and OMAP2 clock framework support by Timo Teras
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@ -43,25 +49,6 @@
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static int dm_timer_count;
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#ifdef CONFIG_ARCH_OMAP1
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static struct omap_dm_timer omap1_dm_timers[] = {
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{ .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
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{ .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
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{ .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
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{ .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 },
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{ .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 },
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{ .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 },
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{ .phys_base = 0xfffb7400, .irq = INT_1610_GPTIMER7 },
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{ .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 },
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};
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static const int omap1_dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
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#else
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#define omap1_dm_timers NULL
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#define omap1_dm_timer_count 0
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#endif /* CONFIG_ARCH_OMAP1 */
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#ifdef CONFIG_ARCH_OMAP2
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static struct omap_dm_timer omap2_dm_timers[] = {
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{ .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
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@ -410,35 +397,20 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer)
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
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#ifdef CONFIG_ARCH_OMAP1
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int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
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{
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int n = (timer - dm_timers) << 1;
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u32 l;
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l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
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l |= source << n;
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omap_writel(l, MOD_CONF_CTRL_1);
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return 0;
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
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#else
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int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
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{
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if (source < 0 || source >= 3)
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return -EINVAL;
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#ifdef CONFIG_ARCH_OMAP2PLUS
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return __omap_dm_timer_set_source(timer->fclk,
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dm_source_clocks[source]);
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#else
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return 0;
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#endif
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
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#endif
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void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
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unsigned int load)
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{
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@ -582,16 +554,12 @@ static int __init omap_dm_timer_init(void)
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struct omap_dm_timer *timer;
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int i, map_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
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if (!(cpu_is_omap16xx() || cpu_class_is_omap2()))
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if (!cpu_class_is_omap2())
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return -ENODEV;
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spin_lock_init(&dm_timer_lock);
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if (cpu_class_is_omap1()) {
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dm_timers = omap1_dm_timers;
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dm_timer_count = omap1_dm_timer_count;
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map_size = SZ_2K;
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} else if (cpu_is_omap24xx()) {
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if (cpu_is_omap24xx()) {
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dm_timers = omap2_dm_timers;
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dm_timer_count = omap2_dm_timer_count;
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dm_source_names = omap2_dm_source_names;
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@ -35,6 +35,7 @@
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#ifndef __ASM_ARCH_DMTIMER_H
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#define __ASM_ARCH_DMTIMER_H
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@ -62,6 +63,12 @@
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struct omap_dm_timer;
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struct clk;
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struct dmtimer_platform_data {
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int (*set_timer_src)(struct platform_device *pdev, int source);
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int timer_ip_version;
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u32 needs_manual_reset:1;
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};
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struct omap_dm_timer *omap_dm_timer_request(void);
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struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
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void omap_dm_timer_free(struct omap_dm_timer *timer);
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@ -228,6 +235,7 @@ struct omap_dm_timer {
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unsigned reserved:1;
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unsigned enabled:1;
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unsigned posted:1;
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struct platform_device *pdev;
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};
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extern u32 sys_timer_reserved;
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