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sh_eth: fix EESIPR values for SH77{34|63}
As the SH77{34|63} manuals are freely available, I've checked the EESIPR values written against the manuals, and they appeared to set the reserved bits 11-15 (which should be 0 on write). Fix those EESIPR values. Fixes:380af9e390
("net: sh_eth: CPU dependency code collect to "struct sh_eth_cpu_data"") Fixes:f5d12767c8
("sh_eth: get SH77{34|63} support out of #ifdef") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -802,7 +802,7 @@ static struct sh_eth_cpu_data sh7734_data = {
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.ecsr_value = ECSR_ICD | ECSR_MPD,
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.ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
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.eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
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.eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003f07ff,
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.tx_check = EESR_TC1 | EESR_FTC,
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.eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
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@ -832,7 +832,7 @@ static struct sh_eth_cpu_data sh7763_data = {
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.ecsr_value = ECSR_ICD | ECSR_MPD,
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.ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
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.eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
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.eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003f07ff,
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.tx_check = EESR_TC1 | EESR_FTC,
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.eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
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