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i.MX arm64 device tree update for 5.19:

Browse Source 
- New board support: Engicam i.Core MX8M Plus SoM and EDIMM2.2 Starter
   Kit, Toradex Verdin i.MX8M Plus devices, Data Modul i.MX8M Mini eDM SBC,
   Verdin based MX8Menlo, 8MNANOD3L EVK, i.MX8M Plus Gateworks GW7400.
 - Enable RTS-CTS on UART3 for imx8mm-beacon and imx8mn-beacon boards.
 - Enable HS400-ES support for i.MX8MN and i.MX8MP uSDHC devices by
   updating the compatible.
 - A few updates on imx8mq-librem5 to increase boost regulation
   current, add panel compatible for r4 ("Evergreen") revision and volume
   buttons a wakeup source.
 - Clean up vendor specific 'fsl,uart-has-rtscts' property by using
   standard 'uart-has-rtscts'.
 - Add GPC, GPU, MEDIAMIX, and HSIO power domains for i.MX8M Plus SoC.
 - A series from Marcel Ziswiler to improve imx8mm-verdin support,
   including cosmetic changes and functional improvements like SD1 sleep
   pinctrl and fully validated IOMUX configuration.
 - Add PWM polarity inversion support for i.MX8 SoCs.
 - A couple of changes from Michael Walle to update PMIC output names and
   min/max voltages for imx8mn-evk board.
 - A series from Tim Harvey to improve imx8mm-venice boards, add missing
   uart-has-rtscts property to UARTs, clock-names to pcie_phy, and
   vdd_5p0 ADC channel.
 - Add VPU codec  devices for i.MX8QXP SoC.
 - Other small and random changes.
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Merge tag 'imx-dt64-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX arm64 device tree update for 5.19:

- New board support: Engicam i.Core MX8M Plus SoM and EDIMM2.2 Starter
  Kit, Toradex Verdin i.MX8M Plus devices, Data Modul i.MX8M Mini eDM SBC,
  Verdin based MX8Menlo, 8MNANOD3L EVK, i.MX8M Plus Gateworks GW7400.
- Enable RTS-CTS on UART3 for imx8mm-beacon and imx8mn-beacon boards.
- Enable HS400-ES support for i.MX8MN and i.MX8MP uSDHC devices by
  updating the compatible.
- A few updates on imx8mq-librem5 to increase boost regulation
  current, add panel compatible for r4 ("Evergreen") revision and volume
  buttons a wakeup source.
- Clean up vendor specific 'fsl,uart-has-rtscts' property by using
  standard 'uart-has-rtscts'.
- Add GPC, GPU, MEDIAMIX, and HSIO power domains for i.MX8M Plus SoC.
- A series from Marcel Ziswiler to improve imx8mm-verdin support,
  including cosmetic changes and functional improvements like SD1 sleep
  pinctrl and fully validated IOMUX configuration.
- Add PWM polarity inversion support for i.MX8 SoCs.
- A couple of changes from Michael Walle to update PMIC output names and
  min/max voltages for imx8mn-evk board.
- A series from Tim Harvey to improve imx8mm-venice boards, add missing
  uart-has-rtscts property to UARTs, clock-names to pcie_phy, and
  vdd_5p0 ADC channel.
- Add VPU codec  devices for i.MX8QXP SoC.
- Other small and random changes.

* tag 'imx-dt64-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (65 commits)
  arm64: dt: imx8mp: support pwm polarity inversion
  arm64: dt: imx8mn: support pwm polarity inversion
  arm64: dt: imx8mm: support pwm polarity inversion
  arm64: dt: imx8mq: support pwm polarity inversion
  arm64: dts: imx8mm-venice-gw7901: remove unnecessary cpu temp override
  arm64: dts: imx8mm-venice-gw7902: add vdd_5p0 ADC channel
  arm64: dts: imx8m*venice: add missing clock-names to pcie_phy
  arm64: dts: imx8mm-venice-gw7902: fix pcie bindings
  arm64: dts: freescale: reduce the interrup-map-mask
  arm64: dts: imx8mn-beacon: Enable RTS-CTS on UART3
  arm64: dts: imx8mm-beacon: Enable RTS-CTS on UART3
  arm64: dts: imx8mm: Use 100 kHz I2C2 on Data Modul i.MX8M Mini eDM SBC
  arm64: dts: imx8mm: Disable USB2 OC on Data Modul i.MX8M Mini eDM SBC
  arm64: dts: imx8mm: Add CPLD on MX8Menlo board
  arm64: dts: imx8mq-kontron-pitx-imx8m: Use the standard 'uart-has-rtscts'
  arm64: dts: imx8mp-verdin: Use the standard 'uart-has-rtscts'
  arm64: dts: imx8mp: Add MEDIA_BLK_CTRL
  arm64: dts: imx8mp: Add MEDIAMIX power domains
  arm64: dts: imx8mp: add HSIO power-domains
  arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit
  ...

Link: https://lore.kernel.org/r/20220508033843.2773685-4-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-05-09 23:46:17 +02:00
commit 977389aabe
58 changed files with 5355 additions and 314 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
arch/arm64/boot/dts/freescale/Makefile
View File

@ -49,12 +49,14 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
@ -72,12 +74,19 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2pro.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr3l-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-kontron-pitx-imx8m.dtb

9
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts
View File

@ -311,10 +311,19 @@
status = "okay";
};
&mscc_felix_port4 {
dsa-tag-protocol = "ocelot-8021q";
};
&mscc_felix_port5 {
dsa-tag-protocol = "ocelot-8021q";
};
&usb0 {
status = "okay";
};
&usb1 {
dr_mode = "host";
status = "okay";
};

2
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
View File

@ -382,9 +382,11 @@
};
&usb0 {
dr_mode = "host";
status = "okay";
};
&usb1 {
dr_mode = "host";
status = "okay";
};

2
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
View File

@ -299,10 +299,10 @@
};
&usb0 {
dr_mode = "host";
status = "okay";
};
&usb1 {
dr_mode = "otg";
status = "okay";
};

2
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View File

@ -599,7 +599,6 @@
compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,dis_rxdet_inp3_quirk;
snps,quirk-frame-length-adjustment = <0x20>;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
@ -610,7 +609,6 @@
compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
reg = <0x0 0x3110000 0x0 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,dis_rxdet_inp3_quirk;
snps,quirk-frame-length-adjustment = <0x20>;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;

6
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View File

@ -335,7 +335,7 @@
<9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0xffffffff 0x0>;
interrupt-map-mask = <0xf 0x0>;
};
};
@ -389,8 +389,8 @@
big-endian;
};
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
ifc: memory-controller@1530000 {
compatible = "fsl,ifc";
reg = <0x0 0x1530000 0x0 0x10000>;
interrupts = <0 43 0x4>;
};

6
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View File

@ -280,8 +280,8 @@
big-endian;
};
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
ifc: memory-controller@1530000 {
compatible = "fsl,ifc";
reg = <0x0 0x1530000 0x0 0x10000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@ -341,7 +341,7 @@
<9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0xffffffff 0x0>;
interrupt-map-mask = <0xf 0x0>;
};
};

6
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
View File

@ -265,7 +265,7 @@
<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0xffffffff 0x0>;
interrupt-map-mask = <0xf 0x0>;
};
};
@ -396,8 +396,8 @@
#interrupt-cells = <2>;
};
ifc: ifc@2240000 {
compatible = "fsl,ifc", "simple-bus";
ifc: memory-controller@2240000 {
compatible = "fsl,ifc";
reg = <0x0 0x2240000 0x0 0x20000>;
interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
little-endian;

10
arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
View File

@ -104,21 +104,21 @@
&dspi {
status = "okay";
dflash0: n25q128a@0 {
dflash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <3000000>;
reg = <0>;
};
dflash1: sst25wf040b@1 {
dflash1: flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <3000000>;
reg = <1>;
};
dflash2: en25s64@2 {
dflash2: flash@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
@ -129,7 +129,7 @@
&qspi {
status = "okay";
flash0: s25fl256s1@0 {
flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
@ -138,7 +138,7 @@
spi-tx-bus-width = <4>;
reg = <0>;
};
flash2: s25fl256s1@2 {
flash2: flash@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";

2
arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
View File

@ -100,7 +100,7 @@
&dspi {
status = "okay";
dflash0: n25q512a@0 {
dflash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";

6
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
View File

@ -305,7 +305,7 @@
<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0xffffffff 0x0>;
interrupt-map-mask = <0xf 0x0>;
};
};
@ -1036,8 +1036,8 @@
QORIQ_CLK_PLL_DIV(4)>;
};
ifc: ifc@2240000 {
compatible = "fsl,ifc", "simple-bus";
ifc: memory-controller@2240000 {
compatible = "fsl,ifc";
reg = <0x0 0x2240000 0x0 0x20000>;
interrupts = <0 21 0x4>; /* Level high type */
little-endian;

6
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View File

@ -698,7 +698,7 @@
<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0xffffffff 0x0>;
interrupt-map-mask = <0xf 0x0>;
};
};
@ -909,7 +909,7 @@
QORIQ_CLK_PLL_DIV(8)>,
<&clockgen QORIQ_CLK_SYSCLK 0>;
clock-names = "ipg", "per";
fsl,clk-source = <0>;
fsl,clk-source = /bits/ 8 <0>;
status = "disabled";
};
@ -921,7 +921,7 @@
QORIQ_CLK_PLL_DIV(8)>,
<&clockgen QORIQ_CLK_SYSCLK 0>;
clock-names = "ipg", "per";
fsl,clk-source = <0>;
fsl,clk-source = /bits/ 8 <0>;
status = "disabled";
};

74
arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi Normal file
View File

@ -0,0 +1,74 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
vpu: vpu@2c000000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x2c000000 0x0 0x2c000000 0x2000000>;
reg = <0 0x2c000000 0 0x1000000>;
power-domains = <&pd IMX_SC_R_VPU>;
status = "disabled";
mu_m0: mailbox@2d000000 {
compatible = "fsl,imx6sx-mu";
reg = <0x2d000000 0x20000>;
interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
power-domains = <&pd IMX_SC_R_VPU_MU_0>;
status = "disabled";
};
mu1_m0: mailbox@2d020000 {
compatible = "fsl,imx6sx-mu";
reg = <0x2d020000 0x20000>;
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
power-domains = <&pd IMX_SC_R_VPU_MU_1>;
status = "disabled";
};
mu2_m0: mailbox@2d040000 {
compatible = "fsl,imx6sx-mu";
reg = <0x2d040000 0x20000>;
interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
power-domains = <&pd IMX_SC_R_VPU_MU_2>;
status = "disabled";
};
vpu_core0: vpu-core@2d080000 {
reg = <0x2d080000 0x10000>;
compatible = "nxp,imx8q-vpu-decoder";
power-domains = <&pd IMX_SC_R_VPU_DEC_0>;
mbox-names = "tx0", "tx1", "rx";
mboxes = <&mu_m0 0 0>,
<&mu_m0 0 1>,
<&mu_m0 1 0>;
status = "disabled";
};
vpu_core1: vpu-core@2d090000 {
reg = <0x2d090000 0x10000>;
compatible = "nxp,imx8q-vpu-encoder";
power-domains = <&pd IMX_SC_R_VPU_ENC_0>;
mbox-names = "tx0", "tx1", "rx";
mboxes = <&mu1_m0 0 0>,
<&mu1_m0 0 1>,
<&mu1_m0 1 0>;
status = "disabled";
};
vpu_core2: vpu-core@2d0a0000 {
reg = <0x2d0a0000 0x10000>;
compatible = "nxp,imx8q-vpu-encoder";
power-domains = <&pd IMX_SC_R_VPU_ENC_1>;
mbox-names = "tx0", "tx1", "rx";
mboxes = <&mu2_m0 0 0>,
<&mu2_m0 0 1>,
<&mu2_m0 1 0>;
status = "disabled";
};
};

3
arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
View File

@ -278,6 +278,7 @@
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MM_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
@ -386,6 +387,8 @@
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40
MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40
MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40
MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40
>;
};

997
arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts Normal file
View File

@ -0,0 +1,997 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Marek Vasut <marex@denx.de>
*/
/dts-v1/;
#include <dt-bindings/net/qca-ar803x.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mm.dtsi"
/ {
model = "Data Modul i.MX8M Mini eDM SBC";
compatible = "dmo,imx8mm-data-modul-edm-sbc", "fsl,imx8mm";
aliases {
rtc0 = &rtc;
rtc1 = &snvs_rtc;
};
chosen {
stdout-path = &uart3;
};
memory@40000000 {
device_type = "memory";
/* There are 1/2/4 GiB options, adjusted by bootloader. */
reg = <0x0 0x40000000 0 0x40000000>;
};
backlight: backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_panel_backlight>;
brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
default-brightness-level = <7>;
enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
pwms = <&pwm1 0 5000000 0>;
/* Disabled by default, unless display board plugged in. */
status = "disabled";
};
clk_xtal25: clk-xtal25 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
panel: panel {
backlight = <&backlight>;
power-supply = <&reg_panel_vcc>;
/* Disabled by default, unless display board plugged in. */
status = "disabled";
};
reg_panel_vcc: regulator-panel-vcc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_panel_vcc_reg>;
regulator-name = "PANEL_VCC";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 6 0>;
enable-active-high;
/* Disabled by default, unless display board plugged in. */
status = "disabled";
};
reg_usdhc2_vcc: regulator-usdhc2-vcc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_vcc_reg>;
regulator-name = "V_3V3_SD";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 0>;
enable-active-high;
};
watchdog-gpio {
/* TPS3813 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_watchdog_gpio>;
compatible = "linux,wdt-gpio";
always-enabled;
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
hw_algo = "level";
/* Reset triggers in 2..3 seconds */
hw_margin_ms = <1500>;
/* Disabled by default */
status = "disabled";
};
};
&A53_0 {
cpu-supply = <&buck2_reg>;
};
&A53_1 {
cpu-supply = <&buck2_reg>;
};
&A53_2 {
cpu-supply = <&buck2_reg>;
};
&A53_3 {
cpu-supply = <&buck2_reg>;
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-hz = /bits/ 64 <750000000>;
};
};
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
flash@0 { /* W25Q128FVSI */
compatible = "jedec,spi-nor";
m25p,fast-read;
spi-max-frequency = <50000000>;
reg = <0>;
};
};
&ecspi2 { /* Feature connector SPI */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
/* Disabled by default, unless feature board plugged in. */
status = "disabled";
};
&ecspi3 { /* Display connector SPI */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
/* Disabled by default, unless display board plugged in. */
status = "disabled";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&fec1_phy>;
phy-supply = <&buck4_reg>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
/* Atheros AR8031 PHY */
fec1_phy: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
/*
* Dedicated ENET_WOL# signal is unused, the PHY
* can wake the SoC up via INT signal as well.
*/
interrupts-extended = <&gpio1 15 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <10000>;
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
qca,keep-pll-enabled;
vddio-supply = <&vddio>;
vddio: vddio-regulator {
regulator-name = "VDDIO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddh: vddh-regulator {
regulator-name = "VDDH";
};
};
};
};
&gpio1 {
gpio-line-names =
"", "ENET_RST#", "WDOG_B#", "PMIC_INT#",
"", "M2-B_PCIE_RST#", "M2-B_PCIE_WAKE#", "RTC_IRQ#",
"WDOG_KICK#", "M2-B_PCIE_CLKREQ#",
"USB1_OTG_ID_3V3", "ENET_WOL#",
"", "", "", "ENET_INT#",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio2 {
gpio-line-names =
"MEMCFG2", "MEMCFG1", "DSI_RESET_1V8#", "DSI_IRQ_1V8#",
"M2-B_FULL_CARD_PWROFF_1V8#", "EEPROM_WP_1V8#",
"PCIE_CLK_GEN_CLKPWRGD_PD_1V8#", "GRAPHICS_PRSNT_1V8#",
"MEMCFG0", "WDOG_EN",
"M2-B_W_DISABLE1_WWAN_1V8#", "M2-B_W_DISABLE2_GPS_1V8#",
"", "", "", "",
"", "", "", "SD2_RESET#", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio3 {
gpio-line-names =
"BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "",
"", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8",
"CSI_PD_1V8", "CSI_RESET_1V8#", "", "",
"", "", "", "",
"", "", "", "M2-B_WAKE_WWAN_1V8#",
"M2-B_RESET_1V8#", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio4 {
gpio-line-names =
"NC0", "NC1", "BOOTCFG0", "BOOTCFG1",
"BOOTCFG2", "BOOTCFG3", "BOOTCFG4", "BOOTCFG5",
"BOOTCFG6", "BOOTCFG7", "NC10", "NC11",
"BOOTCFG8", "BOOTCFG9", "BOOTCFG10", "BOOTCFG11",
"BOOTCFG12", "BOOTCFG13", "BOOTCFG14", "BOOTCFG15",
"NC20", "", "", "",
"", "CAN_INT#", "CAN_RST#", "GPIO4_IO27",
"DIS_USB_DN2", "", "", "";
};
&gpio5 {
gpio-line-names =
"", "DIS_USB_DN1", "USBHUB_RESET#", "GPIO5_IO03",
"GPIO5_IO04", "", "", "",
"", "SPI1_CS#", "", "",
"", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3",
"I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3",
"I2C4_SCL_3V3", "I2C4_SDA_3V3", "", "",
"", "SPI3_CS#", "", "", "", "", "", "";
};
&i2c1 {
/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic: pmic@4b {
compatible = "rohm,bd71847";
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
rohm,reset-snvs-powered;
/*
* i.MX 8M Mini Data Sheet for Consumer Products
* 3.1.3 Operating ranges
* MIMX8MM4DVTLZAA
*/
regulators {
/* VDD_SOC */
buck1_reg: BUCK1 {
regulator-name = "buck1";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
};
/* VDD_ARM */
buck2_reg: BUCK2 {
regulator-name = "buck2";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1050000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <950000>;
};
/* VDD_DRAM, BUCK5 */
buck3_reg: BUCK3 {
regulator-name = "buck3";
/* 1.5 GHz DDR bus clock */
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
};
/* 3V3_VDD, BUCK6 */
buck4_reg: BUCK4 {
regulator-name = "buck4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
/* 1V8_VDD, BUCK7 */
buck5_reg: BUCK5 {
regulator-name = "buck5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
/* 1V1_NVCC_DRAM, BUCK8 */
buck6_reg: BUCK6 {
regulator-name = "buck6";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
/* 1V8_NVCC_SNVS */
ldo1_reg: LDO1 {
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
/* 0V8_VDD_SNVS */
ldo2_reg: LDO2 {
regulator-name = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
/* 1V8_VDDA */
ldo3_reg: LDO3 {
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
/* 0V9_VDD_PHY */
ldo4_reg: LDO4 {
regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
/* 1V2_VDD_PHY */
ldo6_reg: LDO6 {
regulator-name = "ldo6";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c2 {
/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
usb-hub@2c {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_hub>;
compatible = "microchip,usb2514bi";
reg = <0x2c>;
individual-port-switching;
reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
self-powered;
};
eeprom: eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
rtc: rtc@68 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
compatible = "st,m41t62";
reg = <0x68>;
interrupts-extended = <&gpio1 7 IRQ_TYPE_LEVEL_LOW>;
};
pcieclk: clk@6a {
compatible = "renesas,9fgv0241";
reg = <0x6a>;
clocks = <&clk_xtal25>;
#clock-cells = <1>;
};
};
&i2c3 { /* Display connector I2C */
/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
clock-frequency = <320000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c4 { /* Feature connector I2C */
/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
clock-frequency = <320000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>,
<&pinctrl_hog_panel>, <&pinctrl_hog_sbc>,
<&pinctrl_panel_expansion>;
pinctrl_ecspi1: ecspi1-grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x44
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x44
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x44
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
>;
};
pinctrl_ecspi2: ecspi2-grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x44
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x44
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x44
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40
>;
};
pinctrl_ecspi3: ecspi3-grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x44
MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x44
MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x44
MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x40
>;
};
pinctrl_fec1: fec1-grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
/* ENET_RST# */
MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x6
/* ENET_WOL# */
MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000090
/* ENET_INT# */
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000090
>;
};
pinctrl_hog_feature: hog-feature-grp {
fsl,pins = <
/* GPIO4_IO27 */
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000006
/* GPIO5_IO03 */
MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000006
/* GPIO5_IO04 */
MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000006
/* CAN_INT# */
MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000090
/* CAN_RST# */
MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x26
>;
};
pinctrl_hog_panel: hog-panel-grp {
fsl,pins = <
/* GRAPHICS_GPIO0_1V8 */
MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x26
>;
};
pinctrl_hog_misc: hog-misc-grp {
fsl,pins = <
/* PG_V_IN_VAR# */
MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000000
/* CSI_PD_1V8 */
MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x0
/* CSI_RESET_1V8# */
MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x0
/* DIS_USB_DN1 */
MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x0
/* DIS_USB_DN2 */
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x0
/* EEPROM_WP_1V8# */
MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x100
/* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */
MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0
/* GRAPHICS_PRSNT_1V8# */
MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x40000000
/* CLK_CCM_CLKO1_3V3 */
MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x10
>;
};
pinctrl_hog_sbc: hog-sbc-grp {
fsl,pins = <
/* MEMCFG[0..2] straps */
MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000140
MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000140
MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000140
/* BOOT_CFG[0..15] straps */
MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000000
MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000000
MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000000
MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000000
MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000000
MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000000
MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000000
MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x40000000
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000000
MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x40000000
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000000
MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x40000000
MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000000
MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000000
MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000000
MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x40000000
/* Not connected pins */
MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x0
MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x0
MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x0
MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x0
MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x0
>;
};
pinctrl_i2c1: i2c1-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000084
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000084
>;
};
pinctrl_i2c1_gpio: i2c1-gpio-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x84
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x84
>;
};
pinctrl_i2c2: i2c2-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000084
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000084
>;
};
pinctrl_i2c2_gpio: i2c2-gpio-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x84
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x84
>;
};
pinctrl_i2c3: i2c3-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000084
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000084
>;
};
pinctrl_i2c3_gpio: i2c3-gpio-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x84
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x84
>;
};
pinctrl_i2c4: i2c4-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000084
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000084
>;
};
pinctrl_i2c4_gpio: i2c4-gpio-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x84
MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x84
>;
};
pinctrl_panel_backlight: panel-backlight-grp {
fsl,pins = <
/* BL_ENABLE_1V8 */
MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x104
>;
};
pinctrl_panel_expansion: panel-expansion-grp {
fsl,pins = <
/* DSI_RESET_1V8# */
MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x2
/* DSI_IRQ_1V8# */
MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x40000090
>;
};
pinctrl_panel_vcc_reg: panel-vcc-grp {
fsl,pins = <
/* TFT_ENABLE_1V8 */
MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x104
>;
};
pinctrl_panel_pwm: panel-pwm-grp {
fsl,pins = <
/* BL_PWM_3V3 */
MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x12
>;
};
pinctrl_pcie0: pcie-grp {
fsl,pins = <
/* M2-B_RESET_1V8# */
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x102
/* M2-B_PCIE_RST# */
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x2
/* M2-B_FULL_CARD_PWROFF_1V8# */
MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x102
/* M2-B_W_DISABLE1_WWAN_1V8# */
MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x102
/* M2-B_W_DISABLE2_GPS_1V8# */
MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x102
/* CLK_M2_32K768 */
MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x14
/* M2-B_WAKE_WWAN_1V8# */
MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x40000140
/* M2-B_PCIE_WAKE# */
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000140
/* M2-B_PCIE_CLKREQ# */
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000140
>;
};
pinctrl_pmic: pmic-grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000090
>;
};
pinctrl_rtc: rtc-grp {
fsl,pins = <
/* RTC_IRQ# */
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000090
>;
};
pinctrl_sai5: sai5-grp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x100
MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x0
MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x100
MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x100
MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x100
>;
};
pinctrl_uart1: uart1-grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x90
MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x90
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x50
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x50
>;
};
pinctrl_uart2: uart2-grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x50
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x90
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x50
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x90
>;
};
pinctrl_uart3: uart3-grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40
>;
};
pinctrl_uart4: uart4-grp {
fsl,pins = <
MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x40
MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x40
>;
};
pinctrl_usb_hub: usb-hub-grp {
fsl,pins = <
/* USBHUB_RESET# */
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x4
>;
};
pinctrl_usb_otg1: usb-otg1-grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000000
MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x4
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x40000090
>;
};
pinctrl_usdhc2_vcc_reg: usdhc2-vcc-reg-grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x4
>;
};
pinctrl_usdhc2: usdhc2-grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc3: usdhc3-grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
>;
};
pinctrl_watchdog_gpio: watchdog-gpio-grp {
fsl,pins = <
/* WDOG_B# */
MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x26
/* WDOG_EN -- ungate WDT RESET# signal propagation */
MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x6
/* WDOG_KICK# / WDI */
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x26
>;
};
};
&pcie_phy {
fsl,clkreq-unsupported; /* CLKREQ_B is not connected to suitable input */
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,tx-deemph-gen1 = <0x2d>;
fsl,tx-deemph-gen2 = <0xf>;
clocks = <&pcieclk 0>;
status = "okay";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcieclk 0>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_panel_pwm>;
/* Disabled by default, unless display board plugged in. */
status = "disabled";
};
&sai5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai5>;
fsl,sai-mclk-direction-output;
/* Input into codec PLL */
assigned-clocks = <&clk IMX8MM_CLK_SAI5>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>;
assigned-clock-rates = <22579200>;
/* Disabled by default, unless display board plugged in. */
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
status = "disabled";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "disabled";
};
&uart3 { /* A53 Debug */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart4 { /* M4 Debug */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
/* UART4 is reserved for CM and RDC blocks CA access to UART4. */
status = "disabled";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1>;
dr_mode = "otg";
status = "okay";
};
&usbotg2 {
disable-over-current;
dr_mode = "host";
status = "okay";
};
&usdhc2 { /* MicroSD */
assigned-clocks = <&clk IMX8MM_CLK_USDHC2_ROOT>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vcc>;
status = "okay";
};
&usdhc3 { /* eMMC */
assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
vmmc-supply = <&buck4_reg>;
vqmmc-supply = <&buck5_reg>;
status = "okay";
};
&wdog1 {
status = "okay";
};

2
arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi
View File

@ -98,7 +98,7 @@
pinctrl-1 = <&pinctrl_flexspi1>;
status = "okay";
flash0: spi-flash@0 {
flash0: flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;

20
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
View File

@ -59,6 +59,14 @@
enable-active-high;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000 0>;
brightness-levels = <0 255>;
num-interpolated-steps = <255>;
default-brightness-level = <250>;
};
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
@ -395,6 +403,12 @@
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
status = "okay";
};
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
@ -549,4 +563,10 @@
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
>;
};
pinctrl_backlight: backlightgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06
>;
};
};

2
arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts
View File

@ -182,7 +182,7 @@
#address-cells = <1>;
#size-cells = <0>;
usbnet: usbether@1 {
usbnet: ethernet@1 {
compatible = "usb424,ec00";
reg = <1>;
local-mac-address = [ 00 00 00 00 00 00 ];

2
arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
View File

@ -66,7 +66,7 @@
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
spi-flash@0 {
flash@0 {
compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
spi-max-frequency = <80000000>;
reg = <0>;

334
arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts Normal file
View File

@ -0,0 +1,334 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright 2021-2022 Marek Vasut <marex@denx.de>
*/
/dts-v1/;
#include "imx8mm-verdin.dtsi"
/ {
model = "MENLO MX8MM EMBEDDED DEVICE";
compatible = "menlo,mx8menlo",
"toradex,verdin-imx8mm",
"fsl,imx8mm";
/delete-node/ gpio-keys;
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
user1 {
label = "TestLed601";
gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
};
user2 {
label = "TestLed602";
gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
beeper {
compatible = "gpio-beeper";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_beeper>;
gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
};
/* Fixed clock dedicated to SPI CAN on carrier board */
clk_xtal20: clk-xtal20 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <20000000>;
};
};
&ecspi1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
/* CAN controller on the baseboard */
canfd: can@0 {
compatible = "microchip,mcp2518fd";
clocks = <&clk_xtal20>;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
reg = <0>;
spi-max-frequency = <2000000>;
};
};
&ecspi2 {
pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio3 4 GPIO_ACTIVE_LOW>;
status = "okay";
spidev@0 {
compatible = "menlo,m53cpld";
reg = <0>;
spi-max-frequency = <25000000>;
};
spidev@1 {
compatible = "menlo,m53cpld";
reg = <1>;
spi-max-frequency = <25000000>;
};
};
&ethphy0 {
max-speed = <100>;
};
&fec1 {
status = "okay";
};
&flexspi {
status = "okay";
flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <66000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
};
&gpio1 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
&gpio2 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
&gpio3 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "DISP_reset", "KBD_intI",
"", "", "", "",
"", "", "", "";
};
&gpio4 {
/*
* CPLD_D[n] is ARM_CPLD[n] in schematic
* CPLD_int is SA_INTERRUPT in schematic
* CPLD_reset is RESET_SOFT in schematic
*/
gpio-line-names =
"CPLD_D[1]", "CPLD_int", "CPLD_reset", "",
"", "CPLD_D[0]", "", "",
"", "", "", "CPLD_D[2]",
"CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", "CPLD_D[6]",
"CPLD_D[7]", "", "", "",
"", "", "", "",
"", "", "", "KBD_intK",
"", "", "", "";
};
&gpio5 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
&gpio_expander_21 {
status = "okay";
};
&hwmon {
status = "okay";
};
&i2c3 {
status = "okay";
};
&i2c4 {
/* None of this is present on the SoM. */
/delete-node/ bridge@2c;
/delete-node/ hdmi@48;
/delete-node/ touch@4a;
/delete-node/ sensor@4f;
/delete-node/ eeprom@50;
/delete-node/ eeprom@57;
};
&iomuxc {
pinctrl-0 = <&pinctrl_gpio7>, <&pinctrl_gpio_hog1>,
<&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>;
pinctrl_beeper: beepergrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1c4
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x4
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x4
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1c4
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x1c4
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4
MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4
>;
};
pinctrl_uart4_rts: uart4rtsgrp {
fsl,pins = <
/* SODIMM 222 */
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184
>;
};
};
&pinctrl_gpio1 {
fsl,pins = <
/* SODIMM 206 */
MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x1c4
>;
};
&pinctrl_gpio_hog1 {
fsl,pins = <
/* SODIMM 88 */
MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4
/* CPLD_int */
MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4
/* CPLD_reset */
MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4
/* SODIMM 94 */
MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4
/* SODIMM 96 */
MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4
/* CPLD_D[7] */
MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4
/* CPLD_D[6] */
MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4
/* CPLD_D[5] */
MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4
/* CPLD_D[4] */
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4
/* CPLD_D[3] */
MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4
/* CPLD_D[2] */
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4
/* CPLD_D[1] */
MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4
/* CPLD_D[0] */
MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4
/* KBD_intK */
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1c4
/* DISP_reset */
MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x1c4
/* KBD_intI */
MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x1c4
/* SODIMM 46 */
MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x1c4
>;
};
&pinctrl_uart1 {
fsl,pins = <
/* SODIMM 149 */
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4
/* SODIMM 147 */
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4
/* SODIMM 210 */
MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x1c4
/* SODIMM 212 */
MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x1c4
>;
};
&reg_usb_otg1_vbus {
/delete-property/ enable-active-high;
gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
};
&reg_usb_otg2_vbus {
/delete-property/ enable-active-high;
gpio = <&gpio1 14 GPIO_ACTIVE_LOW>;
};
&sai2 {
status = "disabled";
};
&uart1 {
uart-has-rtscts;
status = "okay";
};
&uart2 {
status = "okay";
};
&uart4 {
pinctrl-0 = <&pinctrl_uart4 &pinctrl_uart4_rts>;
linux,rs485-enabled-at-boot-time;
rts-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&usbotg1 {
dr_mode = "peripheral";
status = "okay";
};
&usbotg2 {
dr_mode = "host";
status = "okay";
};
&usdhc2 {
status = "okay";
};

1
arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
View File

@ -112,6 +112,7 @@
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,clkreq-unsupported;
clocks = <&pcie0_refclk>;
clock-names = "ref";
status = "okay";
};

1
arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
View File

@ -134,6 +134,7 @@
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,clkreq-unsupported;
clocks = <&pcie0_refclk>;
clock-names = "ref";
status = "okay";
};

2
arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
View File

@ -154,6 +154,7 @@
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,clkreq-unsupported;
clocks = <&pcie0_refclk>;
clock-names = "ref";
status = "okay";
};
@ -221,6 +222,7 @@
pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>;
cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
bluetooth {

16
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
View File

@ -678,6 +678,7 @@
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,clkreq-unsupported;
clocks = <&pcie0_refclk>;
clock-names = "ref";
status = "okay";
};
@ -716,6 +717,7 @@
dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
};
@ -731,6 +733,7 @@
pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
};
@ -739,6 +742,7 @@
pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>;
cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
};
@ -1087,15 +1091,3 @@
>;
};
};
&cpu_alert0 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
&cpu_crit0 {
temperature = <105000>;
hysteresis = <2000>;
type = "critical";
};

17
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
View File

@ -394,6 +394,13 @@
gw,voltage-divider-ohms = <10000 10000>;
};
channel@9c {
gw,mode = <2>;
reg = <0x9c>;
label = "vdd_5p0";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@a2 {
gw,mode = <2>;
reg = <0xa2>;
@ -595,7 +602,8 @@
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,clkreq-unsupported;
clocks = <&clk IMX8MM_CLK_DUMMY>;
clocks = <&pcie0_refclk>;
clock-names = "ref";
status = "okay";
};
@ -604,8 +612,8 @@
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_DUMMY>, <&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
@ -644,6 +652,7 @@
pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
cts-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
};
@ -660,6 +669,7 @@
pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
bluetooth {
@ -677,6 +687,7 @@
dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
};

1
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
View File

@ -540,6 +540,7 @@
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,clkreq-unsupported;
clocks = <&pcie0_refclk>;
clock-names = "ref";
status = "okay";
};

2
arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi
View File

@ -114,7 +114,7 @@
status = "okay";
};
/* VERDIN I2S_1 */
/* Verdin I2S_1 */
&sai2 {
status = "okay";
};

26
arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi
View File

@ -17,19 +17,6 @@
};
};
/* On-module Wi-Fi */
&usdhc3 {
bus-width = <4>;
keep-power-in-suspend;
non-removable;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>;
vmmc-supply = <&reg_wifi_en>;
status = "okay";
};
&gpio3 {
gpio-line-names = "SODIMM_52",
"SODIMM_54",
@ -92,3 +79,16 @@
"SODIMM_135",
"SODIMM_129";
};
/* On-module Wi-Fi */
&usdhc3 {
bus-width = <4>;
keep-power-in-suspend;
non-removable;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>;
vmmc-supply = <&reg_wifi_en>;
status = "okay";
};

411
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
View File

@ -86,7 +86,7 @@
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "+V3.3_ETH";
regulator-name = "On-module +V3.3_ETH";
startup-delay-us = <200000>;
};
@ -99,7 +99,7 @@
pinctrl-0 = <&pinctrl_reg_usb1_en>;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "usb_otg1_vbus";
regulator-name = "USB_1_EN";
};
reg_usb_otg2_vbus: regulator-usb-otg2 {
@ -111,7 +111,7 @@
pinctrl-0 = <&pinctrl_reg_usb2_en>;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "usb_otg2_vbus";
regulator-name = "USB_2_EN";
};
reg_usdhc2_vmmc: regulator-usdhc2 {
@ -306,7 +306,7 @@
"SODIMM_151",
"SODIMM_153";
ctrl_sleep_moci-hog {
ctrl-sleep-moci-hog {
gpio-hog;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpios = <1 GPIO_ACTIVE_HIGH>;
@ -337,6 +337,11 @@
reg = <0x25>;
sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
/*
* The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC
* behind this PMIC.
*/
regulators {
reg_vdd_soc: BUCK1 {
nxp,dvs-run-voltage = <850000>;
@ -345,7 +350,7 @@
regulator-boot-on;
regulator-max-microvolt = <850000>;
regulator-min-microvolt = <800000>;
regulator-name = "+VDD_SOC";
regulator-name = "On-module +VDD_SOC (BUCK1)";
regulator-ramp-delay = <3125>;
};
@ -356,7 +361,7 @@
regulator-boot-on;
regulator-max-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-name = "+VDD_ARM";
regulator-name = "On-module +VDD_ARM (BUCK2)";
regulator-ramp-delay = <3125>;
};
@ -365,7 +370,7 @@
regulator-boot-on;
regulator-max-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-name = "+VDD_GPU_VPU_DDR";
regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)";
};
reg_vdd_3v3: BUCK4 {
@ -373,7 +378,7 @@
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "+V3.3";
regulator-name = "On-module +V3.3 (BUCK4)";
};
reg_vdd_1v8: BUCK5 {
@ -381,7 +386,7 @@
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "PWR_1V8_MOCI";
regulator-name = "PWR_1V8_MOCI (BUCK5)";
};
reg_nvcc_dram: BUCK6 {
@ -389,7 +394,7 @@
regulator-boot-on;
regulator-max-microvolt = <1100000>;
regulator-min-microvolt = <1100000>;
regulator-name = "+VDD_DDR";
regulator-name = "On-module +VDD_DDR (BUCK6)";
};
reg_nvcc_snvs: LDO1 {
@ -397,7 +402,7 @@
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "+V1.8_SNVS";
regulator-name = "On-module +V1.8_SNVS (LDO1)";
};
reg_vdd_snvs: LDO2 {
@ -405,7 +410,7 @@
regulator-boot-on;
regulator-max-microvolt = <900000>;
regulator-min-microvolt = <800000>;
regulator-name = "+V0.8_SNVS";
regulator-name = "On-module +V0.8_SNVS (LDO2)";
};
reg_vdda: LDO3 {
@ -413,7 +418,7 @@
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "+V1.8A";
regulator-name = "On-module +V1.8A (LDO3)";
};
reg_vdd_phy: LDO4 {
@ -421,13 +426,13 @@
regulator-boot-on;
regulator-max-microvolt = <900000>;
regulator-min-microvolt = <900000>;
regulator-name = "+V0.9_MIPI";
regulator-name = "On-module +V0.9_MIPI (LDO4)";
};
reg_nvcc_sd: LDO5 {
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
regulator-name = "+V3.3_1.8_SD";
regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
};
};
};
@ -580,8 +585,10 @@
atmel_mxt_ts: touch@4a {
compatible = "atmel,maxtouch";
/* Verdin GPIO_9_DSI */
/* (TOUCH_INT#, SODIMM 17, also routed to SN65dsi83 IRQ albeit currently unused) */
/*
* Verdin GPIO_9_DSI
* (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused)
*/
interrupt-parent = <&gpio3>;
interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
@ -661,7 +668,7 @@
#pwm-cells = <3>;
};
/* VERDIN I2S_1 */
/* Verdin I2S_1 */
&sai2 {
#sound-dai-cells = <0>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
@ -695,8 +702,8 @@
uart-has-rtscts;
};
/* Verdin UART_4 */
/*
* Verdin UART_4
* Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS
*/
&uart4 {
@ -750,10 +757,11 @@
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
vmmc-supply = <&reg_usdhc2_vmmc>;
};
@ -774,235 +782,235 @@
pinctrl_can1_int: can1intgrp {
fsl,pins =
<MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x1c4>; /* CAN_1_SPI_INT#_1.8V */
<MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */
};
pinctrl_can2_int: can2intgrp {
fsl,pins =
<MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x1c4>; /* CAN_2_SPI_INT#_1.8V */
<MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */
};
pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
fsl,pins =
<MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1c4>; /* SODIMM 256 */
<MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins =
<MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x4>, /* SODIMM 196 */
<MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x4>, /* SODIMM 200 */
<MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x1c4>, /* SODIMM 198 */
<MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x1c4>; /* SODIMM 202 */
<MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */
<MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */
<MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */
<MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins =
<MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x4>, /* CAN_SPI_SCK_1.8V */
<MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x4>, /* CAN_SPI_MOSI_1.8V */
<MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x1c4>, /* CAN_SPI_MISO_1.8V */
<MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x1c4>, /* CAN_1_SPI_CS_1.8V# */
<MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c4>; /* CAN_2_SPI_CS#_1.8V */
<MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */
<MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */
<MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */
<MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */
<MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */
};
pinctrl_fec1: fec1grp {
fsl,pins =
<MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
<MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
<MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>,
<MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>,
<MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>,
<MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>,
<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
<MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
<MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>,
<MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
<MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>,
<MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>,
<MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>,
<MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>,
<MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>,
<MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>,
<MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c4>;
<MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>;
};
pinctrl_fec1_sleep: fec1-sleepgrp {
fsl,pins =
<MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
<MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
<MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>,
<MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>,
<MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>,
<MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>,
<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
<MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
<MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>,
<MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
<MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>,
<MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>,
<MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>,
<MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>,
<MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>,
<MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>,
<MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x184>;
<MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins =
<MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2>, /* SODIMM 52 */
<MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82>, /* SODIMM 54 */
<MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82>, /* SODIMM 64 */
<MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82>, /* SODIMM 66 */
<MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82>, /* SODIMM 56 */
<MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82>, /* SODIMM 58 */
<MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82>, /* SODIMM 60 */
<MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82>; /* SODIMM 62 */
<MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */
<MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */
<MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */
<MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */
<MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */
<MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */
<MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */
<MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */
};
pinctrl_gpio1: gpio1grp {
fsl,pins =
<MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x184>; /* SODIMM 206 */
<MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */
};
pinctrl_gpio2: gpio2grp {
fsl,pins =
<MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1c4>; /* SODIMM 208 */
<MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */
};
pinctrl_gpio3: gpio3grp {
fsl,pins =
<MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x184>; /* SODIMM 210 */
<MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */
};
pinctrl_gpio4: gpio4grp {
fsl,pins =
<MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x184>; /* SODIMM 212 */
<MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */
};
pinctrl_gpio5: gpio5grp {
fsl,pins =
<MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x184>; /* SODIMM 216 */
<MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */
};
pinctrl_gpio6: gpio6grp {
fsl,pins =
<MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x184>; /* SODIMM 218 */
<MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */
};
pinctrl_gpio7: gpio7grp {
fsl,pins =
<MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x184>; /* SODIMM 220 */
<MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */
};
pinctrl_gpio8: gpio8grp {
fsl,pins =
<MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184>; /* SODIMM 222 */
<MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */
};
/* Verdin GPIO_9_DSI (pulled-up as active-low) */
pinctrl_gpio_9_dsi: gpio9dsigrp {
fsl,pins =
<MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x1c4>; /* SODIMM 17 */
<MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x146>; /* SODIMM 17 */
};
/* Verdin GPIO_10_DSI */
/* Verdin GPIO_10_DSI (pulled-up as active-low) */
pinctrl_gpio_10_dsi: gpio10dsigrp {
fsl,pins =
<MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x1c4>; /* SODIMM 21 */
<MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */
};
pinctrl_gpio_hog1: gpiohog1grp {
fsl,pins =
<MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4>, /* SODIMM 88 */
<MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4>, /* SODIMM 90 */
<MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4>, /* SODIMM 92 */
<MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4>, /* SODIMM 94 */
<MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4>, /* SODIMM 96 */
<MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4>, /* SODIMM 100 */
<MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4>, /* SODIMM 102 */
<MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4>, /* SODIMM 104 */
<MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4>, /* SODIMM 106 */
<MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4>, /* SODIMM 108 */
<MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4>, /* SODIMM 112 */
<MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4>, /* SODIMM 114 */
<MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4>, /* SODIMM 116 */
<MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4>, /* SODIMM 118 */
<MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4>; /* SODIMM 120 */
<MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */
<MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */
<MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */
<MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */
<MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */
<MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */
<MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */
<MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */
<MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */
<MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */
<MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */
<MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */
<MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */
<MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */
<MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */
};
pinctrl_gpio_hog2: gpiohog2grp {
fsl,pins =
<MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1c4>; /* SODIMM 91 */
<MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */
};
pinctrl_gpio_hog3: gpiohog3grp {
fsl,pins =
<MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x1c4>, /* SODIMM 157 */
<MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4>; /* SODIMM 187 */
<MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */
<MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins =
<MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1c4>; /* SODIMM 252 */
<MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */
};
/* On-module I2C */
pinctrl_i2c1: i2c1grp {
fsl,pins =
<MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c6>, /* PMIC_I2C_SCL */
<MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c6>; /* PMIC_I2C_SDA */
<MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */
<MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins =
<MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c6>, /* PMIC_I2C_SCL */
<MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c6>; /* PMIC_I2C_SDA */
<MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */
<MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */
};
/* Verdin I2C_4_CSI */
pinctrl_i2c2: i2c2grp {
fsl,pins =
<MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c6>, /* SODIMM 55 */
<MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c6>; /* SODIMM 53 */
<MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */
<MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins =
<MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c6>, /* SODIMM 55 */
<MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c6>; /* SODIMM 53 */
<MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */
<MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */
};
/* Verdin I2C_2_DSI */
pinctrl_i2c3: i2c3grp {
fsl,pins =
<MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c6>, /* SODIMM 95 */
<MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c6>; /* SODIMM 93 */
<MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */
<MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins =
<MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c6>, /* SODIMM 95 */
<MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c6>; /* SODIMM 93 */
<MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */
<MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */
};
/* Verdin I2C_1 */
pinctrl_i2c4: i2c4grp {
fsl,pins =
<MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c6>, /* SODIMM 14 */
<MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c6>; /* SODIMM 12 */
<MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */
<MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins =
<MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c6>, /* SODIMM 14 */
<MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c6>; /* SODIMM 12 */
<MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */
<MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */
};
/* Verdin I2S_2_BCLK (TOUCH_RESET#) */
pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
fsl,pins =
<MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x184>; /* SODIMM 42 */
<MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */
};
/* Verdin I2S_2_D_OUT shared with SAI5 */
pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
fsl,pins =
<MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x184>; /* SODIMM 46 */
<MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */
};
pinctrl_pcie0: pcie0grp {
@ -1014,7 +1022,7 @@
pinctrl_pmic: pmicirqgrp {
fsl,pins =
<MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41>; /* PMIC_INT# */
<MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */
};
/* Verdin PWM_3_DSI shared with GPIO1_IO1 */
@ -1036,82 +1044,82 @@
/* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */
pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp {
fsl,pins =
<MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x184>; /* SODIMM 19 */
<MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */
};
pinctrl_reg_eth: regethgrp {
fsl,pins =
<MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x184>; /* PMIC_EN_ETH */
<MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */
};
pinctrl_reg_usb1_en: regusb1engrp {
fsl,pins =
<MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x184>; /* SODIMM 155 */
<MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */
};
pinctrl_reg_usb2_en: regusb2engrp {
fsl,pins =
<MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x184>; /* SODIMM 185 */
<MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */
};
pinctrl_sai2: sai2grp {
fsl,pins =
<MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6>, /* SODIMM 32 */
<MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6>, /* SODIMM 30 */
<MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6>, /* SODIMM 38 */
<MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6>, /* SODIMM 36 */
<MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6>; /* SODIMM 34 */
<MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */
<MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */
<MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */
<MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */
<MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */
};
pinctrl_sai5: sai5grp {
fsl,pins =
<MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6>, /* SODIMM 48 */
<MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6>, /* SODIMM 44 */
<MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6>, /* SODIMM 42 */
<MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6>; /* SODIMM 46 */
<MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */
<MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */
<MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */
<MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */
};
/* control signal for optional ATTPM20P or SE050 */
pinctrl_pmic_tpm_ena: pmictpmenagrp {
fsl,pins =
<MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1c4>; /* PMIC_TPM_ENA */
<MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */
};
pinctrl_tsp: tspgrp {
fsl,pins =
<MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140>, /* SODIMM 148 */
<MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140>, /* SODIMM 152 */
<MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x140>, /* SODIMM 154 */
<MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140>, /* SODIMM 174 */
<MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140>; /* SODIMM 150 */
<MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */
<MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */
<MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */
<MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */
<MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */
};
pinctrl_uart1: uart1grp {
fsl,pins =
<MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4>, /* SODIMM 149 */
<MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4>; /* SODIMM 147 */
<MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */
<MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */
};
pinctrl_uart2: uart2grp {
fsl,pins =
<MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1c4>, /* SODIMM 129 */
<MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1c4>, /* SODIMM 131 */
<MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1c4>, /* SODIMM 133 */
<MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1c4>; /* SODIMM 135 */
<MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */
<MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */
<MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */
<MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */
};
pinctrl_uart3: uart3grp {
fsl,pins =
<MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1c4>, /* SODIMM 137 */
<MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1c4>, /* SODIMM 139 */
<MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1c4>, /* SODIMM 141 */
<MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x1c4>; /* SODIMM 143 */
<MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */
<MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */
<MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */
<MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */
};
pinctrl_uart4: uart4grp {
fsl,pins =
<MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x1c4>, /* SODIMM 151 */
<MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x1c4>; /* SODIMM 153 */
<MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */
<MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */
};
pinctrl_usdhc1: usdhc1grp {
@ -1164,101 +1172,124 @@
pinctrl_usdhc2_cd: usdhc2cdgrp {
fsl,pins =
<MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4>; /* SODIMM 84 */
<MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */
};
pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
fsl,pins =
<MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */
};
pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
fsl,pins =
<MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x184>; /* SODIMM 76 */
<MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */
};
/*
* Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the
* on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here.
*/
pinctrl_usdhc2: usdhc2grp {
fsl,pins =
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190>, /* SODIMM 78 */
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0>, /* SODIMM 74 */
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0>, /* SODIMM 80 */
<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0>, /* SODIMM 82 */
<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0>, /* SODIMM 70 */
<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0>, /* SODIMM 72 */
<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0>;
<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */
<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */
<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */
<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins =
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194>,
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4>,
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>,
<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>,
<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>,
<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>,
<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0>;
<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>,
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>,
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>,
<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>,
<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>,
<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins =
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196>,
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6>,
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6>,
<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6>,
<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6>,
<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6>,
<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0>;
<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>,
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>,
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>,
<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>,
<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>,
<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>;
};
/* On-module Wi-Fi/BT or type specific SDHC interface */
/* (e.g. on X52 extension slot of Verdin Development Board) */
/* Avoid backfeeding with removed card power */
pinctrl_usdhc2_sleep: usdhc2slpgrp {
fsl,pins =
<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>,
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>,
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>,
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>,
<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>,
<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>,
<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>;
};
/*
* On-module Wi-Fi/BT or type specific SDHC interface
* (e.g. on X52 extension slot of Verdin Development Board)
*/
pinctrl_usdhc3: usdhc3grp {
fsl,pins =
<MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190>,
<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0>,
<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0>,
<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0>,
<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0>,
<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0>;
<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>,
<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>,
<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>,
<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>,
<MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>,
<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins =
<MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194>,
<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4>,
<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>;
<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>,
<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>,
<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>,
<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>,
<MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>,
<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins =
<MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196>,
<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6>,
<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6>,
<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6>,
<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6>,
<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6>;
<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>,
<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>,
<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>,
<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>,
<MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>,
<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>;
};
pinctrl_wdog: wdoggrp {
fsl,pins =
<MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6>; /* PMIC_WDI */
<MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */
};
pinctrl_wifi_ctrl: wifictrlgrp {
fsl,pins =
<MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x1c4>, /* WIFI_WKUP_BT */
<MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x1c4>, /* WIFI_W_WKUP_HOST */
<MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1c4>; /* WIFI_WKUP_WLAN */
<MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */
<MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */
<MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */
};
pinctrl_wifi_i2s: bti2sgrp {
fsl,pins =
<MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0xd6>, /* WIFI_TX_BCLK */
<MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0xd6>, /* WIFI_TX_DATA0 */
<MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0xd6>, /* WIFI_TX_SYNC */
<MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0xd6>; /* WIFI_RX_DATA0 */
<MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */
<MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */
<MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */
<MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */
};
pinctrl_wifi_pwr_en: wifipwrengrp {
fsl,pins =
<MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x184>; /* PMIC_EN_WIFI */
<MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */
};
};

8
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@ -758,7 +758,7 @@
clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
<&clk IMX8MM_CLK_PWM1_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -769,7 +769,7 @@
clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
<&clk IMX8MM_CLK_PWM2_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -780,7 +780,7 @@
clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
<&clk IMX8MM_CLK_PWM3_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -791,7 +791,7 @@
clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
<&clk IMX8MM_CLK_PWM4_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};

3
arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi
View File

@ -175,6 +175,7 @@
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MN_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
@ -258,6 +259,8 @@
fsl,pins = <
MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40
MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40
MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40
MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40
>;
};

90
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts
View File

@ -7,6 +7,7 @@
/dts-v1/;
#include "imx8mn-bsh-smm-s2-common.dtsi"
#include <dt-bindings/sound/tlv320aic31xx.h>
/ {
model = "BSH SMM S2 PRO";
@ -16,6 +17,65 @@
device_type = "memory";
reg = <0x0 0x40000000 0x0 0x20000000>;
};
sound-tlv320aic31xx {
compatible = "fsl,imx-audio-tlv320aic31xx";
model = "tlv320aic31xx-hifi";
audio-cpu = <&sai3>;
audio-codec = <&tlv320dac3101>;
audio-asrc = <&easrc>;
audio-routing =
"Ext Spk", "SPL",
"Ext Spk", "SPR";
mclk-id = <PLL_CLKIN_BCLK>;
};
vdd_input: vdd_input {
compatible = "regulator-fixed";
regulator-name = "vdd_input";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
&easrc {
fsl,asrc-rate = <48000>;
fsl,asrc-format = <10>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
tlv320dac3101: audio-codec@18 {
compatible = "ti,tlv320dac3101";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dac_rst>;
reg = <0x18>;
#sound-dai-cells = <0>;
HPVDD-supply = <&buck4_reg>;
SPRVDD-supply = <&vdd_input>;
SPLVDD-supply = <&vdd_input>;
AVDD-supply = <&buck4_reg>;
IOVDD-supply = <&buck4_reg>;
DVDD-supply = <&buck5_reg>;
reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
ai31xx-micbias-vg = <MICBIAS_AVDDV>;
clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
};
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
/* eMMC */
@ -30,6 +90,36 @@
};
&iomuxc {
pinctrl_dac_rst: dacrstgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 /* DAC_RST */
>;
};
pinctrl_espi2: espi2grp {
fsl,pins = <
MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082
MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082
MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082
MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400000c3
MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000c3
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000090

114
arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts Normal file
View File

@ -0,0 +1,114 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "imx8mn.dtsi"
#include "imx8mn-evk.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "NXP i.MX8MNano DDR3L EVK board";
compatible = "fsl,imx8mn-ddr3l-evk", "fsl,imx8mn";
};
&A53_0 {
cpu-supply = <&buck1>;
};
&A53_1 {
cpu-supply = <&buck1>;
};
&A53_2 {
cpu-supply = <&buck1>;
};
&A53_3 {
cpu-supply = <&buck1>;
};
&i2c1 {
pmic: pmic@25 {
compatible = "nxp,pca9450b";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
regulators {
buck1: BUCK1 {
regulator-name = "VDD_SOC_0V9";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck4: BUCK4 {
regulator-name = "VDD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5 {
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "NVCC_DRAM_1V35";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "NVCC_SNVS_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: LDO2 {
regulator-name = "VDD_SNVS_0V8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "VDDA_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "VDD_PHY_1V2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "NVCC_SD2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};

54
arch/arm64/boot/dts/freescale/imx8mn-evk.dts
View File

@ -41,18 +41,18 @@
regulators {
buck1: BUCK1{
regulator-name = "BUCK1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-name = "VDD_SOC";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-name = "VDD_ARM_0V9";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
@ -61,63 +61,63 @@
};
buck4: BUCK4{
regulator-name = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-name = "VDD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5{
regulator-name = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-name = "NVCC_DRAM_1V1";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-name = "NVCC_SNVS_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: LDO2 {
regulator-name = "LDO2";
regulator-name = "VDD_SNVS_0V8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "VDDA_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "VDD_PHY_1V2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-name = "NVCC_SD2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;

45
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
View File

@ -110,6 +110,22 @@
};
};
&flexspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <166000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
@ -196,6 +212,15 @@
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MN_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
@ -267,6 +292,17 @@
>;
};
pinctrl_flexspi: flexspigrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
@ -347,6 +383,15 @@
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4

8
arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts
View File

@ -393,6 +393,13 @@
gw,voltage-divider-ohms = <10000 10000>;
};
channel@9c {
gw,mode = <2>;
reg = <0x9c>;
label = "vdd_5p0";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@a2 {
gw,mode = <2>;
reg = <0xa2>;
@ -625,6 +632,7 @@
pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
bluetooth {

14
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@ -705,7 +705,7 @@
clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
<&clk IMX8MN_CLK_PWM1_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -716,7 +716,7 @@
clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
<&clk IMX8MN_CLK_PWM2_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -727,7 +727,7 @@
clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
<&clk IMX8MN_CLK_PWM3_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -738,7 +738,7 @@
clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
<&clk IMX8MN_CLK_PWM4_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -933,7 +933,7 @@
};
usdhc1: mmc@30b40000 {
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
@ -947,7 +947,7 @@
};
usdhc2: mmc@30b50000 {
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
@ -961,7 +961,7 @@
};
usdhc3: mmc@30b60000 {
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b60000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_IPG_ROOT>,

175
arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts Normal file
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@ -0,0 +1,175 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 NXP
* Copyright (c) 2019 Engicam srl
* Copyright (c) 2020 Amarula Solutons(India)
*/
/dts-v1/;
#include "imx8mp.dtsi"
#include "imx8mp-icore-mx8mp.dtsi"
#include <dt-bindings/usb/pd.h>
/ {
model = "Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit";
compatible = "engicam,icore-mx8mp-edimm2.2", "engicam,icore-mx8mp",
"fsl,imx8mp";
chosen {
stdout-path = &uart2;
};
reg_usb1_vbus: regulator-usb1 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb1>;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "usb1_host_vbus";
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VSD_3V3";
};
};
/* Ethernet */
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-handle = <&ethphy0>;
phy-mode = "rgmii-id";
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c22";
micrel,led-mode = <0>;
reg = <7>;
};
};
};
/* console */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "host";
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
/* SDCARD */
&usdhc2 {
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
pinctrl-names = "default" ;
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x19
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x140
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
>;
};
pinctrl_reg_usb1: regusb1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
>;
};
};

186
arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi Normal file
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@ -0,0 +1,186 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 NXP
* Copyright (c) 2019 Engicam srl
* Copyright (c) 2020 Amarula Solutons(India)
*/
/ {
compatible = "engicam,icore-mx8mp", "fsl,imx8mp";
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pca9450: pmic@25 {
compatible = "nxp,pca9450c";
interrupt-parent = <&gpio3>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
reg = <0x25>;
regulators {
buck1: BUCK1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <1000000>;
regulator-name = "BUCK1";
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1025000>;
regulator-min-microvolt = <720000>;
regulator-name = "BUCK2";
regulator-ramp-delay = <3125>;
};
buck4: BUCK4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3600000>;
regulator-min-microvolt = <3000000>;
regulator-name = "BUCK4";
};
buck5: BUCK5 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1950000>;
regulator-min-microvolt = <1650000>;
regulator-name = "BUCK5";
};
buck6: BUCK6 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1155000>;
regulator-min-microvolt = <1045000>;
regulator-name = "BUCK6";
};
ldo1: LDO1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1950000>;
regulator-min-microvolt = <1650000>;
regulator-name = "LDO1";
};
ldo3: LDO3 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1890000>;
regulator-min-microvolt = <1710000>;
regulator-name = "LDO3";
};
ldo5: LDO5 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
regulator-name = "LDO5";
};
};
};
};
/* EMMC */
&usdhc3 {
bus-width = <8>;
non-removable;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
status = "okay";
};
&iomuxc {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x41
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
};

896
arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts Normal file
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@ -0,0 +1,896 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 Gateworks Corporation
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include "imx8mp.dtsi"
/ {
model = "Gateworks Venice GW74xx i.MX8MP board";
compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";
aliases {
ethernet0 = &eqos;
ethernet1 = &fec;
ethernet2 = &lan1;
ethernet3 = &lan2;
ethernet4 = &lan3;
ethernet5 = &lan4;
ethernet6 = &lan5;
};
chosen {
stdout-path = &uart2;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
gpio-keys {
compatible = "gpio-keys";
key-0 {
label = "user_pb";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
key-1 {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-2 {
label = "key_erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
key-3 {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
key-4 {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
key-5 {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
led-controller {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-0 {
function = LED_FUNCTION_HEARTBEAT;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
};
reg_usb2_vbus: regulator-usb2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb2>;
compatible = "regulator-fixed";
regulator-name = "usb_usb2_vbus";
gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_can2_stby: regulator-can2-stby {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_can>;
regulator-name = "can2_stby";
gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_wifi_en: regulator-wifi-en {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_wifi>;
compatible = "regulator-fixed";
regulator-name = "wl";
gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>;
startup-delay-us = <100>;
enable-active-high;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
/* off-board header */
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii-id";
local-mac-address = [00 00 00 00 00 00];
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_can2_stby>;
status = "okay";
};
&gpio1 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"", "", "dio0", "", "dio1", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio2 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"pcie3_wdis#", "", "", "pcie1_wdis@", "pcie2_wdis#", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio3 {
gpio-line-names =
"m2_gdis#", "", "", "", "", "", "", "m2_rst#",
"", "", "", "", "", "", "", "",
"m2_off#", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio4 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "m2_wdis#", "", "", "",
"", "", "", "", "", "", "", "uart_rs485";
};
&gpio5 {
gpio-line-names =
"uart_half", "uart_term", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
pinctrl-0 = <&pinctrl_gsc>;
interrupt-parent = <&gpio4>;
interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <1>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@6 {
gw,mode = <0>;
reg = <0x06>;
label = "temp";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@82 {
gw,mode = <2>;
reg = <0x82>;
label = "vdd_adc1";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@84 {
gw,mode = <2>;
reg = <0x84>;
label = "vdd_adc2";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@86 {
gw,mode = <2>;
reg = <0x86>;
label = "vdd_vin";
gw,voltage-divider-ohms = <22100 1000>;
};
channel@88 {
gw,mode = <2>;
reg = <0x88>;
label = "vdd_3p3";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@8c {
gw,mode = <2>;
reg = <0x8c>;
label = "vdd_2p5";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@90 {
gw,mode = <2>;
reg = <0x90>;
label = "vdd_soc";
};
channel@92 {
gw,mode = <2>;
reg = <0x92>;
label = "vdd_arm";
};
channel@98 {
gw,mode = <2>;
reg = <0x98>;
label = "vdd_1p8";
};
channel@9a {
gw,mode = <2>;
reg = <0x9a>;
label = "vdd_1p2";
};
channel@9c {
gw,mode = <2>;
reg = <0x9c>;
label = "vdd_dram";
};
channel@a2 {
gw,mode = <2>;
reg = <0xa2>;
label = "vdd_gsc";
gw,voltage-divider-ohms = <10000 10000>;
};
};
};
gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio3>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
regulators {
BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <1025000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3600000>;
regulator-boot-on;
regulator-always-on;
};
BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <1950000>;
regulator-boot-on;
regulator-always-on;
};
BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <1045000>;
regulator-max-microvolt = <1155000>;
regulator-boot-on;
regulator-always-on;
};
LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <1950000>;
regulator-boot-on;
regulator-always-on;
};
LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <1710000>;
regulator-max-microvolt = <1890000>;
regulator-boot-on;
regulator-always-on;
};
LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
accelerometer@19 {
compatible = "st,lis2de12";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_accel>;
reg = <0x19>;
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT1";
};
switch: switch@5f {
compatible = "microchip,ksz9897";
reg = <0x5f>;
pinctrl-0 = <&pinctrl_ksz>;
interrupt-parent = <&gpio4>;
interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
ports {
#address-cells = <1>;
#size-cells = <0>;
lan1: port@0 {
reg = <0>;
label = "lan1";
local-mac-address = [00 00 00 00 00 00];
};
lan2: port@1 {
reg = <1>;
label = "lan2";
local-mac-address = [00 00 00 00 00 00];
};
lan3: port@2 {
reg = <2>;
label = "lan3";
local-mac-address = [00 00 00 00 00 00];
};
lan4: port@3 {
reg = <3>;
label = "lan4";
local-mac-address = [00 00 00 00 00 00];
};
lan5: port@4 {
reg = <4>;
label = "lan5";
local-mac-address = [00 00 00 00 00 00];
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&fec>;
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
/* off-board header */
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
/* off-board header */
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
};
/* GPS / off-board header */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* RS232 console */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
/* USB1 - Type C front panel */
&usb3_phy0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
status = "okay";
};
&usb3_0 {
fsl,over-current-active-low;
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "host";
status = "okay";
};
/* USB2 - USB3.0 Hub */
&usb3_phy1 {
vbus-supply = <&reg_usb2_vbus>;
status = "okay";
};
&usb3_1 {
fsl,permanently-attached;
fsl,disable-port-power-control;
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
/* eMMC */
&usdhc3 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000041 /* DIO0 */
MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000041 /* DIO1 */
MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000041 /* M2SKT_OFF# */
MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x40000159 /* PCIE1_WDIS# */
MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000159 /* PCIE2_WDIS# */
MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000159 /* PCIE3_WDIS# */
MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000041 /* M2SKT_RST# */
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000159 /* M2SKT_WDIS# */
MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000159 /* M2SKT_GDIS# */
MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */
MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */
MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */
>;
};
pinctrl_accel: accelgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x159
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x141 /* RST# */
MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x159 /* IRQ# */
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x141
MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x141
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
>;
};
pinctrl_gsc: gscgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x159
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
>;
};
pinctrl_ksz: kszgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x159 /* IRQ# */
MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x141 /* RST# */
>;
};
pinctrl_gpio_leds: ledgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x19
MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x19
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x141
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x141
>;
};
pinctrl_reg_can: regcangrp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154
>;
};
pinctrl_reg_usb2: regusb2grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x141
>;
};
pinctrl_reg_wifi: regwifigrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x119
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC
MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00
MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK
MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK
>;
};
pinctrl_spi2: spi2grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140
MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x140
>;
};
pinctrl_uart3_gpio: uart3gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x119
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
>;
};
pinctrl_usb1: usb1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140
MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
>;
};
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
/* TODO: Audio Codec */
&backlight {
power-supply = <&reg_3p3v>;
};
/* Verdin SPI_1 */
&ecspi1 {
status = "okay";
};
/* EEPROM on display adapter boards */
&eeprom_display_adapter {
status = "okay";
};
/* EEPROM on Verdin Development board */
&eeprom_carrier_board {
status = "okay";
};
&eqos {
status = "okay";
};
&flexcan1 {
status = "okay";
};
&flexcan2 {
status = "okay";
};
/* Verdin QSPI_1 */
&flexspi {
status = "okay";
};
/* Current measurement into module VCC */
&hwmon {
status = "okay";
};
&hwmon_temp {
vs-supply = <&reg_1p8v>;
status = "okay";
};
/* Verdin I2C_2_DSI */
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
/* Verdin I2C_1 */
&i2c4 {
status = "okay";
/* TODO: Audio Codec */
};
/* TODO: Verdin PCIE_1 */
/* Verdin PWM_1 */
&pwm1 {
status = "okay";
};
/* Verdin PWM_2 */
&pwm2 {
status = "okay";
};
/* Verdin PWM_3_DSI */
&pwm3 {
status = "okay";
};
&reg_usdhc2_vmmc {
vin-supply = <&reg_3p3v>;
};
/* TODO: Verdin I2S_1 */
/* Verdin UART_1 */
&uart1 {
status = "okay";
};
/* Verdin UART_2 */
&uart2 {
status = "okay";
};
/* Verdin UART_3, used as the Linux Console */
&uart3 {
status = "okay";
};
/* Verdin USB_1 */
&usb3_0 {
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
/* Verdin USB_2 */
&usb3_1 {
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
/* Verdin SD_1 */
&usdhc2 {
status = "okay";
};

46
arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi Normal file
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@ -0,0 +1,46 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
#include "imx8mp-verdin-dahlia.dtsi"
/ {
/* TODO: Audio Codec */
reg_eth2phy: regulator-eth2phy {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio_expander_21 4 GPIO_ACTIVE_HIGH>; /* ETH_PWR_EN */
off-on-delay = <500000>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "+V3.3_ETH";
startup-delay-us = <200000>;
vin-supply = <&reg_3p3v>;
};
};
&fec {
phy-supply = <&reg_eth2phy>;
status = "okay";
};
&gpio_expander_21 {
status = "okay";
vcc-supply = <&reg_1p8v>;
};
/* TODO: Verdin I2C_1 with Audio Codec */
/* Verdin UART_1, connector X50 through RS485 transceiver */
&uart1 {
linux,rs485-enabled-at-boot-time;
rs485-rts-active-low;
rs485-rx-during-tx;
};
/* Limit frequency on dev board due to long traces and bad signal integrity */
&usdhc2 {
max-frequency = <100000000>;
};

18
arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dahlia.dts Normal file
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@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
/dts-v1/;
#include "imx8mp-verdin.dtsi"
#include "imx8mp-verdin-nonwifi.dtsi"
#include "imx8mp-verdin-dahlia.dtsi"
/ {
model = "Toradex Verdin iMX8M Plus on Dahlia Board";
compatible = "toradex,verdin-imx8mp-nonwifi-dahlia",
"toradex,verdin-imx8mp-nonwifi",
"toradex,verdin-imx8mp",
"fsl,imx8mp";
};

18
arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dev.dts Normal file
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@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
/dts-v1/;
#include "imx8mp-verdin.dtsi"
#include "imx8mp-verdin-nonwifi.dtsi"
#include "imx8mp-verdin-dev.dtsi"
/ {
model = "Toradex Verdin iMX8M Plus on Verdin Development Board";
compatible = "toradex,verdin-imx8mp-nonwifi-dev",
"toradex,verdin-imx8mp-nonwifi",
"toradex,verdin-imx8mp",
"fsl,imx8mp";
};

54
arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi Normal file
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@ -0,0 +1,54 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
&gpio5 {
gpio-line-names = "SODIMM_42",
"SODIMM_46",
"SODIMM_187",
"SODIMM_20",
"SODIMM_22",
"SODIMM_15",
"SODIMM_196",
"SODIMM_200",
"SODIMM_198",
"SODIMM_202",
"SODIMM_164",
"SODIMM_152",
"SODIMM_116",
"SODIMM_128",
"",
"",
"SODIMM_55",
"SODIMM_53",
"SODIMM_95",
"SODIMM_93",
"SODIMM_14",
"SODIMM_12",
"SODIMM_129",
"SODIMM_131",
"SODIMM_137",
"SODIMM_139",
"SODIMM_147",
"SODIMM_149",
"SODIMM_151",
"SODIMM_153";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
<&pinctrl_gpio3>, <&pinctrl_gpio4>,
<&pinctrl_gpio7>, <&pinctrl_gpio8>,
<&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>,
<&pinctrl_hdmi_hog>;
};
/*
* Verdin UART_4
* Often used by the M7 and then should not be enabled here.
*/
&uart4 {
status = "disabled";
};

18
arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dahlia.dts Normal file
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@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
/dts-v1/;
#include "imx8mp-verdin.dtsi"
#include "imx8mp-verdin-wifi.dtsi"
#include "imx8mp-verdin-dahlia.dtsi"
/ {
model = "Toradex Verdin iMX8M Plus WB on Dahlia Board";
compatible = "toradex,verdin-imx8mp-wifi-dahlia",
"toradex,verdin-imx8mp-wifi",
"toradex,verdin-imx8mp",
"fsl,imx8mp";
};

18
arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dev.dts Normal file
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@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
/dts-v1/;
#include "imx8mp-verdin.dtsi"
#include "imx8mp-verdin-wifi.dtsi"
#include "imx8mp-verdin-dev.dtsi"
/ {
model = "Toradex Verdin iMX8M Plus WB on Verdin Development Board";
compatible = "toradex,verdin-imx8mp-wifi-dev",
"toradex,verdin-imx8mp-wifi",
"toradex,verdin-imx8mp",
"fsl,imx8mp";
};

82
arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi Normal file
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@ -0,0 +1,82 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
/ {
reg_wifi_en: regulator-wifi-en {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi_pwr_en>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "PDn_AW-CM276NF";
startup-delay-us = <2000>;
};
};
&gpio5 {
gpio-line-names = "SODIMM_42",
"SODIMM_46",
"SODIMM_187",
"SODIMM_20",
"SODIMM_22",
"SODIMM_15",
"SODIMM_196",
"SODIMM_200",
"SODIMM_198",
"SODIMM_202",
"",
"",
"",
"",
"",
"",
"SODIMM_55",
"SODIMM_53",
"SODIMM_95",
"SODIMM_93",
"SODIMM_14",
"SODIMM_12",
"SODIMM_129",
"SODIMM_131",
"SODIMM_137",
"SODIMM_139",
"SODIMM_147",
"SODIMM_149",
"SODIMM_151",
"SODIMM_153";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
<&pinctrl_gpio3>, <&pinctrl_gpio4>,
<&pinctrl_gpio7>, <&pinctrl_gpio8>,
<&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, <&pinctrl_gpio_hog4>,
<&pinctrl_hdmi_hog>;
};
/* On-module Bluetooth */
&uart4 {
uart-has-rtscts;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bt_uart>;
status = "okay";
};
/* On-module Wi-Fi */
&usdhc1 {
bus-width = <4>;
keep-power-in-suspend;
max-frequency = <100000000>;
non-removable;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi_ctrl>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi_ctrl>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi_ctrl>;
vmmc-supply = <&reg_wifi_en>;
status = "okay";
};

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247
arch/arm64/boot/dts/freescale/imx8mp.dtsi
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@ -4,6 +4,7 @@
*/
#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/power/imx8mp-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -58,6 +59,9 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
nvmem-cells = <&cpu_speed_grade>;
nvmem-cell-names = "speed_grade";
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
};
@ -75,6 +79,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
};
@ -92,6 +97,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
};
@ -109,6 +115,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
};
@ -121,6 +128,35 @@
};
};
a53_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <850000>;
opp-supported-hw = <0x8a0>, <0x7>;
clock-latency-ns = <150000>;
opp-suspend;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <950000>;
opp-supported-hw = <0xa0>, <0x7>;
clock-latency-ns = <150000>;
opp-suspend;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1000000>;
opp-supported-hw = <0x20>, <0x3>;
clock-latency-ns = <150000>;
opp-suspend;
};
};
osc_32k: clock-osc-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -475,6 +511,94 @@
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
gpc: gpc@303a0000 {
compatible = "fsl,imx8mp-gpc";
reg = <0x303a0000 0x1000>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <3>;
pgc {
#address-cells = <1>;
#size-cells = <0>;
pgc_mipi_phy1: power-domain@0 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
};
pgc_pcie_phy: power-domain@1 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
};
pgc_usb1_phy: power-domain@2 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
};
pgc_usb2_phy: power-domain@3 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
};
pgc_gpu2d: power-domain@6 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
power-domains = <&pgc_gpumix>;
};
pgc_gpumix: power-domain@7 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_GPUMIX>;
clocks = <&clk IMX8MP_CLK_GPU_ROOT>,
<&clk IMX8MP_CLK_GPU_AHB>;
assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
<&clk IMX8MP_CLK_GPU_AHB>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <800000000>, <400000000>;
};
pgc_gpu3d: power-domain@9 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
<&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
power-domains = <&pgc_gpumix>;
};
pgc_mediamix: power-domain@10 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
};
pgc_mipi_phy2: power-domain@16 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
};
pgc_hsiomix: power-domains@17 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
<&clk IMX8MP_CLK_HSIO_ROOT>;
assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
assigned-clock-rates = <500000000>;
};
pgc_ispdwp: power-domain@18 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>;
};
};
};
};
aips2: bus@30400000 {
@ -491,7 +615,7 @@
clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
<&clk IMX8MP_CLK_PWM1_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -502,7 +626,7 @@
clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
<&clk IMX8MP_CLK_PWM2_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -513,7 +637,7 @@
clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
<&clk IMX8MP_CLK_PWM3_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -524,7 +648,7 @@
clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
<&clk IMX8MP_CLK_PWM4_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -617,6 +741,8 @@
clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
<&clk IMX8MP_CLK_UART2_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -769,7 +895,7 @@
};
usdhc1: mmc@30b40000 {
compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_DUMMY>,
@ -783,7 +909,7 @@
};
usdhc2: mmc@30b50000 {
compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_DUMMY>,
@ -797,7 +923,7 @@
};
usdhc3: mmc@30b60000 {
compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b60000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_DUMMY>,
@ -892,6 +1018,97 @@
};
};
aips4: bus@32c00000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x32c00000 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
media_blk_ctrl: blk-ctrl@32ec0000 {
compatible = "fsl,imx8mp-media-blk-ctrl",
"syscon";
reg = <0x32ec0000 0x10000>;
power-domains = <&pgc_mediamix>,
<&pgc_mipi_phy1>,
<&pgc_mipi_phy1>,
<&pgc_mediamix>,
<&pgc_mediamix>,
<&pgc_mipi_phy2>,
<&pgc_mediamix>,
<&pgc_ispdwp>,
<&pgc_ispdwp>,
<&pgc_mipi_phy2>;
power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
"lcdif1", "isi", "mipi-csi2",
"lcdif2", "isp", "dwe",
"mipi-dsi2";
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
clock-names = "apb", "axi", "cam1", "cam2",
"disp1", "disp2", "isp", "phy";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <500000000>, <200000000>;
#power-domain-cells = <1>;
};
hsio_blk_ctrl: blk-ctrl@32f10000 {
compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
reg = <0x32f10000 0x24>;
clocks = <&clk IMX8MP_CLK_USB_ROOT>,
<&clk IMX8MP_CLK_PCIE_ROOT>;
clock-names = "usb", "pcie";
power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
<&pgc_usb1_phy>, <&pgc_usb2_phy>,
<&pgc_hsiomix>, <&pgc_pcie_phy>;
power-domain-names = "bus", "usb", "usb-phy1",
"usb-phy2", "pcie", "pcie-phy";
#power-domain-cells = <1>;
};
};
gpu3d: gpu@38000000 {
compatible = "vivante,gc";
reg = <0x38000000 0x8000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
<&clk IMX8MP_CLK_GPU3D_SHADER_CORE>,
<&clk IMX8MP_CLK_GPU_ROOT>,
<&clk IMX8MP_CLK_GPU_AHB>;
clock-names = "core", "shader", "bus", "reg";
assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
<&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <800000000>, <800000000>;
power-domains = <&pgc_gpu3d>;
};
gpu2d: gpu@38008000 {
compatible = "vivante,gc";
reg = <0x38008000 0x8000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
<&clk IMX8MP_CLK_GPU_ROOT>,
<&clk IMX8MP_CLK_GPU_AHB>;
clock-names = "core", "bus", "reg";
assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <800000000>;
power-domains = <&pgc_gpu2d>;
};
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>,
@ -902,6 +1119,12 @@
interrupt-parent = <&gic>;
};
edacmc: memory-controller@3d400000 {
compatible = "snps,ddrc-3.80a";
reg = <0x3d400000 0x400000>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
};
ddr-pmu@3d800000 {
compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
reg = <0x3d800000 0x400000>;
@ -915,6 +1138,7 @@
clock-names = "phy";
assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
#phy-cells = <0>;
status = "disabled";
};
@ -927,6 +1151,7 @@
<&clk IMX8MP_CLK_USB_ROOT>;
clock-names = "hsio", "suspend";
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
#address-cells = <1>;
#size-cells = <1>;
dma-ranges = <0x40000000 0x40000000 0xc0000000>;
@ -940,9 +1165,6 @@
<&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
clock-names = "bus_early", "ref", "suspend";
assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
assigned-clock-rates = <500000000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb3_phy0>, <&usb3_phy0>;
phy-names = "usb2-phy", "usb3-phy";
@ -958,6 +1180,7 @@
clock-names = "phy";
assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
#phy-cells = <0>;
status = "disabled";
};
@ -970,6 +1193,7 @@
<&clk IMX8MP_CLK_USB_ROOT>;
clock-names = "hsio", "suspend";
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
#address-cells = <1>;
#size-cells = <1>;
dma-ranges = <0x40000000 0x40000000 0xc0000000>;
@ -983,9 +1207,6 @@
<&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
clock-names = "bus_early", "ref", "suspend";
assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
assigned-clock-rates = <500000000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb3_phy1>, <&usb3_phy1>;
phy-names = "usb2-phy", "usb3-phy";

2
arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
View File

@ -311,7 +311,7 @@
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
fsl,uart-has-rtscts;
uart-has-rtscts;
assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
status = "okay";

2
arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
View File

@ -18,7 +18,7 @@
backlight_dsi: backlight-dsi {
compatible = "pwm-backlight";
/* 200 Hz for the PAM2841 */
pwms = <&pwm1 0 5000000>;
pwms = <&pwm1 0 5000000 0>;
brightness-levels = <0 100>;
num-interpolated-steps = <100>;
/* Default brightness level (index into the array defined by */

4
arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts
View File

@ -18,6 +18,10 @@
led-max-microamp = <25000>;
};
&lcd_panel {
compatible = "ys,ys57pss36bh5gq";
};
&proximity {
proximity-near-level = <10>;
};

15
arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
View File

@ -42,6 +42,7 @@
gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <50>;
wakeup-source;
};
vol-up {
@ -49,6 +50,7 @@
gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <50>;
wakeup-source;
};
};
@ -323,15 +325,10 @@
};
partition@30000 {
label = "protected1";
reg = <0x30000 0x10000>;
label = "firmware";
reg = <0x30000 0x1d0000>;
read-only;
};
partition@40000 {
label = "rw";
reg = <0x40000 0x1C0000>;
};
};
};
@ -387,8 +384,6 @@
fsl,pins = <
/* CHRG_INT */
MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x80
/* CHG_STATUS_B */
MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x80
>;
};
@ -1098,7 +1093,7 @@
ti,precharge-current = <130000>; /* uA */
ti,minimum-sys-voltage = <3700000>; /* uV */
ti,boost-voltage = <5000000>; /* uV */
ti,boost-max-current = <500000>; /* uA */
ti,boost-max-current = <1500000>; /* uA */
ti,use-vinmin-threshold = <1>; /* enable VINDPM */
ti,vinmin-threshold = <3900000>; /* uV */
monitored-battery = <&bat>;

2
arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
View File

@ -18,7 +18,7 @@
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
pwms = <&pwm2 0 10000>;
pwms = <&pwm2 0 10000 0>;
power-supply = <&reg_main_usb>;
enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
brightness-levels = <0 32 64 128 160 200 255>;

15
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -63,6 +63,13 @@
clock-output-names = "osc_27m";
};
hdmi_phy_27m: clock-hdmi-phy-27m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
clock-output-names = "hdmi_phy_27m";
};
clk_ext1: clock-ext1 {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -791,7 +798,7 @@
clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
<&clk IMX8MQ_CLK_PWM1_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -802,7 +809,7 @@
clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
<&clk IMX8MQ_CLK_PWM2_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -813,7 +820,7 @@
clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
<&clk IMX8MQ_CLK_PWM3_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -824,7 +831,7 @@
clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
<&clk IMX8MQ_CLK_PWM4_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};

25
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
View File

@ -135,6 +135,14 @@
status = "okay";
};
&mu_m0 {
status = "okay";
};
&mu1_m0 {
status = "okay";
};
&scu_key {
status = "okay";
};
@ -196,6 +204,23 @@
status = "okay";
};
&vpu {
compatible = "nxp,imx8qxp-vpu";
status = "okay";
};
&vpu_core0 {
reg = <0x2d040000 0x10000>;
memory-region = <&decoder_boot>, <&decoder_rpc>;
status = "okay";
};
&vpu_core1 {
reg = <0x2d050000 0x10000>;
memory-region = <&encoder_boot>, <&encoder_rpc>;
status = "okay";
};
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <

24
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
View File

@ -46,6 +46,9 @@
serial1 = &lpuart1;
serial2 = &lpuart2;
serial3 = &lpuart3;
vpu_core0 = &vpu_core0;
vpu_core1 = &vpu_core1;
vpu_core2 = &vpu_core2;
};
cpus {
@ -162,10 +165,30 @@
#size-cells = <2>;
ranges;
decoder_boot: decoder-boot@84000000 {
reg = <0 0x84000000 0 0x2000000>;
no-map;
};
encoder_boot: encoder-boot@86000000 {
reg = <0 0x86000000 0 0x200000>;
no-map;
};
decoder_rpc: decoder-rpc@92000000 {
reg = <0 0x92000000 0 0x100000>;
no-map;
};
dsp_reserved: dsp@92400000 {
reg = <0 0x92400000 0 0x2000000>;
no-map;
};
encoder_rpc: encoder-rpc@94400000 {
reg = <0 0x94400000 0 0x700000>;
no-map;
};
};
pmu {
@ -287,6 +310,7 @@
/* sorted in register address */
#include "imx8-ss-img.dtsi"
#include "imx8-ss-vpu.dtsi"
#include "imx8-ss-adma.dtsi"
#include "imx8-ss-conn.dtsi"
#include "imx8-ss-ddr.dtsi"