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drm/i915/tgl: Enabling DSC on Pipe A for TGL
DSC was not supported on Pipe A for previous platforms. Tigerlake onwards, all the pipes support DSC. Hence, the DSC and FEC restriction on Pipe A needs to be removed. v2: Changes in the logic around removing the restriction around Pipe A (Manasi, Lucas) Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190823004655.28905-1-madhumitha.tolakanahalli.pradeep@intel.com
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@ -1737,8 +1737,14 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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return INTEL_GEN(dev_priv) >= 11 &&
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pipe_config->cpu_transcoder != TRANSCODER_A;
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/* On TGL, FEC is supported on all Pipes */
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if (INTEL_GEN(dev_priv) >= 12)
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return true;
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if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
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return true;
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return false;
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}
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static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
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@ -1753,8 +1759,15 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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return INTEL_GEN(dev_priv) >= 10 &&
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pipe_config->cpu_transcoder != TRANSCODER_A;
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/* On TGL, DSC is supported on all Pipes */
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if (INTEL_GEN(dev_priv) >= 12)
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return true;
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if (INTEL_GEN(dev_priv) >= 10 &&
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pipe_config->cpu_transcoder != TRANSCODER_A)
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return true;
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return false;
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}
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static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
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