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The i.MX device tree updates for 4.1:

Browse Source 
- Convert GPC controller to use stacked interrupt domains
  - Add power domain descriptions for i.MX6 platforms
  - Improve i.MX25 pin function defines
  - Disable PWM devices in <soc>.dtsi by default and enable it at board
    level dts where the device is actually available.
  - Define labels for SNVS RTC device to ease the board description,
    where an external RTC is available.
  - Add dr_mode host setting to all i.MX host-only USB instances
  - Support Miscellaneous System Control Module (MSCM) for VF610
  - Add initial i.MX6SL WaRP Board support
  - Add i.MX6SX SDB revision B board support
  - A bunch of imx28-apf28dev board updates, including gpio polarity
    correction and CAN, AUART device support.
  - SolidRun iMX6 platform updates: dual-license of GPLv2/X11, PWM
    setup, PCF8523 RTC, GPIO key and SGTL5000 audio support.
  - A number of random device additions for boards: SPI and CAN for
    vf-colibri, MAX7310 GPIO expander for imx6qdl-sabreauto and LCD
    support for imx25-pdk.
 
 Note: Branch imx/cleanup was merged as the base to solve conflict on
 imx25 iomux header.  Branch imx/soc was merged as the base to solve
 conflict on arch/arm/mach-imx/gpc.c.  And Jason Cooper's irqchip/vybrid
 branch was pulled into the base as a run-time dependency.
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Merge tag 'imx-dt-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/late

Pull "The i.MX device tree updates for 4.1" from Shawn Guo:

 - Convert GPC controller to use stacked interrupt domains
 - Add power domain descriptions for i.MX6 platforms
 - Improve i.MX25 pin function defines
 - Disable PWM devices in <soc>.dtsi by default and enable it at board
   level dts where the device is actually available.
 - Define labels for SNVS RTC device to ease the board description,
   where an external RTC is available.
 - Add dr_mode host setting to all i.MX host-only USB instances
 - Support Miscellaneous System Control Module (MSCM) for VF610
 - Add initial i.MX6SL WaRP Board support
 - Add i.MX6SX SDB revision B board support
 - A bunch of imx28-apf28dev board updates, including gpio polarity
   correction and CAN, AUART device support.
 - SolidRun iMX6 platform updates: dual-license of GPLv2/X11, PWM
   setup, PCF8523 RTC, GPIO key and SGTL5000 audio support.
 - A number of random device additions for boards: SPI and CAN for
   vf-colibri, MAX7310 GPIO expander for imx6qdl-sabreauto and LCD
   support for imx25-pdk.

Note: Branch imx/cleanup was merged as the base to solve conflict on
imx25 iomux header.  Branch imx/soc was merged as the base to solve
conflict on arch/arm/mach-imx/gpc.c.  And Jason Cooper's irqchip/vybrid
branch was pulled into the base as a run-time dependency.

* tag 'imx-dt-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (69 commits)
  ARM: dts: hummingboard: add sgtl5000 support for Hummingboard Pro
  ARM: dts: imx25-pinfunc: Add several pinfunctions
  ARM: dts: vf610: fix missing irqs
  ARM: dts: cubox: Map gpio-keys to gpio3 8
  ARM: dts: hummingboard: Setup pwm lines
  ARM: dts: hummingboard: enable PCF8523 RTC support
  ARM: dts: Re-license SolidRun iMX6 platform DT GPL v2/X11
  ARM: dts: imx28: add alternative pinmuxing for spi3
  ARM: dts: imx6sx: Add label snvs_rtc
  ARM: dts: imx6sl: Add label snvs_rtc
  ARM: imx6: Warn when an old DT is detected
  ARM: imx6: Allow GPC interrupts affinity to be changed
  ARM: imx6qdl-sabreauto.dtsi: add max7310 support
  ARM: dts: imx6sl-warp: Add BCM4330 support
  ARM: dts: imx28-apf28dev: add wakeup function to user button
  ARM: dts: imx28-apf28dev: fix user button polarity
  ARM: dts: imx25-pinfunc: remove input values for pinfuncs without input register
  ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
  ARM: dts: imx6sl-warp: Pass 'bus-width' property
  ARM: dts: imx6qdl: disable PWMs by default
  ...
This commit is contained in:
Arnd Bergmann 2015-04-14 01:18:44 +02:00
commit 9705feacb7
88 changed files with 2529 additions and 2766 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt Normal file
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@ -0,0 +1,14 @@
Freescale Vybrid Miscellaneous System Control - CPU Configuration
The MSCM IP contains multiple sub modules, this binding describes the first
block of registers which contains CPU configuration information.
Required properties:
- compatible: "fsl,vf610-mscm-cpucfg", "syscon"
- reg: the register range of the MSCM CPU configuration registers
Example:
mscm_cpucfg: cpucfg@40001000 {
compatible = "fsl,vf610-mscm-cpucfg", "syscon";
reg = <0x40001000 0x800>;
}

33
Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt Normal file
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@ -0,0 +1,33 @@
Freescale Vybrid Miscellaneous System Control - Interrupt Router
The MSCM IP contains multiple sub modules, this binding describes the second
block of registers which control the interrupt router. The interrupt router
allows to configure the recipient of each peripheral interrupt. Furthermore
it controls the directed processor interrupts. The module is available in all
Vybrid SoC's but is only really useful in dual core configurations (VF6xx
which comes with a Cortex-A5/Cortex-M4 combination).
Required properties:
- compatible: "fsl,vf610-mscm-ir"
- reg: the register range of the MSCM Interrupt Router
- fsl,cpucfg: The handle to the MSCM CPU configuration node, required
to get the current CPU ID
- interrupt-controller: Identifies the node as an interrupt controller
- #interrupt-cells: Two cells, interrupt number and cells.
The hardware interrupt number according to interrupt
assignment of the interrupt router is required.
Flags get passed only when using GIC as parent. Flags
encoding as documented by the GIC bindings.
- interrupt-parent: Should be the phandle for the interrupt controller of
the CPU the device tree is intended to be used on. This
is either the node of the GIC or NVIC controller.
Example:
mscm_ir: interrupt-controller@40001800 {
compatible = "fsl,vf610-mscm-ir";
reg = <0x40001800 0x400>;
fsl,cpucfg = <&mscm_cpucfg>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
}

59
Documentation/devicetree/bindings/power/fsl,imx-gpc.txt Normal file
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@ -0,0 +1,59 @@
Freescale i.MX General Power Controller
=======================================
The i.MX6Q General Power Control (GPC) block contains DVFS load tracking
counters and Power Gating Control (PGC) for the CPU and PU (GPU/VPU) power
domains.
Required properties:
- compatible: Should be "fsl,imx6q-gpc" or "fsl,imx6sl-gpc"
- reg: should be register base and length as documented in the
datasheet
- interrupts: Should contain GPC interrupt request 1
- pu-supply: Link to the LDO regulator powering the PU power domain
- clocks: Clock phandles to devices in the PU power domain that need
to be enabled during domain power-up for reset propagation.
- #power-domain-cells: Should be 1, see below:
The gpc node is a power-controller as documented by the generic power domain
bindings in Documentation/devicetree/bindings/power/power_domain.txt.
Example:
gpc: gpc@020dc000 {
compatible = "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
<0 90 IRQ_TYPE_LEVEL_HIGH>;
pu-supply = <&reg_pu>;
clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
<&clks IMX6QDL_CLK_GPU3D_SHADER>,
<&clks IMX6QDL_CLK_GPU2D_CORE>,
<&clks IMX6QDL_CLK_GPU2D_AXI>,
<&clks IMX6QDL_CLK_OPENVG_AXI>,
<&clks IMX6QDL_CLK_VPU_AXI>;
#power-domain-cells = <1>;
};
Specifying power domain for IP modules
======================================
IP cores belonging to a power domain should contain a 'power-domains' property
that is a phandle pointing to the gpc device node and a DOMAIN_INDEX specifying
the power domain the device belongs to.
Example of a device that is part of the PU power domain:
vpu: vpu@02040000 {
reg = <0x02040000 0x3c000>;
/* ... */
power-domains = <&gpc 1>;
/* ... */
};
The following DOMAIN_INDEX values are valid for i.MX6Q:
ARM_DOMAIN 0
PU_DOMAIN 1
The following additional DOMAIN_INDEX value is valid for i.MX6SL:
DISPLAY_DOMAIN 2

4
arch/arm/boot/dts/Makefile
View File

@ -299,9 +299,11 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-wandboard.dtb \
imx6q-wandboard-revb1.dtb
dtb-$(CONFIG_SOC_IMX6SL) += \
imx6sl-evk.dtb
imx6sl-evk.dtb \
imx6sl-warp.dtb
dtb-$(CONFIG_SOC_IMX6SX) += \
imx6sx-sabreauto.dtb \
imx6sx-sdb-reva.dtb \
imx6sx-sdb.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-qds.dtb \

58
arch/arm/boot/dts/imx25-pdk.dts
View File

@ -75,6 +75,27 @@
mux-int-port = <1>;
mux-ext-port = <4>;
};
wvga: display {
model = "CLAA057VC01CW";
bits-per-pixel = <16>;
fsl,pcr = <0xfa208b80>;
bus-width = <18>;
native-mode = <&wvga_timings>;
display-timings {
wvga_timings: 640x480 {
hactive = <640>;
vactive = <480>;
hback-porch = <45>;
hfront-porch = <114>;
hsync-len = <1>;
vback-porch = <33>;
vfront-porch = <11>;
vsync-len = <1>;
clock-frequency = <25200000>;
};
};
};
};
&audmux {
@ -190,6 +211,33 @@
>;
};
pinctrl_lcd: lcdgrp {
fsl,pins = <
MX25_PAD_LD0__LD0 0xe0
MX25_PAD_LD1__LD1 0xe0
MX25_PAD_LD2__LD2 0xe0
MX25_PAD_LD3__LD3 0xe0
MX25_PAD_LD4__LD4 0xe0
MX25_PAD_LD5__LD5 0xe0
MX25_PAD_LD6__LD6 0xe0
MX25_PAD_LD7__LD7 0xe0
MX25_PAD_LD8__LD8 0xe0
MX25_PAD_LD9__LD9 0xe0
MX25_PAD_LD10__LD10 0xe0
MX25_PAD_LD11__LD11 0xe0
MX25_PAD_LD12__LD12 0xe0
MX25_PAD_LD13__LD13 0xe0
MX25_PAD_LD14__LD14 0xe0
MX25_PAD_LD15__LD15 0xe0
MX25_PAD_GPIO_E__LD16 0xe0
MX25_PAD_GPIO_F__LD17 0xe0
MX25_PAD_HSYNC__HSYNC 0xe0
MX25_PAD_VSYNC__VSYNC 0xe0
MX25_PAD_LSCLK__LSCLK 0xe0
MX25_PAD_OE_ACD__OE_ACD 0xe0
MX25_PAD_CONTRAST__CONTRAST 0xe0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
@ -202,6 +250,16 @@
};
};
&lcdc {
display = <&wvga>;
fsl,lpccr = <0x00a903ff>;
fsl,lscr1 = <0x00120300>;
fsl,dmacr = <0x00020010>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
status = "okay";
};
&nfc {
nand-on-flash-bbt;
status = "okay";

86
arch/arm/boot/dts/imx25-pinfunc.h
View File

@ -17,48 +17,69 @@
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000
#define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
#define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
#define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
#define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
#define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
#define MX25_PAD_A14__A14 0x010 0x230 0x000 0x10 0x000
#define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x15 0x000
#define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x16 0x000
#define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x17 0x000
#define MX25_PAD_A15__A15 0x014 0x234 0x000 0x10 0x000
#define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x15 0x000
#define MX25_PAD_A15__SIM1_RST1 0x014 0x234 0x000 0x16 0x000
#define MX25_PAD_A15__LCDC_PS 0x014 0x234 0x000 0x17 0x000
#define MX25_PAD_A16__A16 0x018 0x000 0x000 0x10 0x000
#define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x15 0x000
#define MX25_PAD_A16__SIM1_VEN1 0x018 0x000 0x000 0x16 0x000
#define MX25_PAD_A16__LCDC_REV 0x018 0x000 0x000 0x17 0x000
#define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x10 0x000
#define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x15 0x000
#define MX25_PAD_A17__SIM1_TX 0x01c 0x238 0x554 0x16 0x000
#define MX25_PAD_A17__FEC_TX_ERR 0x01c 0x238 0x000 0x17 0x000
#define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x10 0x000
#define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x15 0x000
#define MX25_PAD_A18__SIM1_PD1 0x020 0x23c 0x550 0x16 0x000
#define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x17 0x000
#define MX25_PAD_A19__A19 0x024 0x240 0x000 0x10 0x000
#define MX25_PAD_A19__FEC_RX_ER 0x024 0x240 0x518 0x17 0x000
#define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x15 0x000
#define MX25_PAD_A19__SIM1_RX1 0x024 0x240 0x54c 0x16 0x000
#define MX25_PAD_A19__FEC_RX_ERR 0x024 0x240 0x518 0x17 0x000
#define MX25_PAD_A20__A20 0x028 0x244 0x000 0x10 0x000
#define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x15 0x000
#define MX25_PAD_A20__SIM2_CLK1 0x028 0x244 0x000 0x16 0x000
#define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x17 0x000
#define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x10 0x000
#define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x15 0x000
#define MX25_PAD_A21__SIM2_RST1 0x02c 0x248 0x000 0x16 0x000
#define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x17 0x000
#define MX25_PAD_A22__A22 0x030 0x000 0x000 0x10 0x000
#define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x15 0x000
#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x17 0x000
#define MX25_PAD_A22__SIM2_VEN1 0x030 0x000 0x000 0x16 0x000
#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x17 0x000
#define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x10 0x000
#define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x15 0x000
#define MX25_PAD_A23__SIM2_TX1 0x034 0x24c 0x560 0x16 0x000
#define MX25_PAD_A23__FEC_TDATA3 0x034 0x24c 0x000 0x17 0x000
#define MX25_PAD_A24__A24 0x038 0x250 0x000 0x10 0x000
#define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x15 0x000
#define MX25_PAD_A24__SIM2_PD1 0x038 0x250 0x55c 0x16 0x000
#define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x17 0x000
#define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x10 0x000
@ -133,20 +154,25 @@
#define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000
#define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000
#define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000
#define MX25_PAD_D15__SDHC1_DAT7 0x088 0x280 0x4d8 0x06 0x000
#define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000
#define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000
#define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000
#define MX25_PAD_D14__SDHC1_DAT6 0x08c 0x284 0x4d4 0x06 0x000
#define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000
#define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000
#define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000
#define MX25_PAD_D13__SDHC1_DAT5 0x090 0x288 0x4d0 0x06 0x000
#define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000
#define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000
#define MX25_PAD_D12__SDHC1_DAT4 0x094 0x28c 0x4cc 0x06 0x000
#define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000
#define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000
#define MX25_PAD_D11__USBOTG_PWR 0x098 0x290 0x000 0x06 0x000
#define MX25_PAD_D10__D10 0x09c 0x294 0x000 0x00 0x000
#define MX25_PAD_D10__GPIO_4_10 0x09c 0x294 0x000 0x05 0x000
@ -212,26 +238,33 @@
#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x10 0x000
#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x15 0x000
#define MX25_PAD_LD8__SDHC2_CMD 0x0e8 0x2e0 0x4e0 0x06 0x000
#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x10 0x000
#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x15 0x001
#define MX25_PAD_LD9__SDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000
#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x10 0x000
#define MX25_PAD_LD10__FEC_RX_ER 0x0f0 0x2e8 0x518 0x15 0x001
#define MX25_PAD_LD10__FEC_RX_ERR 0x0f0 0x2e8 0x518 0x15 0x001
#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x10 0x000
#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x15 0x001
#define MX25_PAD_LD11__SDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000
#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x10 0x000
#define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000
#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x15 0x001
#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x10 0x000
#define MX25_PAD_LD13__CSPI2_MISO 0x0fc 0x2f4 0x49c 0x02 0x000
#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x15 0x000
#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x10 0x000
#define MX25_PAD_LD14__CSPI2_SCLK 0x100 0x2f8 0x494 0x02 0x000
#define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x15 0x000
#define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x10 0x000
#define MX25_PAD_LD15__CSPI2_RDY 0x104 0x2fc 0x498 0x02 0x000
#define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x15 0x001
#define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x10 0x000
@ -244,6 +277,7 @@
#define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x15 0x000
#define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x10 0x000
#define MX25_PAD_OE_ACD__CSPI2_SS0 0x114 0x30c 0x4a4 0x02 0x000
#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000
#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000
@ -257,26 +291,31 @@
#define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x10 0x000
#define MX25_PAD_CSI_D2__UART5_RXD_MUX 0x120 0x318 0x578 0x11 0x001
#define MX25_PAD_CSI_D2__SIM1_CLK0 0x120 0x318 0x000 0x04 0x000
#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x15 0x000
#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000
#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000
#define MX25_PAD_CSI_D3__UART5_TXD_MUX 0x124 0x31c 0x000 0x11 0x000
#define MX25_PAD_CSI_D3__SIM1_RST0 0x124 0x31c 0x000 0x04 0x000
#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000
#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001
#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x10 0x000
#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x11 0x001
#define MX25_PAD_CSI_D4__SIM1_VEN0 0x128 0x320 0x000 0x04 0x000
#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x15 0x000
#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000
#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000
#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x001
#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x000
#define MX25_PAD_CSI_D5__SIM1_TX0 0x12c 0x324 0x000 0x04 0x000
#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000
#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000
#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000
#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001
#define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000
#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000
#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000
@ -284,32 +323,32 @@
#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000
#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000
#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x12 0x001
#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x12 0x000
#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000
#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x17 0x000
#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000
#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x12 0x001
#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x12 0x000
#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000
#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x17 0x000
#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000
#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x11 0x001
#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x11 0x000
#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x12 0x001
#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000
#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000
#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x11 0x001
#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x11 0x000
#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x12 0x001
#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000
#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000
#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x11 0x001
#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x11 0x000
#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x12 0x001
#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000
#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000
#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x11 0x001
#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x11 0x000
#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x12 0x001
#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000
@ -369,8 +408,8 @@
#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x13 0x000
#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000
#define MX25_PAD_UART2_CTS__FEC_RX_ER 0x18c 0x384 0x518 0x12 0x002
#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x10 0x000
#define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x12 0x002
#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000
#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000
@ -392,11 +431,11 @@
#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x15 0x000
#define MX25_PAD_SD1_DATA2__SD1_DATA2 0x1a0 0x398 0x000 0x10 0x000
#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x15 0x002
#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x12 0x002
#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x15 0x000
#define MX25_PAD_SD1_DATA3__SD1_DATA3 0x1a4 0x39c 0x000 0x10 0x000
#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x10 0x002
#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x12 0x002
#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x15 0x000
#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x10 0x000
@ -410,7 +449,7 @@
#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x15 0x000
#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x10 0x000
#define MX25_PAD_KPP_ROW3__CSI_LD1 0x1b4 0x3ac 0x48c 0x13 0x002
#define MX25_PAD_KPP_ROW3__CSI_D1 0x1b4 0x3ac 0x48c 0x13 0x002
#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x15 0x000
#define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x10 0x000
@ -455,9 +494,18 @@
#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x15 0x000
#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x10 0x000
/*
* According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
* 01/2011) this is CAN1_TX but that's wrong.
*/
#define MX25_PAD_FEC_RDATA1__CAN2_TX 0x1e0 0x3d8 0x000 0x14 0x000
#define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x15 0x000
#define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x10 0x000
/*
* According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
* 01/2011) this is CAN1_RX but that's wrong.
*/
#define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x14 0x000
#define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x15 0x000
@ -471,30 +519,34 @@
#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x10 0x000
#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x15 0x000
#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000
#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x10 0x000
#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x16 0x000
#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x12 0x000
#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x10 0x000
#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x16 0x001
#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x12 0x001
#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x16 0x001
#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x10 0x000
#define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x11 0x000
#define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x12 0x001
#define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x13 0x001
#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000
#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000
#define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x12 0x001
#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001
#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000
#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x11 0x002
#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x12 0x000
#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000
#define MX25_PAD_GPIO_E__UART4_RXD 0x204 0x400 0x570 0x16 0x002
#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000
#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x12 0x000
#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000
#define MX25_PAD_GPIO_F__UART4_TXD 0x208 0x404 0x000 0x16 0x000
#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000
#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x15 0x000
@ -505,6 +557,7 @@
#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x10 0x000
#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x14 0x000
#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x15 0x000
#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x10 0x000
#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x15 0x000
@ -517,6 +570,7 @@
#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 0x224 0x000 0x000 0x00 0x000
#define MX25_PAD_BOOT_MODE0__GPIO_4_30 0x224 0x000 0x000 0x05 0x000
#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000
#define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000

2
arch/arm/boot/dts/imx27.dtsi
View File

@ -488,6 +488,7 @@
interrupts = <54>;
clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
fsl,usbmisc = <&usbmisc 1>;
dr_mode = "host";
status = "disabled";
};
@ -497,6 +498,7 @@
interrupts = <55>;
clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
fsl,usbmisc = <&usbmisc 2>;
dr_mode = "host";
status = "disabled";
};

2
arch/arm/boot/dts/imx28-apf28.dts
View File

@ -78,7 +78,7 @@
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a>;
phy-reset-gpios = <&gpio4 13 0>;
phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
status = "okay";
};
};

30
arch/arm/boot/dts/imx28-apf28dev.dts
View File

@ -110,6 +110,13 @@
};
};
};
can0: can@80032000 {
pinctrl-names = "default";
pinctrl-0 = <&can0_pins_a>;
xceiver-supply = <&reg_can0_vcc>;
status = "okay";
};
};
apbx@80040000 {
@ -130,6 +137,13 @@
status = "okay";
};
auart0: serial@8006a000 {
pinctrl-names = "default";
pinctrl-0 = <&auart0_pins_a>;
fsl,uart-has-rtscts;
status = "okay";
};
usbphy0: usbphy@8007c000 {
status = "okay";
};
@ -143,7 +157,8 @@
ahb@80080000 {
usb0: usb@80080000 {
pinctrl-names = "default";
pinctrl-0 = <&usb0_otg_apf28dev>;
pinctrl-0 = <&usb0_otg_apf28dev
&usb0_id_pins_b>;
vbus-supply = <&reg_usb0_vbus>;
status = "okay";
};
@ -156,7 +171,7 @@
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac1_pins_a>;
phy-reset-gpios = <&gpio0 23 0>;
phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
status = "okay";
};
};
@ -175,6 +190,14 @@
gpio = <&gpio1 23 1>;
enable-active-high;
};
reg_can0_vcc: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "can0_vcc";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
leds {
@ -200,8 +223,9 @@
user-button {
label = "User button";
gpios = <&gpio0 17 0>;
gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
linux,code = <0x100>;
gpio-key,wakeup;
};
};
};

14
arch/arm/boot/dts/imx28.dtsi
View File

@ -829,6 +829,19 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
spi3_pins_b: spi3@1 {
reg = <1>;
fsl,pinmux-ids = <
MX28_PAD_SSP3_SCK__SSP3_SCK
MX28_PAD_SSP3_MOSI__SSP3_CMD
MX28_PAD_SSP3_MISO__SSP3_D0
MX28_PAD_SSP3_SS0__SSP3_D3
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
usb0_pins_a: usb0@0 {
reg = <0>;
fsl,pinmux-ids = <
@ -1197,6 +1210,7 @@
interrupts = <92>;
clocks = <&clks 61>;
fsl,usbphy = <&usbphy1>;
dr_mode = "host";
status = "disabled";
};

1
arch/arm/boot/dts/imx35.dtsi
View File

@ -318,6 +318,7 @@
clocks = <&clks 73>;
fsl,usbmisc = <&usbmisc 1>;
fsl,usbphy = <&usbphy1>;
dr_mode = "host";
status = "disabled";
};

3
arch/arm/boot/dts/imx50.dtsi
View File

@ -197,6 +197,7 @@
reg = <0x53f80200 0x0200>;
interrupts = <14>;
clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
dr_mode = "host";
status = "disabled";
};
@ -205,6 +206,7 @@
reg = <0x53f80400 0x0200>;
interrupts = <16>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
dr_mode = "host";
status = "disabled";
};
@ -213,6 +215,7 @@
reg = <0x53f80600 0x0200>;
interrupts = <17>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
dr_mode = "host";
status = "disabled";
};

3
arch/arm/boot/dts/imx51.dtsi
View File

@ -265,6 +265,7 @@
interrupts = <14>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 1>;
dr_mode = "host";
status = "disabled";
};
@ -274,6 +275,7 @@
interrupts = <16>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 2>;
dr_mode = "host";
status = "disabled";
};
@ -283,6 +285,7 @@
interrupts = <17>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 3>;
dr_mode = "host";
status = "disabled";
};

3
arch/arm/boot/dts/imx53.dtsi
View File

@ -309,6 +309,7 @@
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 1>;
fsl,usbphy = <&usbphy1>;
dr_mode = "host";
status = "disabled";
};
@ -318,6 +319,7 @@
interrupts = <16>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 2>;
dr_mode = "host";
status = "disabled";
};
@ -327,6 +329,7 @@
interrupts = <17>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 3>;
dr_mode = "host";
status = "disabled";
};

4
arch/arm/boot/dts/imx6dl-aristainetos_4.dts
View File

@ -83,3 +83,7 @@
&ipu1_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&pwm1 {
status = "okay";
};

4
arch/arm/boot/dts/imx6dl-aristainetos_7.dts
View File

@ -72,3 +72,7 @@
&ipu1_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&pwm3 {
status = "okay";
};

38
arch/arm/boot/dts/imx6dl-cubox-i.dts
View File

@ -1,5 +1,43 @@
/*
* Copyright (C) 2014 Russell King
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;

38
arch/arm/boot/dts/imx6dl-hummingboard.dts
View File

@ -1,6 +1,44 @@
/*
* Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
* Based on dt work by Russell King
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;

38
arch/arm/boot/dts/imx6q-cubox-i.dts
View File

@ -1,5 +1,43 @@
/*
* Copyright (C) 2014 Russell King
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;

38
arch/arm/boot/dts/imx6q-hummingboard.dts
View File

@ -1,6 +1,44 @@
/*
* Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
* Based on dt work by Russell King
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;

20
arch/arm/boot/dts/imx6q.dtsi
View File

@ -294,19 +294,21 @@
};
&mipi_dsi {
port@2 {
reg = <2>;
ports {
port@2 {
reg = <2>;
mipi_mux_2: endpoint {
remote-endpoint = <&ipu2_di0_mipi>;
mipi_mux_2: endpoint {
remote-endpoint = <&ipu2_di0_mipi>;
};
};
};
port@3 {
reg = <3>;
port@3 {
reg = <3>;
mipi_mux_3: endpoint {
remote-endpoint = <&ipu2_di1_mipi>;
mipi_mux_3: endpoint {
remote-endpoint = <&ipu2_di1_mipi>;
};
};
};
};

62
arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
View File

@ -1,8 +1,48 @@
/*
* Copyright (C) 2014 Russell King
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "imx6qdl-microsom.dtsi"
#include "imx6qdl-microsom-ar8035.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
/ {
ir_recv: ir-receiver {
@ -66,6 +106,18 @@
spdif-controller = <&spdif>;
spdif-out;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&pinctrl_gpio_key>;
pinctrl-names = "default";
button_0 {
label = "Button 0";
gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
};
};
&hdmi {
@ -170,9 +222,19 @@
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
>;
};
pinctrl_gpio_key: gpio-key {
fsl,pins = <
MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x17059
>;
};
};
};
&pwm1 {
status = "okay";
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cubox_i_spdif>;

101
arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
View File

@ -1,5 +1,43 @@
/*
* Copyright (C) 2013,2014 Russell King
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "imx6qdl-microsom.dtsi"
#include "imx6qdl-microsom-ar8035.dtsi"
@ -50,6 +88,19 @@
};
};
sound-sgtl5000 {
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
compatible = "fsl,imx-audio-sgtl5000";
model = "On-board Codec";
mux-ext-port = <5>;
mux-int-port = <1>;
ssi-controller = <&ssi1>;
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "On-board SPDIF";
@ -59,6 +110,10 @@
};
};
&audmux {
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
@ -75,16 +130,24 @@
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
/*
* Not fitted on Carrier-1 board... yet
status = "okay";
/* Pro baseboard model */
rtc: pcf8523@68 {
compatible = "nxp,pcf8523";
reg = <0x68>;
};
*/
/* Pro baseboard model */
sgtl5000: sgtl5000@0a {
clocks = <&clks IMX6QDL_CLK_CKO>;
compatible = "fsl,sgtl5000";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_sgtl5000>;
reg = <0x0a>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
};
};
&i2c2 {
@ -129,6 +192,20 @@
>;
};
pinctrl_hummingboard_pwm1: pwm1grp {
fsl,pins = <MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1>;
};
pinctrl_hummingboard_sgtl5000: hummingboard-sgtl5000 {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0
MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
>;
};
pinctrl_hummingboard_spdif: hummingboard-spdif {
fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
};
@ -168,12 +245,28 @@
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_pwm1>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
status = "okay";
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_spdif>;
status = "okay";
};
&ssi1 {
fsl,mode = "i2s-slave";
status = "okay";
};
&usbh1 {
disable-over-current;
vbus-supply = <&reg_usbh1_vbus>;

38
arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
View File

@ -3,6 +3,44 @@
*
* This describes the hookup for an AR8035 to the iMX6 on the SolidRun
* MicroSOM.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
&fec {
pinctrl-names = "default";

38
arch/arm/boot/dts/imx6qdl-microsom.dtsi
View File

@ -1,5 +1,43 @@
/*
* Copyright (C) 2013,2014 Russell King
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
&iomuxc {

35
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
View File

@ -182,6 +182,34 @@
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
status = "okay";
max7310_a: gpio@30 {
compatible = "maxim,max7310";
reg = <0x30>;
gpio-controller;
#gpio-cells = <2>;
};
max7310_b: gpio@32 {
compatible = "maxim,max7310";
reg = <0x32>;
gpio-controller;
#gpio-cells = <2>;
};
max7310_c: gpio@34 {
compatible = "maxim,max7310";
reg = <0x34>;
gpio-controller;
#gpio-cells = <2>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
@ -265,6 +293,13 @@
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_pwm3: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1

49
arch/arm/boot/dts/imx6qdl.dtsi
View File

@ -53,6 +53,7 @@
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
interrupt-parent = <&intc>;
};
clocks {
@ -82,7 +83,7 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
interrupt-parent = <&gpc>;
ranges;
dma_apbh: dma-apbh@00110000 {
@ -122,6 +123,7 @@
compatible = "arm,cortex-a9-twd-timer";
reg = <0x00a00600 0x20>;
interrupts = <1 13 0xf01>;
interrupt-parent = <&intc>;
clocks = <&clks IMX6QDL_CLK_TWD>;
};
@ -357,6 +359,7 @@
clocks = <&clks IMX6QDL_CLK_IPG>,
<&clks IMX6QDL_CLK_PWM1>;
clock-names = "ipg", "per";
status = "disabled";
};
pwm2: pwm@02084000 {
@ -367,6 +370,7 @@
clocks = <&clks IMX6QDL_CLK_IPG>,
<&clks IMX6QDL_CLK_PWM2>;
clock-names = "ipg", "per";
status = "disabled";
};
pwm3: pwm@02088000 {
@ -377,6 +381,7 @@
clocks = <&clks IMX6QDL_CLK_IPG>,
<&clks IMX6QDL_CLK_PWM3>;
clock-names = "ipg", "per";
status = "disabled";
};
pwm4: pwm@0208c000 {
@ -387,6 +392,7 @@
clocks = <&clks IMX6QDL_CLK_IPG>,
<&clks IMX6QDL_CLK_PWM4>;
clock-names = "ipg", "per";
status = "disabled";
};
can1: flexcan@02090000 {
@ -598,7 +604,7 @@
regulator-name = "vddpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
regulator-enable-ramp-delay = <150>;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <9>;
anatop-vol-bit-width = <5>;
@ -658,7 +664,7 @@
#size-cells = <1>;
ranges = <0 0x020cc000 0x4000>;
snvs-rtc-lp@34 {
snvs_rtc: snvs-rtc-lp@34 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
reg = <0x34 0x58>;
interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
@ -693,8 +699,19 @@
gpc: gpc@020dc000 {
compatible = "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
<0 90 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
pu-supply = <&reg_pu>;
clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
<&clks IMX6QDL_CLK_GPU3D_SHADER>,
<&clks IMX6QDL_CLK_GPU2D_CORE>,
<&clks IMX6QDL_CLK_GPU2D_AXI>,
<&clks IMX6QDL_CLK_OPENVG_AXI>,
<&clks IMX6QDL_CLK_VPU_AXI>;
#power-domain-cells = <1>;
};
gpr: iomuxc-gpr@020e0000 {
@ -845,6 +862,7 @@
clocks = <&clks IMX6QDL_CLK_USBOH3>;
fsl,usbphy = <&usbphy2>;
fsl,usbmisc = <&usbmisc 1>;
dr_mode = "host";
status = "disabled";
};
@ -854,6 +872,7 @@
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_USBOH3>;
fsl,usbmisc = <&usbmisc 2>;
dr_mode = "host";
status = "disabled";
};
@ -863,6 +882,7 @@
interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_USBOH3>;
fsl,usbmisc = <&usbmisc 3>;
dr_mode = "host";
status = "disabled";
};
@ -1022,19 +1042,24 @@
reg = <0x021e0000 0x4000>;
status = "disabled";
port@0 {
reg = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
mipi_mux_0: endpoint {
remote-endpoint = <&ipu1_di0_mipi>;
port@0 {
reg = <0>;
mipi_mux_0: endpoint {
remote-endpoint = <&ipu1_di0_mipi>;
};
};
};
port@1 {
reg = <1>;
port@1 {
reg = <1>;
mipi_mux_1: endpoint {
remote-endpoint = <&ipu1_di1_mipi>;
mipi_mux_1: endpoint {
remote-endpoint = <&ipu1_di1_mipi>;
};
};
};
};

262
arch/arm/boot/dts/imx6sl-warp.dts Normal file
View File

@ -0,0 +1,262 @@
/*
* Copyright 2014, 2015 O.S. Systems Software LTDA.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6sl.dtsi"
/ {
model = "WaRP Board";
compatible = "warp,imx6sl-warp", "fsl,imx6sl";
memory {
reg = <0x80000000 0x20000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb_otg1_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 0 0>;
enable-active-high;
};
reg_usb_otg2_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 2 0>;
enable-active-high;
};
reg_1p8v: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
usdhc3_pwrseq: usdhc3_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */
<&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */
<&gpio4 4 GPIO_ACTIVE_LOW>, /* BT_WAKE */
<&gpio4 6 GPIO_ACTIVE_LOW>; /* BT_RST_N */
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usbotg2 {
vbus-supply = <&reg_usb_otg2_vbus>;
disable-over-current;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <4>;
non-removable;
keep-power-in-suspend;
enable-sdio-wakeup;
mmc-pwrseq = <&usdhc3_pwrseq>;
status = "okay";
};
&iomuxc {
imx6sl-warp {
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x41b0b1
MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x41b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6SL_PAD_EPDC_D12__UART2_RX_DATA 0x41b0b1
MX6SL_PAD_EPDC_D13__UART2_TX_DATA 0x41b0b1
MX6SL_PAD_EPDC_D14__UART2_RTS_B 0x4130B1
MX6SL_PAD_EPDC_D15__UART2_CTS_B 0x4130B1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x41b0b1
MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x41b0b1
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059
MX6SL_PAD_SD2_CLK__SD2_CLK 0x410059
MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x417059
MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x417059
MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x417059
MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x417059
MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x417059
MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x417059
MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x417059
MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x417059
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170b9
MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100b9
MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170b9
MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170b9
MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170b9
MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170b9
MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170b9
MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170b9
MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170b9
MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170f9
MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100f9
MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170f9
MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170f9
MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170f9
MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170f9
MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170f9
MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170f9
MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170f9
MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170f9
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6SL_PAD_SD3_CMD__SD3_CMD 0x417059
MX6SL_PAD_SD3_CLK__SD3_CLK 0x410059
MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x417059
MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x417059
MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x417059
MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x417059
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170b9
MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100b9
MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170b9
MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170b9
MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170b9
MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170f9
MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100f9
MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170f9
MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170f9
MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170f9
MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170f9
>;
};
};
};

13
arch/arm/boot/dts/imx6sl.dtsi
View File

@ -72,6 +72,7 @@
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
interrupt-parent = <&intc>;
};
clocks {
@ -95,7 +96,7 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
interrupt-parent = <&gpc>;
ranges;
ocram: sram@00900000 {
@ -568,7 +569,7 @@
#size-cells = <1>;
ranges = <0 0x020cc000 0x4000>;
snvs-rtc-lp@34 {
snvs_rtc: snvs-rtc-lp@34 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
reg = <0x34 0x58>;
interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
@ -603,7 +604,14 @@
gpc: gpc@020dc000 {
compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
pu-supply = <&reg_pu>;
clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
<&clks IMX6SL_CLK_GPU2D_PODF>;
#power-domain-cells = <1>;
};
gpr: iomuxc-gpr@020e0000 {
@ -699,6 +707,7 @@
interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_USBOH3>;
fsl,usbmisc = <&usbmisc 2>;
dr_mode = "host";
status = "disabled";
};

143
arch/arm/boot/dts/imx6sx-sdb-reva.dts Normal file
View File

@ -0,0 +1,143 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6sx-sdb.dtsi"
/ {
model = "Freescale i.MX6 SoloX SDB RevA Board";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pfuze100@08 {
compatible = "fsl,pfuze100";
reg = <0x08>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw3b_reg: sw3b {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
&qspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi2>;
status = "okay";
flash0: s25fl128s@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25fl128s";
spi-max-frequency = <66000000>;
};
flash1: s25fl128s@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25fl128s";
spi-max-frequency = <66000000>;
};
};

609
arch/arm/boot/dts/imx6sx-sdb.dts
View File

@ -1,197 +1,40 @@
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6sx.dtsi"
#include "imx6sx-sdb.dtsi"
/ {
model = "Freescale i.MX6 SoloX SDB Board";
compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
chosen {
stdout-path = &uart1;
};
memory {
reg = <0x80000000 0x40000000>;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
volume-up {
label = "Volume Up";
gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
volume-down {
label = "Volume Down";
gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vcc_sd3: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_vcc_sd3>;
regulator-name = "VCC_SD3";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg1_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg2_vbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg2>;
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_psu_5v: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "PSU-5V0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_lcd_3v3: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "lcd-3v3";
gpio = <&gpio3 27 0>;
enable-active-high;
};
reg_peri_3v3: regulator@5 {
compatible = "regulator-fixed";
reg = <5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_peri_3v3>;
regulator-name = "peri_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_enet_3v3: regulator@6 {
compatible = "regulator-fixed";
reg = <6>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_3v3>;
regulator-name = "enet_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
};
};
sound {
compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <6>;
};
model = "Freescale i.MX6 SoloX SDB RevB Board";
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-supply = <&reg_enet_3v3>;
phy-mode = "rgmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
reg = <1>;
};
ethphy2: ethernet-phy@2 {
reg = <2>;
};
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rgmii";
phy-handle = <&ethphy2>;
status = "okay";
&cpu0 {
operating-points = <
/* kHz uV */
996000 1250000
792000 1175000
396000 1175000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC uV */
996000 1250000
792000 1175000
396000 1175000
>;
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pfuze100@08 {
compatible = "fsl,pfuze100";
compatible = "fsl,pfuze200";
reg = <0x08>;
regulators {
@ -203,14 +46,6 @@
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
@ -232,11 +67,6 @@
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
@ -292,401 +122,24 @@
};
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
codec: wm8962@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clks IMX6SX_CLK_AUDIO>;
DCVDD-supply = <&vgen4_reg>;
DBVDD-supply = <&vgen4_reg>;
AVDD-supply = <&vgen4_reg>;
CPVDD-supply = <&vgen4_reg>;
MICVDD-supply = <&vgen3_reg>;
PLLVDD-supply = <&vgen4_reg>;
SPKVDD1-supply = <&reg_psu_5v>;
SPKVDD2-supply = <&reg_psu_5v>;
};
};
&lcdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
lcd-supply = <&reg_lcd_3v3>;
display = <&display0>;
status = "okay";
display0: display0 {
bits-per-pixel = <16>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <33500000>;
hactive = <800>;
vactive = <480>;
hback-porch = <89>;
hfront-porch = <164>;
vback-porch = <23>;
vfront-porch = <10>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&snvs_poweroff {
status = "okay";
};
&qspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi2>;
status = "okay";
flash0: s25fl128s@0 {
flash0: n25q256a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a";
spi-max-frequency = <29000000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25fl128s";
spi-max-frequency = <66000000>;
};
flash1: s25fl128s@1 {
flash1: n25q256a@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a";
spi-max-frequency = <29000000>;
reg = <1>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25fl128s";
spi-max-frequency = <66000000>;
};
};
&ssi2 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart5 { /* for bluetooth */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
fsl,uart-has-rtscts;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1_id>;
status = "okay";
};
&usbotg2 {
vbus-supply = <&reg_usb_otg2_vbus>;
dr_mode = "host";
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
non-removable;
no-1-8-v;
keep-power-in-suspend;
enable-sdio-wakeup;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
keep-power-in-suspend;
enable-sdio-wakeup;
vmmc-supply = <&vcc_sd3>;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&iomuxc {
imx6x-sdb {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0
MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0
MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0
MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0
MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
>;
};
pinctrl_enet_3v3: enet3v3grp {
fsl,pins = <
MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
>;
};
pinctrl_gpio_keys: gpio_keysgrp {
fsl,pins = <
MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
>;
};
pinctrl_lcd: lcdgrp {
fsl,pins = <
MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
>;
};
pinctrl_peri_3v3: peri3v3grp {
fsl,pins = <
MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
>;
};
pinctrl_pwm3: pwm3grp-1 {
fsl,pins = <
MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
>;
};
pinctrl_qspi2: qspi2grp {
fsl,pins = <
MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1
MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1
MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1
MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1
MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1
MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1
MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1
MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1
MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1
MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1
MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1
MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1
>;
};
pinctrl_vcc_sd3: vccsd3grp {
fsl,pins = <
MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
>;
};
pinctrl_usb_otg1: usbotg1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
>;
};
pinctrl_usb_otg1_id: usbotg1idgrp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
>;
};
pinctrl_usb_otg2: usbot2ggrp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
>;
};
};
};

562
arch/arm/boot/dts/imx6sx-sdb.dtsi Normal file
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@ -0,0 +1,562 @@
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6sx.dtsi"
/ {
model = "Freescale i.MX6 SoloX SDB Board";
compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
chosen {
stdout-path = &uart1;
};
memory {
reg = <0x80000000 0x40000000>;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
volume-up {
label = "Volume Up";
gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
volume-down {
label = "Volume Down";
gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vcc_sd3: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_vcc_sd3>;
regulator-name = "VCC_SD3";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg1_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg2_vbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg2>;
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_psu_5v: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "PSU-5V0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_lcd_3v3: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "lcd-3v3";
gpio = <&gpio3 27 0>;
enable-active-high;
};
reg_peri_3v3: regulator@5 {
compatible = "regulator-fixed";
reg = <5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_peri_3v3>;
regulator-name = "peri_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_enet_3v3: regulator@6 {
compatible = "regulator-fixed";
reg = <6>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_3v3>;
regulator-name = "enet_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
};
};
sound {
compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <6>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-supply = <&reg_enet_3v3>;
phy-mode = "rgmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
reg = <1>;
};
ethphy2: ethernet-phy@2 {
reg = <2>;
};
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rgmii";
phy-handle = <&ethphy2>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
codec: wm8962@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clks IMX6SX_CLK_AUDIO>;
DCVDD-supply = <&vgen4_reg>;
DBVDD-supply = <&vgen4_reg>;
AVDD-supply = <&vgen4_reg>;
CPVDD-supply = <&vgen4_reg>;
MICVDD-supply = <&vgen3_reg>;
PLLVDD-supply = <&vgen4_reg>;
SPKVDD1-supply = <&reg_psu_5v>;
SPKVDD2-supply = <&reg_psu_5v>;
};
};
&lcdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
lcd-supply = <&reg_lcd_3v3>;
display = <&display0>;
status = "okay";
display0: display0 {
bits-per-pixel = <16>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <33500000>;
hactive = <800>;
vactive = <480>;
hback-porch = <89>;
hfront-porch = <164>;
vback-porch = <23>;
vfront-porch = <10>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&snvs_poweroff {
status = "okay";
};
&ssi2 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart5 { /* for bluetooth */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
fsl,uart-has-rtscts;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1_id>;
status = "okay";
};
&usbotg2 {
vbus-supply = <&reg_usb_otg2_vbus>;
dr_mode = "host";
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
non-removable;
no-1-8-v;
keep-power-in-suspend;
enable-sdio-wakeup;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
keep-power-in-suspend;
enable-sdio-wakeup;
vmmc-supply = <&vcc_sd3>;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&iomuxc {
imx6x-sdb {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0
MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0
MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0
MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0
MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
>;
};
pinctrl_enet_3v3: enet3v3grp {
fsl,pins = <
MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
>;
};
pinctrl_gpio_keys: gpio_keysgrp {
fsl,pins = <
MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
>;
};
pinctrl_lcd: lcdgrp {
fsl,pins = <
MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
>;
};
pinctrl_peri_3v3: peri3v3grp {
fsl,pins = <
MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
>;
};
pinctrl_pwm3: pwm3grp-1 {
fsl,pins = <
MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
>;
};
pinctrl_qspi2: qspi2grp {
fsl,pins = <
MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1
MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1
MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1
MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1
MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1
MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1
MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1
MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1
MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1
MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1
MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1
MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1
>;
};
pinctrl_vcc_sd3: vccsd3grp {
fsl,pins = <
MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
>;
};
pinctrl_usb_otg1: usbotg1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
>;
};
pinctrl_usb_otg1_id: usbotg1idgrp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
>;
};
pinctrl_usb_otg2: usbot2ggrp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
>;
};
};
};

9
arch/arm/boot/dts/imx6sx.dtsi
View File

@ -88,6 +88,7 @@
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
interrupt-parent = <&intc>;
};
clocks {
@ -131,7 +132,7 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
interrupt-parent = <&gpc>;
ranges;
pmu {
@ -666,7 +667,7 @@
#size-cells = <1>;
ranges = <0 0x020cc000 0x4000>;
snvs-rtc-lp@34 {
snvs_rtc: snvs-rtc-lp@34 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
reg = <0x34 0x58>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
@ -700,7 +701,10 @@
gpc: gpc@020dc000 {
compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
};
iomuxc: iomuxc@020e0000 {
@ -763,6 +767,7 @@
fsl,usbmisc = <&usbmisc 2>;
phy_type = "hsic";
fsl,anatop = <&anatop>;
dr_mode = "host";
status = "disabled";
};

31
arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
View File

@ -12,6 +12,12 @@
bootargs = "console=ttyLP0,115200";
};
clk16m: clk16m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <16000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
@ -47,6 +53,21 @@
status = "okay";
};
&dspi1 {
status = "okay";
mcp2515can: can@0 {
compatible = "microchip,mcp2515";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_int>;
reg = <0>;
clocks = <&clk16m>;
spi-max-frequency = <10000000>;
interrupt-parent = <&gpio1>;
interrupts = <11 GPIO_ACTIVE_LOW>;
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
@ -94,3 +115,13 @@
&usbh1 {
vbus-supply = <&usbh_vbus_reg>;
};
&iomuxc {
vf610-colibri {
pinctrl_can_int: can_int {
fsl,pins = <
VF610_PAD_PTB21__GPIO_43 0x22ed
>;
};
};
};

15
arch/arm/boot/dts/vf-colibri.dtsi
View File

@ -23,6 +23,12 @@
status = "okay";
};
&dspi1 {
bus-num = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dspi1>;
};
&edma0 {
status = "okay";
};
@ -107,6 +113,15 @@
>;
};
pinctrl_dspi1: dspi1grp {
fsl,pins = <
VF610_PAD_PTD5__DSPI1_CS0 0x33e2
VF610_PAD_PTD6__DSPI1_SIN 0x33e1
VF610_PAD_PTD7__DSPI1_SOUT 0x33e2
VF610_PAD_PTD8__DSPI1_SCK 0x33e2
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
VF610_PAD_PTA24__ESDHC1_CLK 0x31ef

137
arch/arm/boot/dts/vf500.dtsi
View File

@ -24,14 +24,13 @@
};
soc {
interrupt-parent = <&intc>;
aips-bus@40000000 {
intc: interrupt-controller@40002000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
interrupt-parent = <&intc>;
reg = <0x40003000 0x1000>,
<0x40002100 0x100>;
};
@ -40,145 +39,17 @@
compatible = "arm,cortex-a9-global-timer";
reg = <0x40002200 0x20>;
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
clocks = <&clks VF610_CLK_PLATFORM_BUS>;
};
};
};
};
&adc0 {
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
};
&adc1 {
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
};
&can0 {
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
};
&can1 {
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
};
&dspi0 {
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
};
&edma0 {
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma-tx", "edma-err";
};
&edma1 {
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma-tx", "edma-err";
};
&esdhc1 {
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
};
&fec0 {
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
};
&fec1 {
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
};
&ftm {
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
};
&gpio0 {
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
};
&gpio1 {
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
};
&gpio2 {
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
};
&gpio3 {
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
};
&gpio4 {
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
};
&i2c0 {
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
};
&pit {
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
};
&qspi0 {
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
};
&sai2 {
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
};
&snvsrtc {
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
};
&src {
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
};
&uart0 {
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
};
&uart1 {
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
};
&uart2 {
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
};
&uart3 {
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
};
&uart4 {
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
};
&uart5 {
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
};
&usbdev0 {
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
};
&usbh1 {
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
};
&usbphy0 {
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
};
&usbphy1 {
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
&mscm_ir {
interrupt-parent = <&intc>;
};
&wdoga5 {
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};

64
arch/arm/boot/dts/vfxxx.dtsi
View File

@ -54,6 +54,7 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&mscm_ir>;
ranges;
aips0: aips-bus@40000000 {
@ -62,6 +63,19 @@
#size-cells = <1>;
ranges;
mscm_cpucfg: cpucfg@40001000 {
compatible = "fsl,vf610-mscm-cpucfg", "syscon";
reg = <0x40001000 0x800>;
};
mscm_ir: interrupt-controller@40001800 {
compatible = "fsl,vf610-mscm-ir";
reg = <0x40001800 0x400>;
fsl,cpucfg = <&mscm_cpucfg>;
interrupt-controller;
#interrupt-cells = <2>;
};
edma0: dma-controller@40018000 {
#dma-cells = <2>;
compatible = "fsl,vf610-edma";
@ -69,6 +83,9 @@
<0x40024000 0x1000>,
<0x40025000 0x1000>;
dma-channels = <32>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
<9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma-tx", "edma-err";
clock-names = "dmamux0", "dmamux1";
clocks = <&clks VF610_CLK_DMAMUX0>,
<&clks VF610_CLK_DMAMUX1>;
@ -78,6 +95,7 @@
can0: flexcan@40020000 {
compatible = "fsl,vf610-flexcan";
reg = <0x40020000 0x4000>;
interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_FLEXCAN0>,
<&clks VF610_CLK_FLEXCAN0>;
clock-names = "ipg", "per";
@ -87,6 +105,7 @@
uart0: serial@40027000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40027000 0x1000>;
interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART0>;
clock-names = "ipg";
dmas = <&edma0 0 2>,
@ -98,6 +117,7 @@
uart1: serial@40028000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40028000 0x1000>;
interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART1>;
clock-names = "ipg";
dmas = <&edma0 0 4>,
@ -109,6 +129,7 @@
uart2: serial@40029000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40029000 0x1000>;
interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART2>;
clock-names = "ipg";
dmas = <&edma0 0 6>,
@ -120,6 +141,7 @@
uart3: serial@4002a000 {
compatible = "fsl,vf610-lpuart";
reg = <0x4002a000 0x1000>;
interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART3>;
clock-names = "ipg";
dmas = <&edma0 0 8>,
@ -133,15 +155,29 @@
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
reg = <0x4002c000 0x1000>;
interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_DSPI0>;
clock-names = "dspi";
spi-num-chipselects = <5>;
status = "disabled";
};
dspi1: dspi1@4002d000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
reg = <0x4002d000 0x1000>;
interrupts = <68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_DSPI1>;
clock-names = "dspi";
spi-num-chipselects = <5>;
status = "disabled";
};
sai2: sai@40031000 {
compatible = "fsl,vf610-sai";
reg = <0x40031000 0x1000>;
interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_SAI2>;
clock-names = "sai";
dma-names = "tx", "rx";
@ -153,6 +189,7 @@
pit: pit@40037000 {
compatible = "fsl,vf610-pit";
reg = <0x40037000 0x1000>;
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_PIT>;
clock-names = "pit";
};
@ -186,6 +223,7 @@
adc0: adc@4003b000 {
compatible = "fsl,vf610-adc";
reg = <0x4003b000 0x1000>;
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ADC0>;
clock-names = "adc";
status = "disabled";
@ -194,6 +232,7 @@
wdoga5: wdog@4003e000 {
compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
reg = <0x4003e000 0x1000>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_WDT>;
clock-names = "wdog";
status = "disabled";
@ -204,6 +243,7 @@
#size-cells = <0>;
compatible = "fsl,vf610-qspi";
reg = <0x40044000 0x1000>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_QSPI0_EN>,
<&clks VF610_CLK_QSPI0>;
clock-names = "qspi_en", "qspi";
@ -213,7 +253,6 @@
iomuxc: iomuxc@40048000 {
compatible = "fsl,vf610-iomuxc";
reg = <0x40048000 0x1000>;
#gpio-range-cells = <3>;
};
gpio0: gpio@40049000 {
@ -221,6 +260,7 @@
reg = <0x40049000 0x1000 0x400ff000 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 0 32>;
@ -231,6 +271,7 @@
reg = <0x4004a000 0x1000 0x400ff040 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 32 32>;
@ -241,6 +282,7 @@
reg = <0x4004b000 0x1000 0x400ff080 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 64 32>;
@ -251,6 +293,7 @@
reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 96 32>;
@ -261,6 +304,7 @@
reg = <0x4004d000 0x1000 0x400ff100 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 128 7>;
@ -274,6 +318,7 @@
usbphy0: usbphy@40050800 {
compatible = "fsl,vf610-usbphy";
reg = <0x40050800 0x400>;
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBPHY0>;
fsl,anatop = <&anatop>;
status = "disabled";
@ -282,6 +327,7 @@
usbphy1: usbphy@40050c00 {
compatible = "fsl,vf610-usbphy";
reg = <0x40050c00 0x400>;
interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBPHY1>;
fsl,anatop = <&anatop>;
status = "disabled";
@ -292,6 +338,7 @@
#size-cells = <0>;
compatible = "fsl,vf610-i2c";
reg = <0x40066000 0x1000>;
interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_I2C0>;
clock-names = "ipg";
dmas = <&edma0 0 50>,
@ -311,6 +358,7 @@
usbdev0: usb@40034000 {
compatible = "fsl,vf610-usb", "fsl,imx27-usb";
reg = <0x40034000 0x800>;
interrupts = <75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBC0>;
fsl,usbphy = <&usbphy0>;
fsl,usbmisc = <&usbmisc0 0>;
@ -329,6 +377,7 @@
src: src@4006e000 {
compatible = "fsl,vf610-src", "syscon";
reg = <0x4006e000 0x1000>;
interrupts = <96 IRQ_TYPE_LEVEL_HIGH>;
};
};
@ -345,6 +394,9 @@
<0x400a1000 0x1000>,
<0x400a2000 0x1000>;
dma-channels = <32>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
<11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma-tx", "edma-err";
clock-names = "dmamux0", "dmamux1";
clocks = <&clks VF610_CLK_DMAMUX2>,
<&clks VF610_CLK_DMAMUX3>;
@ -360,6 +412,7 @@
snvsrtc: snvs-rtc-lp@34 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
reg = <0x34 0x58>;
interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_SNVS>;
clock-names = "snvs-rtc";
};
@ -368,6 +421,7 @@
uart4: serial@400a9000 {
compatible = "fsl,vf610-lpuart";
reg = <0x400a9000 0x1000>;
interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART4>;
clock-names = "ipg";
status = "disabled";
@ -376,6 +430,7 @@
uart5: serial@400aa000 {
compatible = "fsl,vf610-lpuart";
reg = <0x400aa000 0x1000>;
interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART5>;
clock-names = "ipg";
status = "disabled";
@ -384,6 +439,7 @@
adc1: adc@400bb000 {
compatible = "fsl,vf610-adc";
reg = <0x400bb000 0x1000>;
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ADC1>;
clock-names = "adc";
status = "disabled";
@ -392,6 +448,7 @@
esdhc1: esdhc@400b2000 {
compatible = "fsl,imx53-esdhc";
reg = <0x400b2000 0x1000>;
interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_IPG_BUS>,
<&clks VF610_CLK_PLATFORM_BUS>,
<&clks VF610_CLK_ESDHC1>;
@ -402,6 +459,7 @@
usbh1: usb@400b4000 {
compatible = "fsl,vf610-usb", "fsl,imx27-usb";
reg = <0x400b4000 0x800>;
interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBC1>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc1 0>;
@ -420,6 +478,7 @@
ftm: ftm@400b8000 {
compatible = "fsl,ftm-timer";
reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "ftm-evt", "ftm-src",
"ftm-evt-counter-en", "ftm-src-counter-en";
clocks = <&clks VF610_CLK_FTM2>,
@ -432,6 +491,7 @@
fec0: ethernet@400d0000 {
compatible = "fsl,mvf600-fec";
reg = <0x400d0000 0x1000>;
interrupts = <78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ENET0>,
<&clks VF610_CLK_ENET0>,
<&clks VF610_CLK_ENET>;
@ -442,6 +502,7 @@
fec1: ethernet@400d1000 {
compatible = "fsl,mvf600-fec";
reg = <0x400d1000 0x1000>;
interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ENET1>,
<&clks VF610_CLK_ENET1>,
<&clks VF610_CLK_ENET>;
@ -452,6 +513,7 @@
can1: flexcan@400d4000 {
compatible = "fsl,vf610-flexcan";
reg = <0x400d4000 0x4000>;
interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_FLEXCAN1>,
<&clks VF610_CLK_FLEXCAN1>;
clock-names = "ipg", "per";

3
arch/arm/configs/imx_v4_v5_defconfig
View File

@ -24,9 +24,8 @@ CONFIG_ARCH_MXC=y
CONFIG_MACH_SCB9328=y
CONFIG_MACH_APF9328=y
CONFIG_MACH_MX21ADS=y
CONFIG_MACH_MX25_3DS=y
CONFIG_MACH_EUKREA_CPUIMX25SD=y
CONFIG_MACH_IMX25_DT=y
CONFIG_SOC_IMX25=y
CONFIG_MACH_MX27ADS=y
CONFIG_MACH_MX27_3DS=y
CONFIG_MACH_IMX27_VISSTRIM_M10=y

2
arch/arm/configs/multi_v5_defconfig
View File

@ -13,7 +13,7 @@ CONFIG_ARCH_MVEBU=y
CONFIG_MACH_KIRKWOOD=y
CONFIG_MACH_NETXBIG=y
CONFIG_ARCH_MXC=y
CONFIG_MACH_IMX25_DT=y
CONFIG_SOC_IMX25=y
CONFIG_MACH_IMX27_DT=y
CONFIG_ARCH_U300=y
CONFIG_PCI_MVEBU=y

85
arch/arm/mach-imx/Kconfig
View File

@ -21,6 +21,7 @@ config MXC_AVIC
config MXC_DEBUG_BOARD
bool "Enable MXC debug board(for 3-stack)"
depends on MACH_MX27_3DS || MACH_MX31_3DS || MACH_MX35_3DS
help
The debug board is an integral part of the MXC 3-stack(PDK)
platforms, it can be attached or removed from the peripheral
@ -50,6 +51,7 @@ config HAVE_IMX_ANATOP
config HAVE_IMX_GPC
bool
select PM_GENERIC_DOMAINS if PM
config HAVE_IMX_MMDC
bool
@ -77,13 +79,6 @@ config SOC_IMX21
select IMX_HAVE_IOMUX_V1
select MXC_AVIC
config SOC_IMX25
bool
select ARCH_MXC_IOMUX_V3
select CPU_ARM926T
select MXC_AVIC
select PINCTRL_IMX25
config SOC_IMX27
bool
select CPU_ARM926T
@ -149,62 +144,6 @@ config MACH_MX21ADS
Include support for MX21ADS platform. This includes specific
configurations for the board and its peripherals.
comment "MX25 platforms:"
config MACH_MX25_3DS
bool "Support MX25PDK (3DS) Platform"
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMXDI_RTC
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select SOC_IMX25
config MACH_EUKREA_CPUIMX25SD
bool "Support Eukrea CPUIMX25 Platform"
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMXDI_RTC
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select USB_ULPI_VIEWPORT if USB_ULPI
select SOC_IMX25
choice
prompt "Baseboard"
depends on MACH_EUKREA_CPUIMX25SD
default MACH_EUKREA_MBIMXSD25_BASEBOARD
config MACH_EUKREA_MBIMXSD25_BASEBOARD
bool "Eukrea MBIMXSD development board"
select IMX_HAVE_PLATFORM_GPIO_KEYS
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_SPI_IMX
select LEDS_GPIO_REGISTER
help
This adds board specific devices that can be found on Eukrea's
MBIMXSD evaluation board.
endchoice
config MACH_IMX25_DT
bool "Support i.MX25 platforms from device tree"
select SOC_IMX25
help
Include support for Freescale i.MX25 based platforms
using the device tree for discovery
comment "MX27 platforms:"
config MACH_MX27ADS
@ -557,6 +496,20 @@ config MACH_VPR200
endif
if ARCH_MULTI_V5
comment "Device tree only"
config SOC_IMX25
bool "i.MX25 support"
select ARCH_MXC_IOMUX_V3
select CPU_ARM926T
select MXC_AVIC
select PINCTRL_IMX25
help
This enables support for Freescale i.MX25 processor
endif
if ARCH_MULTI_V7
comment "Device tree only"
@ -631,12 +584,14 @@ config SOC_IMX6SX
config SOC_VF610
bool "Vybrid Family VF610 support"
select IRQ_DOMAIN_HIERARCHY
select ARM_GIC
select PINCTRL_VF610
select PL310_ERRATA_769419 if CACHE_L2X0
select SMP_ON_UP if SMP
help
This enable support for Freescale Vybrid VF610 processor.
This enables support for Freescale Vybrid VF610 processor.
choice
prompt "Clocksource for scheduler clock"
@ -666,7 +621,7 @@ config SOC_LS1021A
select ZONE_DMA if ARM_LPAE
help
This enable support for Freescale LS1021A processor.
This enables support for Freescale LS1021A processor.
endif

8
arch/arm/mach-imx/Makefile
View File

@ -3,7 +3,7 @@ obj-y := time.o cpu.o system.o irq-common.o
obj-$(CONFIG_SOC_IMX1) += clk-imx1.o mm-imx1.o
obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o
obj-$(CONFIG_SOC_IMX25) += clk-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
obj-$(CONFIG_SOC_IMX25) += clk-imx25.o cpu-imx25.o mach-imx25.o
obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o
@ -48,12 +48,6 @@ obj-$(CONFIG_MACH_IMX1_DT) += imx1-dt.o
# i.MX21 based machines
obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
# i.MX25 based machines
obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX25SD) += mach-eukrea_cpuimx25.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o
obj-$(CONFIG_MACH_IMX25_DT) += imx25-dt.o
# i.MX27 based machines
obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o

75
arch/arm/mach-imx/clk-imx25.c
View File

@ -30,7 +30,6 @@
#include "clk.h"
#include "common.h"
#include "hardware.h"
#include "mx25.h"
#define CCM_MPCTL 0x00
#define CCM_UPCTL 0x04
@ -239,80 +238,6 @@ static int __init __mx25_clocks_init(unsigned long osc_rate,
return 0;
}
int __init mx25_clocks_init(void)
{
void __iomem *ccm;
ccm = ioremap(MX25_CRM_BASE_ADDR, SZ_16K);
__mx25_clocks_init(24000000, ccm);
clk_register_clkdev(clk[gpt1_ipg], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
/* i.mx25 has the i.mx21 type uart */
clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");
clk_register_clkdev(clk[uart2_ipg], "ipg", "imx21-uart.1");
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.1");
clk_register_clkdev(clk[uart3_ipg], "ipg", "imx21-uart.2");
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.2");
clk_register_clkdev(clk[uart4_ipg], "ipg", "imx21-uart.3");
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.3");
clk_register_clkdev(clk[uart5_ipg], "ipg", "imx21-uart.4");
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.4");
clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.0");
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.1");
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.2");
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
clk_register_clkdev(clk[usbotg_ahb], "ahb", "imx-udc-mx27");
clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
clk_register_clkdev(clk[nfc_ipg_per], NULL, "imx25-nand.0");
/* i.mx25 has the i.mx35 type cspi */
clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0");
clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1");
clk_register_clkdev(clk[cspi3_ipg], NULL, "imx35-cspi.2");
clk_register_clkdev(clk[kpp_ipg], NULL, "imx-keypad");
clk_register_clkdev(clk[tsc_ipg], NULL, "mx25-adc");
clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.0");
clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.1");
clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.2");
clk_register_clkdev(clk[fec_ipg], "ipg", "imx25-fec.0");
clk_register_clkdev(clk[fec_ahb], "ahb", "imx25-fec.0");
clk_register_clkdev(clk[dryice_ipg], NULL, "imxdi_rtc.0");
clk_register_clkdev(clk[lcdc_ipg_per], "per", "imx21-fb.0");
clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx21-fb.0");
clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx21-fb.0");
clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0");
clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0");
clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.1");
clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0");
clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0");
clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0");
clk_register_clkdev(clk[esdhc2_ipg_per], "per", "sdhci-esdhc-imx25.1");
clk_register_clkdev(clk[esdhc2_ipg], "ipg", "sdhci-esdhc-imx25.1");
clk_register_clkdev(clk[esdhc2_ahb], "ahb", "sdhci-esdhc-imx25.1");
clk_register_clkdev(clk[csi_ipg_per], "per", "imx25-camera.0");
clk_register_clkdev(clk[csi_ipg], "ipg", "imx25-camera.0");
clk_register_clkdev(clk[csi_ahb], "ahb", "imx25-camera.0");
clk_register_clkdev(clk[dummy], "audmux", NULL);
clk_register_clkdev(clk[can1_ipg], NULL, "flexcan.0");
clk_register_clkdev(clk[can2_ipg], NULL, "flexcan.1");
/* i.mx25 has the i.mx35 type sdma */
clk_register_clkdev(clk[sdma_ipg], "ipg", "imx35-sdma");
clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma");
clk_register_clkdev(clk[iim_ipg], "iim", NULL);
mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1);
return 0;
}
static void __init mx25_clocks_init_dt(struct device_node *np)
{
struct device_node *refnp;

8
arch/arm/mach-imx/clk-imx6q.c
View File

@ -119,6 +119,7 @@ static unsigned int share_count_asrc;
static unsigned int share_count_ssi1;
static unsigned int share_count_ssi2;
static unsigned int share_count_ssi3;
static unsigned int share_count_mipi_core_cfg;
static void __init imx6q_clocks_init(struct device_node *ccm_node)
{
@ -246,6 +247,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);
clk[IMX6QDL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
clk[IMX6QDL_CLK_VIDEO_27M] = imx_clk_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20);
if (cpu_is_imx6dl()) {
clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
@ -400,7 +402,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "video_27m", base + 0x70, 4);
clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
@ -415,7 +417,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2_shared("hsi_tx", "hsi_tx_podf", base + 0x74, 16, &share_count_mipi_core_cfg);
clk[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg);
clk[IMX6QDL_CLK_MIPI_IPG] = imx_clk_gate2_shared("mipi_ipg", "ipg", base + 0x74, 16, &share_count_mipi_core_cfg);
if (cpu_is_imx6dl())
/*
* The multiplexer and divider of the imx6q clock gpu2d get

7
arch/arm/mach-imx/common.h
View File

@ -23,13 +23,11 @@ struct of_device_id;
void mx1_map_io(void);
void mx21_map_io(void);
void mx25_map_io(void);
void mx27_map_io(void);
void mx31_map_io(void);
void mx35_map_io(void);
void imx1_init_early(void);
void imx21_init_early(void);
void imx25_init_early(void);
void imx27_init_early(void);
void imx31_init_early(void);
void imx35_init_early(void);
@ -37,13 +35,11 @@ void mxc_init_irq(void __iomem *);
void tzic_init_irq(void);
void mx1_init_irq(void);
void mx21_init_irq(void);
void mx25_init_irq(void);
void mx27_init_irq(void);
void mx31_init_irq(void);
void mx35_init_irq(void);
void imx1_soc_init(void);
void imx21_soc_init(void);
void imx25_soc_init(void);
void imx27_soc_init(void);
void imx31_soc_init(void);
void imx35_soc_init(void);
@ -51,7 +47,6 @@ void epit_timer_init(void __iomem *base, int irq);
void mxc_timer_init(void __iomem *, int);
int mx1_clocks_init(unsigned long fref);
int mx21_clocks_init(unsigned long lref, unsigned long fref);
int mx25_clocks_init(void);
int mx27_clocks_init(unsigned long fref);
int mx31_clocks_init(unsigned long fref);
int mx35_clocks_init(void);
@ -71,6 +66,7 @@ unsigned int imx_get_soc_revision(void);
void imx_init_revision_from_anatop(void);
struct device *imx_soc_device_init(void);
void imx6_enable_rbc(bool enable);
void imx_gpc_check_dt(void);
void imx_gpc_set_arm_power_in_lpm(bool power_off);
void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
@ -106,7 +102,6 @@ static inline void imx_scu_map_io(void) {}
static inline void imx_smp_prepare(void) {}
#endif
void imx_src_init(void);
void imx_gpc_init(void);
void imx_gpc_pre_suspend(bool arm_power_off);
void imx_gpc_post_resume(void);
void imx_gpc_mask_all(void);

11
arch/arm/mach-imx/cpu-imx25.c
View File

@ -11,6 +11,8 @@
*/
#include <linux/module.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "iim.h"
#include "hardware.h"
@ -20,8 +22,15 @@ static int mx25_cpu_rev = -1;
static int mx25_read_cpu_rev(void)
{
u32 rev;
void __iomem *iim_base;
struct device_node *np;
np = of_find_compatible_node(NULL, NULL, "fsl,imx25-iim");
iim_base = of_iomap(np, 0);
BUG_ON(!iim_base);
rev = readl(iim_base + MXC_IIMSREV);
iounmap(iim_base);
rev = __raw_readl(MX25_IO_ADDRESS(MX25_IIM_BASE_ADDR + MXC_IIMSREV));
switch (rev) {
case 0x00:
return IMX_CHIP_REVISION_1_0;

85
arch/arm/mach-imx/devices-imx25.h
View File

@ -1,85 +0,0 @@
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include "devices/devices-common.h"
extern const struct imx_fec_data imx25_fec_data;
#define imx25_add_fec(pdata) \
imx_add_fec(&imx25_fec_data, pdata)
extern const struct imx_flexcan_data imx25_flexcan_data[];
#define imx25_add_flexcan(id) \
imx_add_flexcan(&imx25_flexcan_data[id])
#define imx25_add_flexcan0() imx25_add_flexcan(0)
#define imx25_add_flexcan1() imx25_add_flexcan(1)
extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data;
#define imx25_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata)
extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data;
#define imx25_add_imxdi_rtc() \
imx_add_imxdi_rtc(&imx25_imxdi_rtc_data)
extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data;
#define imx25_add_imx2_wdt() \
imx_add_imx2_wdt(&imx25_imx2_wdt_data)
extern const struct imx_imx_fb_data imx25_imx_fb_data;
#define imx25_add_imx_fb(pdata) \
imx_add_imx_fb(&imx25_imx_fb_data, pdata)
extern const struct imx_imx_i2c_data imx25_imx_i2c_data[];
#define imx25_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx25_imx_i2c_data[id], pdata)
#define imx25_add_imx_i2c0(pdata) imx25_add_imx_i2c(0, pdata)
#define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata)
#define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata)
extern const struct imx_imx_keypad_data imx25_imx_keypad_data;
#define imx25_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx25_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx25_imx_ssi_data[];
#define imx25_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata)
extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[];
#define imx25_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx25_imx_uart_data[id], pdata)
#define imx25_add_imx_uart0(pdata) imx25_add_imx_uart(0, pdata)
#define imx25_add_imx_uart1(pdata) imx25_add_imx_uart(1, pdata)
#define imx25_add_imx_uart2(pdata) imx25_add_imx_uart(2, pdata)
#define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata)
#define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata)
extern const struct imx_mx2_camera_data imx25_mx2_camera_data;
#define imx25_add_mx2_camera(pdata) \
imx_add_mx2_camera(&imx25_mx2_camera_data, pdata)
extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data;
#define imx25_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data;
#define imx25_add_mxc_ehci_hs(pdata) \
imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata)
extern const struct imx_mxc_nand_data imx25_mxc_nand_data;
#define imx25_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx25_mxc_nand_data, pdata)
extern const struct imx_sdhci_esdhc_imx_data imx25_sdhci_esdhc_imx_data[];
#define imx25_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata)
extern const struct imx_spi_imx_data imx25_cspi_data[];
#define imx25_add_spi_imx(id, pdata) \
imx_add_spi_imx(&imx25_cspi_data[id], pdata)
#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata)
#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata)
#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata)

3
arch/arm/mach-imx/devices/Kconfig
View File

@ -21,9 +21,6 @@ config IMX_HAVE_PLATFORM_IMX27_CODA
config IMX_HAVE_PLATFORM_IMX2_WDT
bool
config IMX_HAVE_PLATFORM_IMXDI_RTC
bool
config IMX_HAVE_PLATFORM_IMX_FB
bool

1
arch/arm/mach-imx/devices/Makefile
View File

@ -8,7 +8,6 @@ obj-y += platform-gpio-mxc.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX27_CODA) += platform-imx27-coda.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o
obj-y += platform-imx-dma.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o

5
arch/arm/mach-imx/devices/platform-fec.c
View File

@ -19,11 +19,6 @@
.irq = soc ## _INT_FEC, \
}
#ifdef CONFIG_SOC_IMX25
const struct imx_fec_data imx25_fec_data __initconst =
imx_fec_data_entry_single(MX25, "imx25-fec");
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_fec_data imx27_fec_data __initconst =
imx_fec_data_entry_single(MX27, "imx27-fec");

5
arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
View File

@ -18,11 +18,6 @@
.irq = soc ## _INT_USB_OTG, \
}
#ifdef CONFIG_SOC_IMX25
const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst =
imx_fsl_usb2_udc_data_entry_single(MX25, "imx-udc-mx27");
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst =
imx_fsl_usb2_udc_data_entry_single(MX27, "imx-udc-mx27");

5
arch/arm/mach-imx/devices/platform-imx-fb.c
View File

@ -29,11 +29,6 @@ const struct imx_imx_fb_data imx21_imx_fb_data __initconst =
imx_imx_fb_data_entry_single(MX21, "imx21-fb", SZ_4K);
#endif /* ifdef CONFIG_SOC_IMX21 */
#ifdef CONFIG_SOC_IMX25
const struct imx_imx_fb_data imx25_imx_fb_data __initconst =
imx_imx_fb_data_entry_single(MX25, "imx21-fb", SZ_16K);
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_imx_fb_data imx27_imx_fb_data __initconst =
imx_imx_fb_data_entry_single(MX27, "imx21-fb", SZ_4K);

10
arch/arm/mach-imx/devices/platform-imx-i2c.c
View File

@ -31,16 +31,6 @@ const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst =
imx_imx_i2c_data_entry_single(MX21, "imx21-i2c", 0, , SZ_4K);
#endif /* ifdef CONFIG_SOC_IMX21 */
#ifdef CONFIG_SOC_IMX25
const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = {
#define imx25_imx_i2c_data_entry(_id, _hwid) \
imx_imx_i2c_data_entry(MX25, "imx21-i2c", _id, _hwid, SZ_16K)
imx25_imx_i2c_data_entry(0, 1),
imx25_imx_i2c_data_entry(1, 2),
imx25_imx_i2c_data_entry(2, 3),
};
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = {
#define imx27_imx_i2c_data_entry(_id, _hwid) \

5
arch/arm/mach-imx/devices/platform-imx-keypad.c
View File

@ -21,11 +21,6 @@ const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst =
imx_imx_keypad_data_entry_single(MX21, SZ_16);
#endif /* ifdef CONFIG_SOC_IMX21 */
#ifdef CONFIG_SOC_IMX25
const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst =
imx_imx_keypad_data_entry_single(MX25, SZ_16K);
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst =
imx_imx_keypad_data_entry_single(MX27, SZ_16);

9
arch/arm/mach-imx/devices/platform-imx-ssi.c
View File

@ -30,15 +30,6 @@ const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = {
};
#endif /* ifdef CONFIG_SOC_IMX21 */
#ifdef CONFIG_SOC_IMX25
const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = {
#define imx25_imx_ssi_data_entry(_id, _hwid) \
imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K)
imx25_imx_ssi_data_entry(0, 1),
imx25_imx_ssi_data_entry(1, 2),
};
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = {
#define imx27_imx_ssi_data_entry(_id, _hwid) \

12
arch/arm/mach-imx/devices/platform-imx-uart.c
View File

@ -47,18 +47,6 @@ const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = {
};
#endif
#ifdef CONFIG_SOC_IMX25
const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = {
#define imx25_imx_uart_data_entry(_id, _hwid) \
imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K)
imx25_imx_uart_data_entry(0, 1),
imx25_imx_uart_data_entry(1, 2),
imx25_imx_uart_data_entry(2, 3),
imx25_imx_uart_data_entry(3, 4),
imx25_imx_uart_data_entry(4, 5),
};
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = {
#define imx27_imx_uart_data_entry(_id, _hwid) \

5
arch/arm/mach-imx/devices/platform-imx2-wdt.c
View File

@ -25,11 +25,6 @@ const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst =
imx_imx2_wdt_data_entry_single(MX21, 0, , SZ_4K);
#endif /* ifdef CONFIG_SOC_IMX21 */
#ifdef CONFIG_SOC_IMX25
const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst =
imx_imx2_wdt_data_entry_single(MX25, 0, , SZ_16K);
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst =
imx_imx2_wdt_data_entry_single(MX27, 0, , SZ_4K);

42
arch/arm/mach-imx/devices/platform-imxdi_rtc.c
View File

@ -1,42 +0,0 @@
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <asm/sizes.h>
#include "../hardware.h"
#include "devices-common.h"
#define imx_imxdi_rtc_data_entry_single(soc) \
{ \
.iobase = soc ## _DRYICE_BASE_ADDR, \
.irq = soc ## _INT_DRYICE, \
}
#ifdef CONFIG_SOC_IMX25
const struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst =
imx_imxdi_rtc_data_entry_single(MX25);
#endif /* ifdef CONFIG_SOC_IMX25 */
struct platform_device *__init imx_add_imxdi_rtc(
const struct imx_imxdi_rtc_data *data)
{
struct resource res[] = {
{
.start = data->iobase,
.end = data->iobase + SZ_16K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = data->irq,
.end = data->irq,
.flags = IORESOURCE_IRQ,
},
};
return imx_add_platform_device("imxdi_rtc", 0,
res, ARRAY_SIZE(res), NULL, 0);
}

5
arch/arm/mach-imx/devices/platform-mx2-camera.c
View File

@ -27,11 +27,6 @@
.irqemmaprp = soc ## _INT_EMMAPRP, \
}
#ifdef CONFIG_SOC_IMX25
const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst =
imx_mx2_camera_data_entry_single(MX25, "imx25-camera");
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst =
imx_mx2_camera_data_entry_single_emma(MX27, "imx27-camera");

7
arch/arm/mach-imx/devices/platform-mxc-ehci.c
View File

@ -18,13 +18,6 @@
.irq = soc ## _INT_USB_ ## hs, \
}
#ifdef CONFIG_SOC_IMX25
const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst =
imx_mxc_ehci_data_entry_single(MX25, 0, OTG);
const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst =
imx_mxc_ehci_data_entry_single(MX25, 1, HS);
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst =
imx_mxc_ehci_data_entry_single(MX27, 0, OTG);

5
arch/arm/mach-imx/devices/platform-mxc_nand.c
View File

@ -34,11 +34,6 @@ const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst =
imx_mxc_nand_data_entry_single(MX21, "imx21-nand", SZ_4K);
#endif /* ifdef CONFIG_SOC_IMX21 */
#ifdef CONFIG_SOC_IMX25
const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst =
imx_mxc_nand_data_entry_single(MX25, "imx25-nand", SZ_8K);
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst =
imx_mxc_nand_data_entry_single(MX27, "imx27-nand", SZ_4K);

11
arch/arm/mach-imx/devices/platform-spi_imx.c
View File

@ -39,17 +39,6 @@ const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
};
#endif
#ifdef CONFIG_SOC_IMX25
/* i.mx25 has the i.mx35 type cspi */
const struct imx_spi_imx_data imx25_cspi_data[] __initconst = {
#define imx25_cspi_data_entry(_id, _hwid) \
imx_spi_imx_data_entry(MX25, CSPI, "imx35-cspi", _id, _hwid, SZ_16K)
imx25_cspi_data_entry(0, 1),
imx25_cspi_data_entry(1, 2),
imx25_cspi_data_entry(2, 3),
};
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_spi_imx_data imx27_cspi_data[] __initconst = {
#define imx27_cspi_data_entry(_id, _hwid) \

99
arch/arm/mach-imx/ehci-imx25.c
View File

@ -1,99 +0,0 @@
/*
* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
* Copyright (C) 2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/platform_data/usb-ehci-mxc.h>
#include "ehci.h"
#include "hardware.h"
#define USBCTRL_OTGBASE_OFFSET 0x600
#define MX25_OTG_SIC_SHIFT 29
#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT)
#define MX25_OTG_PM_BIT (1 << 24)
#define MX25_OTG_PP_BIT (1 << 11)
#define MX25_OTG_OCPOL_BIT (1 << 3)
#define MX25_H1_SIC_SHIFT 21
#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
#define MX25_H1_PP_BIT (1 << 18)
#define MX25_H1_PM_BIT (1 << 16)
#define MX25_H1_IPPUE_UP_BIT (1 << 7)
#define MX25_H1_IPPUE_DOWN_BIT (1 << 6)
#define MX25_H1_TLL_BIT (1 << 5)
#define MX25_H1_USBTE_BIT (1 << 4)
#define MX25_H1_OCPOL_BIT (1 << 2)
int mx25_initialize_usb_hw(int port, unsigned int flags)
{
unsigned int v;
v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
switch (port) {
case 0: /* OTG port */
v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
MX25_OTG_OCPOL_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
v |= MX25_OTG_PM_BIT;
if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
v |= MX25_OTG_PP_BIT;
if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
v |= MX25_OTG_OCPOL_BIT;
break;
case 1: /* H1 port */
v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |
MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
v |= MX25_H1_PM_BIT;
if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
v |= MX25_H1_PP_BIT;
if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
v |= MX25_H1_OCPOL_BIT;
if (!(flags & MXC_EHCI_TTL_ENABLED))
v |= MX25_H1_TLL_BIT;
if (flags & MXC_EHCI_INTERNAL_PHY)
v |= MX25_H1_USBTE_BIT;
if (flags & MXC_EHCI_IPPUE_DOWN)
v |= MX25_H1_IPPUE_DOWN_BIT;
if (flags & MXC_EHCI_IPPUE_UP)
v |= MX25_H1_IPPUE_UP_BIT;
break;
default:
return -EINVAL;
}
writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
return 0;
}

310
arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
View File

@ -1,310 +0,0 @@
/*
* Copyright (C) 2010 Eric Benard - eric@eukrea.com
*
* Based on pcm970-baseboard.c which is :
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/gpio.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/spi/spi.h>
#include <video/platform_lcd.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include "common.h"
#include "devices-imx25.h"
#include "hardware.h"
#include "iomux-mx25.h"
#include "mx25.h"
static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
/* LCD */
MX25_PAD_LD0__LD0,
MX25_PAD_LD1__LD1,
MX25_PAD_LD2__LD2,
MX25_PAD_LD3__LD3,
MX25_PAD_LD4__LD4,
MX25_PAD_LD5__LD5,
MX25_PAD_LD6__LD6,
MX25_PAD_LD7__LD7,
MX25_PAD_LD8__LD8,
MX25_PAD_LD9__LD9,
MX25_PAD_LD10__LD10,
MX25_PAD_LD11__LD11,
MX25_PAD_LD12__LD12,
MX25_PAD_LD13__LD13,
MX25_PAD_LD14__LD14,
MX25_PAD_LD15__LD15,
MX25_PAD_GPIO_E__LD16,
MX25_PAD_GPIO_F__LD17,
MX25_PAD_HSYNC__HSYNC,
MX25_PAD_VSYNC__VSYNC,
MX25_PAD_LSCLK__LSCLK,
MX25_PAD_OE_ACD__OE_ACD,
MX25_PAD_CONTRAST__CONTRAST,
/* LCD_PWR */
MX25_PAD_PWM__GPIO_1_26,
/* LED */
MX25_PAD_POWER_FAIL__GPIO_3_19,
/* SWITCH */
MX25_PAD_VSTBY_ACK__GPIO_3_18,
/* UART2 */
MX25_PAD_UART2_RTS__UART2_RTS,
MX25_PAD_UART2_CTS__UART2_CTS,
MX25_PAD_UART2_TXD__UART2_TXD,
MX25_PAD_UART2_RXD__UART2_RXD,
/* SD1 */
MX25_PAD_SD1_CMD__SD1_CMD,
MX25_PAD_SD1_CLK__SD1_CLK,
MX25_PAD_SD1_DATA0__SD1_DATA0,
MX25_PAD_SD1_DATA1__SD1_DATA1,
MX25_PAD_SD1_DATA2__SD1_DATA2,
MX25_PAD_SD1_DATA3__SD1_DATA3,
/* SD1 CD */
MX25_PAD_DE_B__GPIO_2_20,
/* I2S */
MX25_PAD_KPP_COL3__AUD5_TXFS,
MX25_PAD_KPP_COL2__AUD5_TXC,
MX25_PAD_KPP_COL1__AUD5_RXD,
MX25_PAD_KPP_COL0__AUD5_TXD,
/* CAN */
MX25_PAD_GPIO_D__CAN2_RX,
MX25_PAD_GPIO_C__CAN2_TX,
/* SPI1 */
MX25_PAD_CSPI1_MOSI__CSPI1_MOSI,
MX25_PAD_CSPI1_MISO__CSPI1_MISO,
MX25_PAD_CSPI1_SS0__GPIO_1_16,
MX25_PAD_CSPI1_SS1__GPIO_1_17,
MX25_PAD_CSPI1_SCLK__CSPI1_SCLK,
MX25_PAD_CSPI1_RDY__GPIO_2_22,
};
#define GPIO_LED1 IMX_GPIO_NR(3, 19)
#define GPIO_SWITCH1 IMX_GPIO_NR(3, 18)
#define GPIO_SD1CD IMX_GPIO_NR(2, 20)
#define GPIO_LCDPWR IMX_GPIO_NR(1, 26)
#define GPIO_SPI1_SS0 IMX_GPIO_NR(1, 16)
#define GPIO_SPI1_SS1 IMX_GPIO_NR(1, 17)
#define GPIO_SPI1_IRQ IMX_GPIO_NR(2, 22)
static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
{
.mode = {
.name = "CMO-QVGA",
.refresh = 60,
.xres = 320,
.yres = 240,
.pixclock = KHZ2PICOS(6500),
.left_margin = 30,
.right_margin = 38,
.upper_margin = 20,
.lower_margin = 3,
.hsync_len = 15,
.vsync_len = 4,
},
.bpp = 16,
.pcr = 0xCAD08B80,
}, {
.mode = {
.name = "DVI-VGA",
.refresh = 60,
.xres = 640,
.yres = 480,
.pixclock = 32000,
.hsync_len = 7,
.left_margin = 100,
.right_margin = 100,
.vsync_len = 7,
.upper_margin = 7,
.lower_margin = 100,
},
.pcr = 0xFA208B80,
.bpp = 16,
}, {
.mode = {
.name = "DVI-SVGA",
.refresh = 60,
.xres = 800,
.yres = 600,
.pixclock = 25000,
.hsync_len = 7,
.left_margin = 75,
.right_margin = 75,
.vsync_len = 7,
.upper_margin = 7,
.lower_margin = 75,
},
.pcr = 0xFA208B80,
.bpp = 16,
},
};
static const struct imx_fb_platform_data eukrea_mximxsd_fb_pdata __initconst = {
.mode = eukrea_mximxsd_modes,
.num_modes = ARRAY_SIZE(eukrea_mximxsd_modes),
.pwmr = 0x00A903FF,
.lscr1 = 0x00120300,
.dmacr = 0x00040060,
};
static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
unsigned int power)
{
if (power)
gpio_direction_output(GPIO_LCDPWR, 1);
else
gpio_direction_output(GPIO_LCDPWR, 0);
}
static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
.set_power = eukrea_mbimxsd_lcd_power_set,
};
static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
.name = "platform-lcd",
.dev.platform_data = &eukrea_mbimxsd_lcd_power_data,
};
static const struct gpio_led eukrea_mbimxsd_leds[] __initconst = {
{
.name = "led1",
.default_trigger = "heartbeat",
.active_low = 1,
.gpio = GPIO_LED1,
},
};
static const struct gpio_led_platform_data
eukrea_mbimxsd_led_info __initconst = {
.leds = eukrea_mbimxsd_leds,
.num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
};
static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
{
.gpio = GPIO_SWITCH1,
.code = BTN_0,
.desc = "BP1",
.active_low = 1,
.wakeup = 1,
},
};
static const struct gpio_keys_platform_data
eukrea_mbimxsd_button_data __initconst = {
.buttons = eukrea_mbimxsd_gpio_buttons,
.nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
};
static struct platform_device *platform_devices[] __initdata = {
&eukrea_mbimxsd_lcd_powerdev,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
{
I2C_BOARD_INFO("tlv320aic23", 0x1a),
},
};
static const
struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = {
.flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
};
static struct esdhc_platform_data sd1_pdata = {
.cd_gpio = GPIO_SD1CD,
.cd_type = ESDHC_CD_GPIO,
.wp_type = ESDHC_WP_NONE,
};
static struct spi_board_info eukrea_mbimxsd25_spi_board_info[] __initdata = {
{
.modalias = "spidev",
.max_speed_hz = 20000000,
.bus_num = 0,
.chip_select = 0,
.mode = SPI_MODE_0,
},
{
.modalias = "spidev",
.max_speed_hz = 20000000,
.bus_num = 0,
.chip_select = 1,
.mode = SPI_MODE_0,
},
};
static int eukrea_mbimxsd25_spi_cs[] = {GPIO_SPI1_SS0, GPIO_SPI1_SS1};
static const struct spi_imx_master eukrea_mbimxsd25_spi0_data __initconst = {
.chipselect = eukrea_mbimxsd25_spi_cs,
.num_chipselect = ARRAY_SIZE(eukrea_mbimxsd25_spi_cs),
};
/*
* system init for baseboard usage. Will be called by cpuimx25 init.
*
* Add platform devices present on this baseboard and init
* them from CPU side as far as required to use them later on
*/
void __init eukrea_mbimxsd25_baseboard_init(void)
{
if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
ARRAY_SIZE(eukrea_mbimxsd_pads)))
printk(KERN_ERR "error setting mbimxsd pads !\n");
imx25_add_imx_uart1(&uart_pdata);
imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata);
imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
imx25_add_flexcan1();
imx25_add_sdhci_esdhc_imx(0, &sd1_pdata);
gpio_request(GPIO_LED1, "LED1");
gpio_direction_output(GPIO_LED1, 1);
gpio_free(GPIO_LED1);
gpio_request(GPIO_SWITCH1, "SWITCH1");
gpio_direction_input(GPIO_SWITCH1);
gpio_free(GPIO_SWITCH1);
gpio_request(GPIO_LCDPWR, "LCDPWR");
gpio_direction_output(GPIO_LCDPWR, 1);
i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
gpio_request(GPIO_SPI1_IRQ, "SPI1_IRQ");
gpio_direction_input(GPIO_SPI1_IRQ);
gpio_free(GPIO_SPI1_IRQ);
imx25_add_spi_imx0(&eukrea_mbimxsd25_spi0_data);
spi_register_board_info(eukrea_mbimxsd25_spi_board_info,
ARRAY_SIZE(eukrea_mbimxsd25_spi_board_info));
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
gpio_led_register_device(-1, &eukrea_mbimxsd_led_info);
imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
}

2
arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
View File

@ -100,7 +100,7 @@ static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.num_modes = ARRAY_SIZE(fb_modedb),
};
static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
static const iomux_v3_cfg_t eukrea_mbimxsd_pads[] __initconst = {
/* LCD */
MX35_PAD_LD0__IPU_DISPB_DAT_0,
MX35_PAD_LD1__IPU_DISPB_DAT_1,

353
arch/arm/mach-imx/gpc.c
View File

@ -10,15 +10,25 @@
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/regulator/consumer.h>
#include <linux/irqchip/arm-gic.h>
#include "common.h"
#include "hardware.h"
#define GPC_CNTR 0x000
#define GPC_IMR1 0x008
#define GPC_PGC_GPU_PDN 0x260
#define GPC_PGC_GPU_PUPSCR 0x264
#define GPC_PGC_GPU_PDNSCR 0x268
#define GPC_PGC_CPU_PDN 0x2a0
#define GPC_PGC_CPU_PUPSCR 0x2a4
#define GPC_PGC_CPU_PDNSCR 0x2a8
@ -26,6 +36,19 @@
#define GPC_PGC_SW_SHIFT 0x0
#define IMR_NUM 4
#define GPC_MAX_IRQS (IMR_NUM * 32)
#define GPU_VPU_PUP_REQ BIT(1)
#define GPU_VPU_PDN_REQ BIT(0)
#define GPC_CLK_MAX 6
struct pu_domain {
struct generic_pm_domain base;
struct regulator *reg;
struct clk *clk[GPC_CLK_MAX];
int num_clks;
};
static void __iomem *gpc_base;
static u32 gpc_wake_irqs[IMR_NUM];
@ -77,17 +100,17 @@ void imx_gpc_post_resume(void)
static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
{
unsigned int idx = d->hwirq / 32 - 1;
unsigned int idx = d->hwirq / 32;
u32 mask;
/* Sanity check for SPI irq */
if (d->hwirq < 32)
return -EINVAL;
mask = 1 << d->hwirq % 32;
gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
gpc_wake_irqs[idx] & ~mask;
/*
* Do *not* call into the parent, as the GIC doesn't have any
* wake-up facility...
*/
return 0;
}
@ -117,7 +140,7 @@ void imx_gpc_hwirq_unmask(unsigned int hwirq)
void __iomem *reg;
u32 val;
reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
val = readl_relaxed(reg);
val &= ~(1 << hwirq % 32);
writel_relaxed(val, reg);
@ -128,7 +151,7 @@ void imx_gpc_hwirq_mask(unsigned int hwirq)
void __iomem *reg;
u32 val;
reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
val = readl_relaxed(reg);
val |= 1 << (hwirq % 32);
writel_relaxed(val, reg);
@ -136,37 +159,319 @@ void imx_gpc_hwirq_mask(unsigned int hwirq)
static void imx_gpc_irq_unmask(struct irq_data *d)
{
/* Sanity check for SPI irq */
if (d->hwirq < 32)
return;
imx_gpc_hwirq_unmask(d->hwirq);
irq_chip_unmask_parent(d);
}
static void imx_gpc_irq_mask(struct irq_data *d)
{
/* Sanity check for SPI irq */
if (d->hwirq < 32)
return;
imx_gpc_hwirq_mask(d->hwirq);
irq_chip_mask_parent(d);
}
void __init imx_gpc_init(void)
static struct irq_chip imx_gpc_chip = {
.name = "GPC",
.irq_eoi = irq_chip_eoi_parent,
.irq_mask = imx_gpc_irq_mask,
.irq_unmask = imx_gpc_irq_unmask,
.irq_retrigger = irq_chip_retrigger_hierarchy,
.irq_set_wake = imx_gpc_irq_set_wake,
#ifdef CONFIG_SMP
.irq_set_affinity = irq_chip_set_affinity_parent,
#endif
};
static int imx_gpc_domain_xlate(struct irq_domain *domain,
struct device_node *controller,
const u32 *intspec,
unsigned int intsize,
unsigned long *out_hwirq,
unsigned int *out_type)
{
struct device_node *np;
if (domain->of_node != controller)
return -EINVAL; /* Shouldn't happen, really... */
if (intsize != 3)
return -EINVAL; /* Not GIC compliant */
if (intspec[0] != 0)
return -EINVAL; /* No PPI should point to this domain */
*out_hwirq = intspec[1];
*out_type = intspec[2];
return 0;
}
static int imx_gpc_domain_alloc(struct irq_domain *domain,
unsigned int irq,
unsigned int nr_irqs, void *data)
{
struct of_phandle_args *args = data;
struct of_phandle_args parent_args;
irq_hw_number_t hwirq;
int i;
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
gpc_base = of_iomap(np, 0);
WARN_ON(!gpc_base);
if (args->args_count != 3)
return -EINVAL; /* Not GIC compliant */
if (args->args[0] != 0)
return -EINVAL; /* No PPI should point to this domain */
hwirq = args->args[1];
if (hwirq >= GPC_MAX_IRQS)
return -EINVAL; /* Can't deal with this */
for (i = 0; i < nr_irqs; i++)
irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
&imx_gpc_chip, NULL);
parent_args = *args;
parent_args.np = domain->parent->of_node;
return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs, &parent_args);
}
static struct irq_domain_ops imx_gpc_domain_ops = {
.xlate = imx_gpc_domain_xlate,
.alloc = imx_gpc_domain_alloc,
.free = irq_domain_free_irqs_common,
};
static int __init imx_gpc_init(struct device_node *node,
struct device_node *parent)
{
struct irq_domain *parent_domain, *domain;
int i;
if (!parent) {
pr_err("%s: no parent, giving up\n", node->full_name);
return -ENODEV;
}
parent_domain = irq_find_host(parent);
if (!parent_domain) {
pr_err("%s: unable to obtain parent domain\n", node->full_name);
return -ENXIO;
}
gpc_base = of_iomap(node, 0);
if (WARN_ON(!gpc_base))
return -ENOMEM;
domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
node, &imx_gpc_domain_ops,
NULL);
if (!domain) {
iounmap(gpc_base);
return -ENOMEM;
}
/* Initially mask all interrupts */
for (i = 0; i < IMR_NUM; i++)
writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
/* Register GPC as the secondary interrupt controller behind GIC */
gic_arch_extn.irq_mask = imx_gpc_irq_mask;
gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
return 0;
}
/*
* We cannot use the IRQCHIP_DECLARE macro that lives in
* drivers/irqchip, so we're forced to roll our own. Not very nice.
*/
OF_DECLARE_2(irqchip, imx_gpc, "fsl,imx6q-gpc", imx_gpc_init);
void __init imx_gpc_check_dt(void)
{
struct device_node *np;
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
if (WARN_ON(!np ||
!of_find_property(np, "interrupt-controller", NULL)))
pr_warn("Outdated DT detected, system is about to crash!!!\n");
}
#ifdef CONFIG_PM_GENERIC_DOMAINS
static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
{
int iso, iso2sw;
u32 val;
/* Read ISO and ISO2SW power down delays */
val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR);
iso = val & 0x3f;
iso2sw = (val >> 8) & 0x3f;
/* Gate off PU domain when GPU/VPU when powered down */
writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
/* Request GPC to power down GPU/VPU */
val = readl_relaxed(gpc_base + GPC_CNTR);
val |= GPU_VPU_PDN_REQ;
writel_relaxed(val, gpc_base + GPC_CNTR);
/* Wait ISO + ISO2SW IPG clock cycles */
ndelay((iso + iso2sw) * 1000 / 66);
}
static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
{
struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
_imx6q_pm_pu_power_off(genpd);
if (pu->reg)
regulator_disable(pu->reg);
return 0;
}
static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
{
struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
int i, ret, sw, sw2iso;
u32 val;
if (pu->reg)
ret = regulator_enable(pu->reg);
if (pu->reg && ret) {
pr_err("%s: failed to enable regulator: %d\n", __func__, ret);
return ret;
}
/* Enable reset clocks for all devices in the PU domain */
for (i = 0; i < pu->num_clks; i++)
clk_prepare_enable(pu->clk[i]);
/* Gate off PU domain when GPU/VPU when powered down */
writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
/* Read ISO and ISO2SW power down delays */
val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR);
sw = val & 0x3f;
sw2iso = (val >> 8) & 0x3f;
/* Request GPC to power up GPU/VPU */
val = readl_relaxed(gpc_base + GPC_CNTR);
val |= GPU_VPU_PUP_REQ;
writel_relaxed(val, gpc_base + GPC_CNTR);
/* Wait ISO + ISO2SW IPG clock cycles */
ndelay((sw + sw2iso) * 1000 / 66);
/* Disable reset clocks for all devices in the PU domain */
for (i = 0; i < pu->num_clks; i++)
clk_disable_unprepare(pu->clk[i]);
return 0;
}
static struct generic_pm_domain imx6q_arm_domain = {
.name = "ARM",
};
static struct pu_domain imx6q_pu_domain = {
.base = {
.name = "PU",
.power_off = imx6q_pm_pu_power_off,
.power_on = imx6q_pm_pu_power_on,
.power_off_latency_ns = 25000,
.power_on_latency_ns = 2000000,
},
};
static struct generic_pm_domain imx6sl_display_domain = {
.name = "DISPLAY",
};
static struct generic_pm_domain *imx_gpc_domains[] = {
&imx6q_arm_domain,
&imx6q_pu_domain.base,
&imx6sl_display_domain,
};
static struct genpd_onecell_data imx_gpc_onecell_data = {
.domains = imx_gpc_domains,
.num_domains = ARRAY_SIZE(imx_gpc_domains),
};
static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
{
struct clk *clk;
bool is_off;
int i;
imx6q_pu_domain.reg = pu_reg;
for (i = 0; ; i++) {
clk = of_clk_get(dev->of_node, i);
if (IS_ERR(clk))
break;
if (i >= GPC_CLK_MAX) {
dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
goto clk_err;
}
imx6q_pu_domain.clk[i] = clk;
}
imx6q_pu_domain.num_clks = i;
is_off = IS_ENABLED(CONFIG_PM);
if (is_off) {
_imx6q_pm_pu_power_off(&imx6q_pu_domain.base);
} else {
/*
* Enable power if compiled without CONFIG_PM in case the
* bootloader disabled it.
*/
imx6q_pm_pu_power_on(&imx6q_pu_domain.base);
}
pm_genpd_init(&imx6q_pu_domain.base, NULL, is_off);
return of_genpd_add_provider_onecell(dev->of_node,
&imx_gpc_onecell_data);
clk_err:
while (i--)
clk_put(imx6q_pu_domain.clk[i]);
return -EINVAL;
}
#else
static inline int imx_gpc_genpd_init(struct device *dev, struct regulator *reg)
{
return 0;
}
#endif /* CONFIG_PM_GENERIC_DOMAINS */
static int imx_gpc_probe(struct platform_device *pdev)
{
struct regulator *pu_reg;
int ret;
pu_reg = devm_regulator_get_optional(&pdev->dev, "pu");
if (PTR_ERR(pu_reg) == -ENODEV)
pu_reg = NULL;
if (IS_ERR(pu_reg)) {
ret = PTR_ERR(pu_reg);
dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret);
return ret;
}
return imx_gpc_genpd_init(&pdev->dev, pu_reg);
}
static const struct of_device_id imx_gpc_dt_ids[] = {
{ .compatible = "fsl,imx6q-gpc" },
{ .compatible = "fsl,imx6sl-gpc" },
{ }
};
static struct platform_driver imx_gpc_driver = {
.driver = {
.name = "imx-gpc",
.owner = THIS_MODULE,
.of_match_table = imx_gpc_dt_ids,
},
.probe = imx_gpc_probe,
};
static int __init imx_pgc_init(void)
{
return platform_driver_register(&imx_gpc_driver);
}
subsys_initcall(imx_pgc_init);

1
arch/arm/mach-imx/hardware.h
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@ -112,7 +112,6 @@
#include "mx21.h"
#include "mx27.h"
#include "mx1.h"
#include "mx25.h"
#define imx_map_entry(soc, name, _type) { \
.virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \

524
arch/arm/mach-imx/iomux-mx25.h
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@ -1,524 +0,0 @@
/*
* arch/arm/plat-mxc/include/mach/iomux-mx25.h
*
* Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de>
*
* based on arch/arm/mach-mx25/mx25_pins.h
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* and
* arch/arm/plat-mxc/include/mach/iomux-mx35.h
* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __MACH_IOMUX_MX25_H__
#define __MACH_IOMUX_MX25_H__
#include "iomux-v3.h"
/*
* IOMUX/PAD Bit field definitions
*/
#define MX25_PAD_A10__A10 IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A10__GPIO_4_0 IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A13__A13 IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A13__GPIO_4_1 IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A14__A14 IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A14__GPIO_2_0 IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A15__A15 IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A15__GPIO_2_1 IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A16__A16 IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A16__GPIO_2_2 IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A17__A17 IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A17__GPIO_2_3 IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A18__A18 IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A18__GPIO_2_4 IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A18__FEC_COL IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTRL)
#define MX25_PAD_A19__A19 IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A19__FEC_RX_ER IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTRL)
#define MX25_PAD_A19__GPIO_2_5 IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A20__A20 IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A20__GPIO_2_6 IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A20__FEC_RDATA2 IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTRL)
#define MX25_PAD_A21__A21 IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A21__GPIO_2_7 IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A21__FEC_RDATA3 IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTRL)
#define MX25_PAD_A22__A22 IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A22__GPIO_2_8 IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A23__A23 IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A23__GPIO_2_9 IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A24__A24 IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A24__GPIO_2_10 IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A24__FEC_RX_CLK IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTRL)
#define MX25_PAD_A25__A25 IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A25__GPIO_2_11 IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A25__FEC_CRS IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTRL)
#define MX25_PAD_EB0__EB0 IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_EB0__AUD4_TXD IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL)
#define MX25_PAD_EB0__GPIO_2_12 IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_EB1__EB1 IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_EB1__AUD4_RXD IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL)
#define MX25_PAD_EB1__GPIO_2_13 IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_OE__OE IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_OE__AUD4_TXC IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_OE__GPIO_2_14 IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS0__CS0 IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS0__GPIO_4_2 IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS1__CS1 IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS1__NF_CE3 IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS1__GPIO_4_3 IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS4__CS4 IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS4__NF_CE1 IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS4__UART5_CTS IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS4__GPIO_3_20 IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS5__CS5 IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS5__NF_CE2 IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS5__UART5_RTS IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL)
#define MX25_PAD_CS5__GPIO_3_21 IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NF_CE0__NF_CE0 IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NF_CE0__GPIO_3_22 IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_ECB__ECB IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_ECB__UART5_TXD_MUX IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_ECB__GPIO_3_23 IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LBA__LBA IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LBA__UART5_RXD_MUX IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL)
#define MX25_PAD_LBA__GPIO_3_24 IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_BCLK__BCLK IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_BCLK__GPIO_4_4 IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_RW__RW IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_RW__AUD4_TXFS IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL)
#define MX25_PAD_RW__GPIO_3_25 IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NFWE_B__NFWE_B IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NFWE_B__GPIO_3_26 IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NFRE_B__NFRE_B IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NFRE_B__GPIO_3_27 IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NFALE__NFALE IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NFALE__GPIO_3_28 IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NFCLE__NFCLE IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NFCLE__GPIO_3_29 IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NFWP_B__NFWP_B IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NFWP_B__GPIO_3_30 IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NFRB__NFRB IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE)
#define MX25_PAD_NFRB__GPIO_3_31 IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D15__D15 IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D15__LD16 IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_D15__GPIO_4_5 IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D14__D14 IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D14__LD17 IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_D14__GPIO_4_6 IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D13__D13 IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D13__LD18 IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_D13__GPIO_4_7 IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D12__D12 IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D12__GPIO_4_8 IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D11__D11 IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D11__GPIO_4_9 IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D10__D10 IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D10__GPIO_4_10 IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D10__USBOTG_OC IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP)
#define MX25_PAD_D9__D9 IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D9__GPIO_4_11 IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D9__USBH2_PWR IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE)
#define MX25_PAD_D8__D8 IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D8__GPIO_4_12 IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D8__USBH2_OC IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP)
#define MX25_PAD_D7__D7 IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D7__GPIO_4_13 IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D6__D6 IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D6__GPIO_4_14 IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D5__D5 IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D5__GPIO_4_15 IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D4__D4 IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D4__GPIO_4_16 IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D3__D3 IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D3__GPIO_4_17 IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D2__D2 IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D2__GPIO_4_18 IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D1__D1 IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D1__GPIO_4_19 IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D0__D0 IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D0__GPIO_4_20 IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD0__LD0 IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD0__CSI_D0 IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL)
#define MX25_PAD_LD0__GPIO_2_15 IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD1__LD1 IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD1__CSI_D1 IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL)
#define MX25_PAD_LD1__GPIO_2_16 IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD2__LD2 IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD2__GPIO_2_17 IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD3__LD3 IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD3__GPIO_2_18 IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD4__LD4 IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD4__GPIO_2_19 IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD5__LD5 IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD5__GPIO_1_19 IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD6__LD6 IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD6__GPIO_1_20 IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD7__LD7 IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD7__GPIO_1_21 IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD8__LD8 IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD8__FEC_TX_ERR IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD9__LD9 IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD9__FEC_COL IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL)
#define MX25_PAD_LD10__LD10 IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD10__FEC_RX_ER IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL)
#define MX25_PAD_LD11__LD11 IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD11__FEC_RDATA2 IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL)
#define MX25_PAD_LD12__LD12 IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD12__FEC_RDATA3 IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL)
#define MX25_PAD_LD13__LD13 IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD13__FEC_TDATA2 IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD14__LD14 IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD14__FEC_TDATA3 IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD15__LD15 IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD15__FEC_RX_CLK IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL)
#define MX25_PAD_HSYNC__HSYNC IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_HSYNC__GPIO_1_22 IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_VSYNC__VSYNC IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_VSYNC__GPIO_1_23 IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LSCLK__LSCLK IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LSCLK__GPIO_1_24 IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_OE_ACD__OE_ACD IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_OE_ACD__GPIO_1_25 IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CONTRAST__CONTRAST IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CONTRAST__PWM4_PWMO IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CONTRAST__FEC_CRS IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL)
#define MX25_PAD_PWM__PWM IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_PWM__GPIO_1_26 IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_PWM__USBH2_OC IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP)
#define MX25_PAD_CSI_D2__CSI_D2 IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D2__UART5_RXD_MUX IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL)
#define MX25_PAD_CSI_D2__GPIO_1_27 IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D2__CSPI3_MOSI IOMUX_PAD(0x318, 0x120, 0x17, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D3__CSI_D3 IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D3__GPIO_1_28 IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D3__CSPI3_MISO IOMUX_PAD(0x31c, 0x124, 0x17, 0x4b4, 1, NO_PAD_CTRL)
#define MX25_PAD_CSI_D4__CSI_D4 IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D4__UART5_RTS IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL)
#define MX25_PAD_CSI_D4__GPIO_1_29 IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D4__CSPI3_SCLK IOMUX_PAD(0x320, 0x128, 0x17, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D5__CSI_D5 IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D5__GPIO_1_30 IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D5__CSPI3_RDY IOMUX_PAD(0x324, 0x12c, 0x17, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D6__CSI_D6 IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D6__GPIO_1_31 IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D7__CSI_D7 IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D7__GPIO_1_6 IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D8__CSI_D8 IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D8__GPIO_1_7 IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D9__CSI_D9 IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D9__GPIO_4_21 IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_MCLK__CSI_MCLK IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_MCLK__GPIO_1_8 IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_VSYNC__CSI_VSYNC IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_VSYNC__GPIO_1_9 IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_HSYNC__CSI_HSYNC IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_HSYNC__GPIO_1_10 IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_I2C1_CLK__GPIO_1_12 IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_I2C1_DAT__GPIO_1_13 IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSPI1_MISO__GPIO_1_15 IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSPI1_SS0__GPIO_1_16 IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSPI1_SS1__GPIO_1_17 IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSPI1_RDY__CSPI1_RDY IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE)
#define MX25_PAD_CSPI1_RDY__GPIO_2_22 IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN)
#define MX25_PAD_UART1_RXD__GPIO_4_22 IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART1_TXD__GPIO_4_23 IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP)
#define MX25_PAD_UART1_RTS__CSI_D0 IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL)
#define MX25_PAD_UART1_RTS__GPIO_4_24 IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP)
#define MX25_PAD_UART1_CTS__CSI_D1 IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL)
#define MX25_PAD_UART1_CTS__GPIO_4_25 IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART2_RXD__GPIO_4_26 IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART2_TXD__GPIO_4_27 IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART2_RTS__FEC_COL IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTRL)
#define MX25_PAD_UART2_RTS__GPIO_4_28 IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART2_CTS__FEC_RX_ER IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTRL)
#define MX25_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART2_CTS__GPIO_4_29 IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
#define MX25_PAD_SD1_CMD__FEC_RDATA2 IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTRL)
#define MX25_PAD_SD1_CMD__GPIO_2_23 IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
#define MX25_PAD_SD1_CLK__FEC_RDATA3 IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTRL)
#define MX25_PAD_SD1_CLK__GPIO_2_24 IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
#define MX25_PAD_SD1_DATA0__GPIO_2_25 IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
#define MX25_PAD_SD1_DATA1__AUD7_RXD IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA1__GPIO_2_26 IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
#define MX25_PAD_SD1_DATA2__FEC_RX_CLK IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA2__GPIO_2_27 IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
#define MX25_PAD_SD1_DATA3__FEC_CRS IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA3__GPIO_2_28 IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL)
#define KPP_CTL_ROW (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#define KPP_CTL_COL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
#define MX25_PAD_KPP_ROW0__KPP_ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, KPP_CTL_ROW)
#define MX25_PAD_KPP_ROW0__GPIO_2_29 IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_KPP_ROW1__KPP_ROW1 IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, KPP_CTL_ROW)
#define MX25_PAD_KPP_ROW1__GPIO_2_30 IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_KPP_ROW2__KPP_ROW2 IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, KPP_CTL_ROW)
#define MX25_PAD_KPP_ROW2__CSI_D0 IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL)
#define MX25_PAD_KPP_ROW2__GPIO_2_31 IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_KPP_ROW3__KPP_ROW3 IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, KPP_CTL_ROW)
#define MX25_PAD_KPP_ROW3__CSI_LD1 IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL)
#define MX25_PAD_KPP_ROW3__GPIO_3_0 IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_KPP_COL0__KPP_COL0 IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, KPP_CTL_COL)
#define MX25_PAD_KPP_COL0__UART4_RXD_MUX IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL)
#define MX25_PAD_KPP_COL0__AUD5_TXD IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
#define MX25_PAD_KPP_COL0__GPIO_3_1 IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_KPP_COL1__KPP_COL1 IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, KPP_CTL_COL)
#define MX25_PAD_KPP_COL1__UART4_TXD_MUX IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_KPP_COL1__AUD5_RXD IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
#define MX25_PAD_KPP_COL1__GPIO_3_2 IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_KPP_COL2__KPP_COL2 IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, KPP_CTL_COL)
#define MX25_PAD_KPP_COL2__UART4_RTS IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_KPP_COL2__AUD5_TXC IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
#define MX25_PAD_KPP_COL2__GPIO_3_3 IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_KPP_COL3__KPP_COL3 IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, KPP_CTL_COL)
#define MX25_PAD_KPP_COL3__UART4_CTS IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_KPP_COL3__AUD5_TXFS IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
#define MX25_PAD_KPP_COL3__GPIO_3_4 IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_FEC_MDC__AUD4_TXD IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL)
#define MX25_PAD_FEC_MDC__GPIO_3_5 IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP)
#define MX25_PAD_FEC_MDIO__AUD4_RXD IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL)
#define MX25_PAD_FEC_MDIO__GPIO_3_6 IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_FEC_TDATA0__GPIO_3_7 IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_FEC_TDATA1__AUD4_TXFS IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL)
#define MX25_PAD_FEC_TDATA1__GPIO_3_8 IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_FEC_TX_EN__GPIO_3_9 IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
#define MX25_PAD_FEC_RDATA0__GPIO_3_10 IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
#define MX25_PAD_FEC_RDATA1__GPIO_3_11 IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_FEC_RX_DV__FEC_RX_DV IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
#define MX25_PAD_FEC_RX_DV__CAN2_RX IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP)
#define MX25_PAD_FEC_RX_DV__GPIO_3_12 IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN)
#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_RTCK__RTCK IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_RTCK__OWIRE IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_RTCK__GPIO_3_14 IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_DE_B__DE_B IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_DE_B__GPIO_2_20 IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_TDO__TDO IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_A__GPIO_A IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_A__CAN1_TX IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
#define MX25_PAD_GPIO_A__USBOTG_PWR IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE)
#define MX25_PAD_GPIO_B__GPIO_B IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_B__CAN1_RX IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K_UP)
#define MX25_PAD_GPIO_B__USBOTG_OC IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP)
#define MX25_PAD_GPIO_C__GPIO_C IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_C__CAN2_TX IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
#define MX25_PAD_GPIO_D__GPIO_D IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_E__LD16 IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_GPIO_D__CAN2_RX IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
#define MX25_PAD_GPIO_E__GPIO_E IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_F__LD17 IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_F__GPIO_F IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_F__AUD7_TXC IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_VSTBY_REQ__VSTBY_REQ IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_VSTBY_REQ__AUD7_TXFS IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_VSTBY_REQ__GPIO_3_17 IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_VSTBY_ACK__VSTBY_ACK IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_VSTBY_ACK__GPIO_3_18 IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_POWER_FAIL__POWER_FAIL IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_POWER_FAIL__AUD7_RXD IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL)
#define MX25_PAD_POWER_FAIL__GPIO_3_19 IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CLKO__CLKO IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CLKO__GPIO_2_21 IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_BOOT_MODE0__GPIO_4_30 IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_BOOT_MODE1__GPIO_4_31 IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DVS_MISC IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DSE_FEC IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DVS_JTAG IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DSE_NFC IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DSE_CSI IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DSE_WEIM IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DSE_DDR IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DVS_CRM IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DSE_KPP IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DSE_SDHC1 IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DSE_LCD IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DSE_UART IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DVS_NFC IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DVS_CSI IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DSE_CSPI1 IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DDRTYPE IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DVS_SDHC1 IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DVS_LCD IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL)
#endif /* __MACH_IOMUX_MX25_H__ */

2
arch/arm/mach-imx/iomux-mx3.h
View File

@ -114,7 +114,7 @@ enum iomux_gp_func {
*/
int mxc_iomux_alloc_pin(unsigned int pin, const char *label);
/*
* setups mutliple pins
* setups multiple pins
* convenient way to call the above function with tables
*/
int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,

5
arch/arm/mach-imx/iomux-v3.c
View File

@ -56,9 +56,10 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
return 0;
}
int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list,
unsigned count)
{
iomux_v3_cfg_t *p = pad_list;
const iomux_v3_cfg_t *p = pad_list;
int i;
int ret;

5
arch/arm/mach-imx/iomux-v3.h
View File

@ -128,10 +128,11 @@ typedef u64 iomux_v3_cfg_t;
int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
/*
* setups mutliple pads
* setups multiple pads
* convenient way to call the above function with tables
*/
int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list,
unsigned count);
/*
* Initialise the iomux controller

2
arch/arm/mach-imx/mach-cpuimx35.c
View File

@ -75,7 +75,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
},
};
static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = {
static const iomux_v3_cfg_t eukrea_cpuimx35_pads[] __initconst = {
/* UART1 */
MX35_PAD_CTS1__UART1_CTS,
MX35_PAD_RTS1__UART1_RTS,

172
arch/arm/mach-imx/mach-eukrea_cpuimx25.c
View File

@ -1,172 +0,0 @@
/*
* Copyright 2009 Sascha Hauer, <kernel@pengutronix.de>
* Copyright 2010 Eric Bénard - Eukréa Electromatique, <eric@eukrea.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor,
* Boston, MA 02110-1301, USA.
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
#include "common.h"
#include "devices-imx25.h"
#include "ehci.h"
#include "eukrea-baseboards.h"
#include "hardware.h"
#include "iomux-mx25.h"
#include "mx25.h"
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static iomux_v3_cfg_t eukrea_cpuimx25_pads[] = {
/* FEC - RMII */
MX25_PAD_FEC_MDC__FEC_MDC,
MX25_PAD_FEC_MDIO__FEC_MDIO,
MX25_PAD_FEC_TDATA0__FEC_TDATA0,
MX25_PAD_FEC_TDATA1__FEC_TDATA1,
MX25_PAD_FEC_TX_EN__FEC_TX_EN,
MX25_PAD_FEC_RDATA0__FEC_RDATA0,
MX25_PAD_FEC_RDATA1__FEC_RDATA1,
MX25_PAD_FEC_RX_DV__FEC_RX_DV,
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
/* I2C1 */
MX25_PAD_I2C1_CLK__I2C1_CLK,
MX25_PAD_I2C1_DAT__I2C1_DAT,
};
static const struct fec_platform_data mx25_fec_pdata __initconst = {
.phy = PHY_INTERFACE_MODE_RMII,
};
static const struct mxc_nand_platform_data
eukrea_cpuimx25_nand_board_info __initconst = {
.width = 1,
.hw_ecc = 1,
.flash_bbt = 1,
};
static const struct imxi2c_platform_data
eukrea_cpuimx25_i2c0_data __initconst = {
.bitrate = 100000,
};
static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = {
{
I2C_BOARD_INFO("pcf8563", 0x51),
},
};
static int eukrea_cpuimx25_otg_init(struct platform_device *pdev)
{
return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
}
static const struct mxc_usbh_platform_data otg_pdata __initconst = {
.init = eukrea_cpuimx25_otg_init,
.portsc = MXC_EHCI_MODE_UTMI,
};
static int eukrea_cpuimx25_usbh2_init(struct platform_device *pdev)
{
return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
}
static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
.init = eukrea_cpuimx25_usbh2_init,
.portsc = MXC_EHCI_MODE_SERIAL,
};
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_UTMI,
.workaround = FLS_USB2_WORKAROUND_ENGCM09152,
};
static bool otg_mode_host __initdata;
static int __init eukrea_cpuimx25_otg_mode(char *options)
{
if (!strcmp(options, "host"))
otg_mode_host = true;
else if (!strcmp(options, "device"))
otg_mode_host = false;
else
pr_info("otg_mode neither \"host\" nor \"device\". "
"Defaulting to device\n");
return 1;
}
__setup("otg_mode=", eukrea_cpuimx25_otg_mode);
static void __init eukrea_cpuimx25_init(void)
{
imx25_soc_init();
if (mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads,
ARRAY_SIZE(eukrea_cpuimx25_pads)))
printk(KERN_ERR "error setting cpuimx25 pads !\n");
imx25_add_imx_uart0(&uart_pdata);
imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
imx25_add_imxdi_rtc();
imx25_add_fec(&mx25_fec_pdata);
imx25_add_imx2_wdt();
i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
ARRAY_SIZE(eukrea_cpuimx25_i2c_devices));
imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data);
if (otg_mode_host)
imx25_add_mxc_ehci_otg(&otg_pdata);
else
imx25_add_fsl_usb2_udc(&otg_device_pdata);
imx25_add_mxc_ehci_hs(&usbh2_pdata);
#ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD
eukrea_mbimxsd25_baseboard_init();
#endif
}
static void __init eukrea_cpuimx25_timer_init(void)
{
mx25_clocks_init();
}
MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
/* Maintainer: Eukrea Electromatique */
.atag_offset = 0x100,
.map_io = mx25_map_io,
.init_early = imx25_init_early,
.init_irq = mx25_init_irq,
.init_time = eukrea_cpuimx25_timer_init,
.init_machine = eukrea_cpuimx25_init,
.restart = mxc_restart,
MACHINE_END

20
arch/arm/mach-imx/imx25-dt.c → arch/arm/mach-imx/mach-imx25.c
View File

@ -10,12 +10,29 @@
*/
#include <linux/irq.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "common.h"
#include "mx25.h"
#include "hardware.h"
static void __init imx25_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX25);
}
static void __init mx25_init_irq(void)
{
struct device_node *np;
void __iomem *avic_base;
np = of_find_compatible_node(NULL, NULL, "fsl,avic");
avic_base = of_iomap(np, 0);
BUG_ON(!avic_base);
mxc_init_irq(avic_base);
}
static const char * const imx25_dt_board_compat[] __initconst = {
"fsl,imx25",
@ -23,7 +40,6 @@ static const char * const imx25_dt_board_compat[] __initconst = {
};
DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
.map_io = mx25_map_io,
.init_early = imx25_init_early,
.init_irq = mx25_init_irq,
.dt_compat = imx25_dt_board_compat,

2
arch/arm/mach-imx/mach-imx6q.c
View File

@ -387,10 +387,10 @@ static void __init imx6q_map_io(void)
static void __init imx6q_init_irq(void)
{
imx_gpc_check_dt();
imx_init_revision_from_anatop();
imx_init_l2cache();
imx_src_init();
imx_gpc_init();
irqchip_init();
}

2
arch/arm/mach-imx/mach-imx6sl.c
View File

@ -61,10 +61,10 @@ static void __init imx6sl_init_machine(void)
static void __init imx6sl_init_irq(void)
{
imx_gpc_check_dt();
imx_init_revision_from_anatop();
imx_init_l2cache();
imx_src_init();
imx_gpc_init();
irqchip_init();
}

2
arch/arm/mach-imx/mach-imx6sx.c
View File

@ -81,10 +81,10 @@ static void __init imx6sx_init_machine(void)
static void __init imx6sx_init_irq(void)
{
imx_gpc_check_dt();
imx_init_revision_from_anatop();
imx_init_l2cache();
imx_src_init();
imx_gpc_init();
irqchip_init();
}

270
arch/arm/mach-imx/mach-mx25_3ds.c
View File

@ -1,270 +0,0 @@
/*
* Copyright 2009 Sascha Hauer, <kernel@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor,
* Boston, MA 02110-1301, USA.
*/
/*
* This machine is known as:
* - i.MX25 3-Stack Development System
* - i.MX25 Platform Development Kit (i.MX25 PDK)
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/usb/otg.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
#include "common.h"
#include "devices-imx25.h"
#include "ehci.h"
#include "hardware.h"
#include "iomux-mx25.h"
#include "mx25.h"
#define MX25PDK_CAN_PWDN IMX_GPIO_NR(4, 6)
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static iomux_v3_cfg_t mx25pdk_pads[] = {
MX25_PAD_FEC_MDC__FEC_MDC,
MX25_PAD_FEC_MDIO__FEC_MDIO,
MX25_PAD_FEC_TDATA0__FEC_TDATA0,
MX25_PAD_FEC_TDATA1__FEC_TDATA1,
MX25_PAD_FEC_TX_EN__FEC_TX_EN,
MX25_PAD_FEC_RDATA0__FEC_RDATA0,
MX25_PAD_FEC_RDATA1__FEC_RDATA1,
MX25_PAD_FEC_RX_DV__FEC_RX_DV,
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
MX25_PAD_A17__GPIO_2_3, /* FEC_EN, GPIO 35 */
MX25_PAD_D12__GPIO_4_8, /* FEC_RESET_B, GPIO 104 */
/* LCD */
MX25_PAD_LD0__LD0,
MX25_PAD_LD1__LD1,
MX25_PAD_LD2__LD2,
MX25_PAD_LD3__LD3,
MX25_PAD_LD4__LD4,
MX25_PAD_LD5__LD5,
MX25_PAD_LD6__LD6,
MX25_PAD_LD7__LD7,
MX25_PAD_LD8__LD8,
MX25_PAD_LD9__LD9,
MX25_PAD_LD10__LD10,
MX25_PAD_LD11__LD11,
MX25_PAD_LD12__LD12,
MX25_PAD_LD13__LD13,
MX25_PAD_LD14__LD14,
MX25_PAD_LD15__LD15,
MX25_PAD_GPIO_E__LD16,
MX25_PAD_GPIO_F__LD17,
MX25_PAD_HSYNC__HSYNC,
MX25_PAD_VSYNC__VSYNC,
MX25_PAD_LSCLK__LSCLK,
MX25_PAD_OE_ACD__OE_ACD,
MX25_PAD_CONTRAST__CONTRAST,
/* Keypad */
MX25_PAD_KPP_ROW0__KPP_ROW0,
MX25_PAD_KPP_ROW1__KPP_ROW1,
MX25_PAD_KPP_ROW2__KPP_ROW2,
MX25_PAD_KPP_ROW3__KPP_ROW3,
MX25_PAD_KPP_COL0__KPP_COL0,
MX25_PAD_KPP_COL1__KPP_COL1,
MX25_PAD_KPP_COL2__KPP_COL2,
MX25_PAD_KPP_COL3__KPP_COL3,
/* SD1 */
MX25_PAD_SD1_CMD__SD1_CMD,
MX25_PAD_SD1_CLK__SD1_CLK,
MX25_PAD_SD1_DATA0__SD1_DATA0,
MX25_PAD_SD1_DATA1__SD1_DATA1,
MX25_PAD_SD1_DATA2__SD1_DATA2,
MX25_PAD_SD1_DATA3__SD1_DATA3,
MX25_PAD_A14__GPIO_2_0, /* WriteProtect */
MX25_PAD_A15__GPIO_2_1, /* CardDetect */
/* I2C1 */
MX25_PAD_I2C1_CLK__I2C1_CLK,
MX25_PAD_I2C1_DAT__I2C1_DAT,
/* CAN1 */
MX25_PAD_GPIO_A__CAN1_TX,
MX25_PAD_GPIO_B__CAN1_RX,
MX25_PAD_D14__GPIO_4_6, /* CAN_PWDN */
};
static const struct fec_platform_data mx25_fec_pdata __initconst = {
.phy = PHY_INTERFACE_MODE_RMII,
};
#define FEC_ENABLE_GPIO IMX_GPIO_NR(2, 3)
#define FEC_RESET_B_GPIO IMX_GPIO_NR(4, 8)
static void __init mx25pdk_fec_reset(void)
{
gpio_request(FEC_ENABLE_GPIO, "FEC PHY enable");
gpio_request(FEC_RESET_B_GPIO, "FEC PHY reset");
gpio_direction_output(FEC_ENABLE_GPIO, 0); /* drop PHY power */
gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */
udelay(2);
/* turn on PHY power and lift reset */
gpio_set_value(FEC_ENABLE_GPIO, 1);
gpio_set_value(FEC_RESET_B_GPIO, 1);
}
static const struct mxc_nand_platform_data
mx25pdk_nand_board_info __initconst = {
.width = 1,
.hw_ecc = 1,
.flash_bbt = 1,
};
static struct imx_fb_videomode mx25pdk_modes[] = {
{
.mode = {
.name = "CRT-VGA",
.refresh = 60,
.xres = 640,
.yres = 480,
.pixclock = 39683,
.left_margin = 45,
.right_margin = 114,
.upper_margin = 33,
.lower_margin = 11,
.hsync_len = 1,
.vsync_len = 1,
},
.bpp = 16,
.pcr = 0xFA208B80,
},
};
static const struct imx_fb_platform_data mx25pdk_fb_pdata __initconst = {
.mode = mx25pdk_modes,
.num_modes = ARRAY_SIZE(mx25pdk_modes),
.pwmr = 0x00A903FF,
.lscr1 = 0x00120300,
.dmacr = 0x00020010,
};
static const uint32_t mx25pdk_keymap[] = {
KEY(0, 0, KEY_UP),
KEY(0, 1, KEY_DOWN),
KEY(0, 2, KEY_VOLUMEDOWN),
KEY(0, 3, KEY_HOME),
KEY(1, 0, KEY_RIGHT),
KEY(1, 1, KEY_LEFT),
KEY(1, 2, KEY_ENTER),
KEY(1, 3, KEY_VOLUMEUP),
KEY(2, 0, KEY_F6),
KEY(2, 1, KEY_F8),
KEY(2, 2, KEY_F9),
KEY(2, 3, KEY_F10),
KEY(3, 0, KEY_F1),
KEY(3, 1, KEY_F2),
KEY(3, 2, KEY_F3),
KEY(3, 3, KEY_POWER),
};
static const struct matrix_keymap_data mx25pdk_keymap_data __initconst = {
.keymap = mx25pdk_keymap,
.keymap_size = ARRAY_SIZE(mx25pdk_keymap),
};
static int mx25pdk_usbh2_init(struct platform_device *pdev)
{
return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
}
static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
.init = mx25pdk_usbh2_init,
.portsc = MXC_EHCI_MODE_SERIAL,
};
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_UTMI,
};
static const struct imxi2c_platform_data mx25_3ds_i2c0_data __initconst = {
.bitrate = 100000,
};
#define SD1_GPIO_WP IMX_GPIO_NR(2, 0)
#define SD1_GPIO_CD IMX_GPIO_NR(2, 1)
static const struct esdhc_platform_data mx25pdk_esdhc_pdata __initconst = {
.wp_gpio = SD1_GPIO_WP,
.cd_gpio = SD1_GPIO_CD,
.wp_type = ESDHC_WP_GPIO,
.cd_type = ESDHC_CD_GPIO,
};
static void __init mx25pdk_init(void)
{
imx25_soc_init();
mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
ARRAY_SIZE(mx25pdk_pads));
imx25_add_imx_uart0(&uart_pdata);
imx25_add_fsl_usb2_udc(&otg_device_pdata);
imx25_add_mxc_ehci_hs(&usbh2_pdata);
imx25_add_mxc_nand(&mx25pdk_nand_board_info);
imx25_add_imxdi_rtc();
imx25_add_imx_fb(&mx25pdk_fb_pdata);
imx25_add_imx2_wdt();
mx25pdk_fec_reset();
imx25_add_fec(&mx25_fec_pdata);
imx25_add_imx_keypad(&mx25pdk_keymap_data);
imx25_add_sdhci_esdhc_imx(0, &mx25pdk_esdhc_pdata);
imx25_add_imx_i2c0(&mx25_3ds_i2c0_data);
gpio_request_one(MX25PDK_CAN_PWDN, GPIOF_OUT_INIT_LOW, "can-pwdn");
imx25_add_flexcan0();
}
static void __init mx25pdk_timer_init(void)
{
mx25_clocks_init();
}
MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
/* Maintainer: Freescale Semiconductor, Inc. */
.atag_offset = 0x100,
.map_io = mx25_map_io,
.init_early = imx25_init_early,
.init_irq = mx25_init_irq,
.init_time = mx25pdk_timer_init,
.init_machine = mx25pdk_init,
.restart = mxc_restart,
MACHINE_END

2
arch/arm/mach-imx/mach-mx35_3ds.c
View File

@ -166,7 +166,7 @@ static struct platform_device *devices[] __initdata = {
&mx35pdk_flash,
};
static iomux_v3_cfg_t mx35pdk_pads[] = {
static const iomux_v3_cfg_t mx35pdk_pads[] __initconst = {
/* UART1 */
MX35_PAD_CTS1__UART1_CTS,
MX35_PAD_RTS1__UART1_RTS,

2
arch/arm/mach-imx/mach-pcm043.c
View File

@ -129,7 +129,7 @@ static struct platform_device *devices[] __initdata = {
&pcm043_flash,
};
static iomux_v3_cfg_t pcm043_pads[] = {
static const iomux_v3_cfg_t pcm043_pads[] __initconst = {
/* UART1 */
MX35_PAD_CTS1__UART1_CTS,
MX35_PAD_RTS1__UART1_RTS,

2
arch/arm/mach-imx/mach-vpr200.c
View File

@ -161,7 +161,7 @@ static struct i2c_board_info vpr200_i2c_devices[] = {
}
};
static iomux_v3_cfg_t vpr200_pads[] = {
static const iomux_v3_cfg_t vpr200_pads[] __initconst = {
/* UART1 */
MX35_PAD_TXD1__UART1_TXD_MUX,
MX35_PAD_RXD1__UART1_RXD_MUX,

89
arch/arm/mach-imx/mm-imx25.c
View File

@ -1,89 +0,0 @@
/*
* Copyright (C) 1999,2000 Arm Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* - add MX31 specific definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/pinctrl/machine.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
#include "common.h"
#include "devices/devices-common.h"
#include "hardware.h"
#include "iomux-v3.h"
#include "mx25.h"
/*
* This table defines static virtual address mappings for I/O regions.
* These are the mappings common across all MX25 boards.
*/
static struct map_desc mx25_io_desc[] __initdata = {
imx_map_entry(MX25, AVIC, MT_DEVICE_NONSHARED),
imx_map_entry(MX25, AIPS1, MT_DEVICE_NONSHARED),
imx_map_entry(MX25, AIPS2, MT_DEVICE_NONSHARED),
};
/*
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory mappings
* for the IO modules.
*/
void __init mx25_map_io(void)
{
iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc));
}
void __init imx25_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX25);
mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
}
void __init mx25_init_irq(void)
{
mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
}
static struct sdma_platform_data imx25_sdma_pdata __initdata = {
.fw_name = "sdma-imx25.bin",
};
static const struct resource imx25_audmux_res[] __initconst = {
DEFINE_RES_MEM(MX25_AUDMUX_BASE_ADDR, SZ_16K),
};
void __init imx25_soc_init(void)
{
mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
mxc_device_init();
/* i.mx25 has the i.mx35 type gpio */
mxc_register_gpio("imx35-gpio", 0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0);
mxc_register_gpio("imx35-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0);
mxc_register_gpio("imx35-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
mxc_register_gpio("imx35-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
pinctrl_provide_dummies();
/* i.mx25 has the i.mx35 type sdma */
imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
/* i.mx25 has the i.mx31 type audmux */
platform_device_register_simple("imx31-audmux", 0, imx25_audmux_res,
ARRAY_SIZE(imx25_audmux_res));
}

117
arch/arm/mach-imx/mx25.h
View File

@ -1,117 +0,0 @@
#ifndef __MACH_MX25_H__
#define __MACH_MX25_H__
#define MX25_AIPS1_BASE_ADDR 0x43f00000
#define MX25_AIPS1_SIZE SZ_1M
#define MX25_AIPS2_BASE_ADDR 0x53f00000
#define MX25_AIPS2_SIZE SZ_1M
#define MX25_AVIC_BASE_ADDR 0x68000000
#define MX25_AVIC_SIZE SZ_1M
#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000)
#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000)
#define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000)
#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000)
#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000)
#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000)
#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000)
#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000)
#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000)
#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000)
#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000)
#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000)
#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000)
#define MX25_UART1_BASE_ADDR 0x43f90000
#define MX25_UART2_BASE_ADDR 0x43f94000
#define MX25_AUDMUX_BASE_ADDR 0x43fb0000
#define MX25_UART3_BASE_ADDR 0x5000c000
#define MX25_UART4_BASE_ADDR 0x50008000
#define MX25_UART5_BASE_ADDR 0x5002c000
#define MX25_CSPI3_BASE_ADDR 0x50004000
#define MX25_CSPI2_BASE_ADDR 0x50010000
#define MX25_FEC_BASE_ADDR 0x50038000
#define MX25_SSI2_BASE_ADDR 0x50014000
#define MX25_SSI1_BASE_ADDR 0x50034000
#define MX25_NFC_BASE_ADDR 0xbb000000
#define MX25_IIM_BASE_ADDR 0x53ff0000
#define MX25_DRYICE_BASE_ADDR 0x53ffc000
#define MX25_ESDHC1_BASE_ADDR 0x53fb4000
#define MX25_ESDHC2_BASE_ADDR 0x53fb8000
#define MX25_LCDC_BASE_ADDR 0x53fbc000
#define MX25_KPP_BASE_ADDR 0x43fa8000
#define MX25_SDMA_BASE_ADDR 0x53fd4000
#define MX25_USB_BASE_ADDR 0x53ff4000
#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000)
/*
* The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200
* for the host controller. Early documentation drafts specified 0x400 and
* Freescale internal sources confirm only the latter value to work.
*/
#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400)
#define MX25_CSI_BASE_ADDR 0x53ff8000
#define MX25_IO_P2V(x) IMX_IO_P2V(x)
#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
/*
* Interrupt numbers
*/
#include <asm/irq.h>
#define MX25_INT_CSPI3 (NR_IRQS_LEGACY + 0)
#define MX25_INT_I2C1 (NR_IRQS_LEGACY + 3)
#define MX25_INT_I2C2 (NR_IRQS_LEGACY + 4)
#define MX25_INT_UART4 (NR_IRQS_LEGACY + 5)
#define MX25_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
#define MX25_INT_ESDHC1 (NR_IRQS_LEGACY + 9)
#define MX25_INT_I2C3 (NR_IRQS_LEGACY + 10)
#define MX25_INT_SSI2 (NR_IRQS_LEGACY + 11)
#define MX25_INT_SSI1 (NR_IRQS_LEGACY + 12)
#define MX25_INT_CSPI2 (NR_IRQS_LEGACY + 13)
#define MX25_INT_CSPI1 (NR_IRQS_LEGACY + 14)
#define MX25_INT_GPIO3 (NR_IRQS_LEGACY + 16)
#define MX25_INT_CSI (NR_IRQS_LEGACY + 17)
#define MX25_INT_UART3 (NR_IRQS_LEGACY + 18)
#define MX25_INT_GPIO4 (NR_IRQS_LEGACY + 23)
#define MX25_INT_KPP (NR_IRQS_LEGACY + 24)
#define MX25_INT_DRYICE (NR_IRQS_LEGACY + 25)
#define MX25_INT_PWM1 (NR_IRQS_LEGACY + 26)
#define MX25_INT_UART2 (NR_IRQS_LEGACY + 32)
#define MX25_INT_NFC (NR_IRQS_LEGACY + 33)
#define MX25_INT_SDMA (NR_IRQS_LEGACY + 34)
#define MX25_INT_USB_HS (NR_IRQS_LEGACY + 35)
#define MX25_INT_PWM2 (NR_IRQS_LEGACY + 36)
#define MX25_INT_USB_OTG (NR_IRQS_LEGACY + 37)
#define MX25_INT_LCDC (NR_IRQS_LEGACY + 39)
#define MX25_INT_UART5 (NR_IRQS_LEGACY + 40)
#define MX25_INT_PWM3 (NR_IRQS_LEGACY + 41)
#define MX25_INT_PWM4 (NR_IRQS_LEGACY + 42)
#define MX25_INT_CAN1 (NR_IRQS_LEGACY + 43)
#define MX25_INT_CAN2 (NR_IRQS_LEGACY + 44)
#define MX25_INT_UART1 (NR_IRQS_LEGACY + 45)
#define MX25_INT_GPIO2 (NR_IRQS_LEGACY + 51)
#define MX25_INT_GPIO1 (NR_IRQS_LEGACY + 52)
#define MX25_INT_GPT1 (NR_IRQS_LEGACY + 54)
#define MX25_INT_FEC (NR_IRQS_LEGACY + 57)
#define MX25_DMA_REQ_SSI2_RX1 22
#define MX25_DMA_REQ_SSI2_TX1 23
#define MX25_DMA_REQ_SSI2_RX0 24
#define MX25_DMA_REQ_SSI2_TX0 25
#define MX25_DMA_REQ_SSI1_RX1 26
#define MX25_DMA_REQ_SSI1_TX1 27
#define MX25_DMA_REQ_SSI1_RX0 28
#define MX25_DMA_REQ_SSI1_TX0 29
#ifndef __ASSEMBLY__
extern int mx25_revision(void);
#endif
#endif /* ifndef __MACH_MX25_H__ */

6
arch/arm/mach-imx/pm-imx6.c
View File

@ -310,10 +310,12 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
* Low-Power mode.
* 3) Software should mask IRQ #32 right after CCM Low-Power mode
* is set (set bits 0-1 of CCM_CLPCR).
*
* Note that IRQ #32 is GIC SPI #0.
*/
imx_gpc_hwirq_unmask(32);
imx_gpc_hwirq_unmask(0);
writel_relaxed(val, ccm_base + CLPCR);
imx_gpc_hwirq_mask(32);
imx_gpc_hwirq_mask(0);
return 0;
}

13
drivers/bus/imx-weim.c
View File

@ -142,7 +142,7 @@ static int __init weim_parse_dt(struct platform_device *pdev,
&pdev->dev);
const struct imx_weim_devtype *devtype = of_id->data;
struct device_node *child;
int ret;
int ret, have_child = 0;
if (devtype == &imx50_weim_devtype) {
ret = imx_weim_gpr_setup(pdev);
@ -155,14 +155,15 @@ static int __init weim_parse_dt(struct platform_device *pdev,
continue;
ret = weim_timing_setup(child, base, devtype);
if (ret) {
dev_err(&pdev->dev, "%s set timing failed.\n",
if (ret)
dev_warn(&pdev->dev, "%s set timing failed.\n",
child->full_name);
return ret;
}
else
have_child = 1;
}
ret = of_platform_populate(pdev->dev.of_node,
if (have_child)
ret = of_platform_populate(pdev->dev.of_node,
of_default_bus_match_table,
NULL, &pdev->dev);
if (ret)

1
drivers/irqchip/Makefile
View File

@ -37,6 +37,7 @@ obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o
obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o
obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o
obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
obj-$(CONFIG_SOC_VF610) += irq-vf610-mscm-ir.o
obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o
obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o
obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o

212
drivers/irqchip/irq-vf610-mscm-ir.c Normal file
View File

@ -0,0 +1,212 @@
/*
* Copyright (C) 2014-2015 Toradex AG
* Author: Stefan Agner <stefan@agner.ch>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*
* IRQ chip driver for MSCM interrupt router available on Vybrid SoC's.
* The interrupt router is between the CPU's interrupt controller and the
* peripheral. The router allows to route the peripheral interrupts to
* one of the two available CPU's on Vybrid VF6xx SoC's (Cortex-A5 or
* Cortex-M4). The router will be configured transparently on a IRQ
* request.
*
* o All peripheral interrupts of the Vybrid SoC can be routed to
* CPU 0, CPU 1 or both. The routing is useful for dual-core
* variants of Vybrid SoC such as VF6xx. This driver routes the
* requested interrupt to the CPU currently running on.
*
* o It is required to setup the interrupt router even on single-core
* variants of Vybrid.
*/
#include <linux/cpu_pm.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/mfd/syscon.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/regmap.h>
#include "irqchip.h"
#define MSCM_CPxNUM 0x4
#define MSCM_IRSPRC(n) (0x80 + 2 * (n))
#define MSCM_IRSPRC_CPEN_MASK 0x3
#define MSCM_IRSPRC_NUM 112
struct vf610_mscm_ir_chip_data {
void __iomem *mscm_ir_base;
u16 cpu_mask;
u16 saved_irsprc[MSCM_IRSPRC_NUM];
};
static struct vf610_mscm_ir_chip_data *mscm_ir_data;
static inline void vf610_mscm_ir_save(struct vf610_mscm_ir_chip_data *data)
{
int i;
for (i = 0; i < MSCM_IRSPRC_NUM; i++)
data->saved_irsprc[i] = readw_relaxed(data->mscm_ir_base + MSCM_IRSPRC(i));
}
static inline void vf610_mscm_ir_restore(struct vf610_mscm_ir_chip_data *data)
{
int i;
for (i = 0; i < MSCM_IRSPRC_NUM; i++)
writew_relaxed(data->saved_irsprc[i], data->mscm_ir_base + MSCM_IRSPRC(i));
}
static int vf610_mscm_ir_notifier(struct notifier_block *self,
unsigned long cmd, void *v)
{
switch (cmd) {
case CPU_CLUSTER_PM_ENTER:
vf610_mscm_ir_save(mscm_ir_data);
break;
case CPU_CLUSTER_PM_ENTER_FAILED:
case CPU_CLUSTER_PM_EXIT:
vf610_mscm_ir_restore(mscm_ir_data);
break;
}
return NOTIFY_OK;
}
static struct notifier_block mscm_ir_notifier_block = {
.notifier_call = vf610_mscm_ir_notifier,
};
static void vf610_mscm_ir_enable(struct irq_data *data)
{
irq_hw_number_t hwirq = data->hwirq;
struct vf610_mscm_ir_chip_data *chip_data = data->chip_data;
u16 irsprc;
irsprc = readw_relaxed(chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
irsprc &= MSCM_IRSPRC_CPEN_MASK;
WARN_ON(irsprc & ~chip_data->cpu_mask);
writew_relaxed(chip_data->cpu_mask,
chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
irq_chip_unmask_parent(data);
}
static void vf610_mscm_ir_disable(struct irq_data *data)
{
irq_hw_number_t hwirq = data->hwirq;
struct vf610_mscm_ir_chip_data *chip_data = data->chip_data;
writew_relaxed(0x0, chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
irq_chip_mask_parent(data);
}
static struct irq_chip vf610_mscm_ir_irq_chip = {
.name = "mscm-ir",
.irq_mask = irq_chip_mask_parent,
.irq_unmask = irq_chip_unmask_parent,
.irq_eoi = irq_chip_eoi_parent,
.irq_enable = vf610_mscm_ir_enable,
.irq_disable = vf610_mscm_ir_disable,
.irq_retrigger = irq_chip_retrigger_hierarchy,
.irq_set_affinity = irq_chip_set_affinity_parent,
};
static int vf610_mscm_ir_domain_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *arg)
{
int i;
irq_hw_number_t hwirq;
struct of_phandle_args *irq_data = arg;
struct of_phandle_args gic_data;
if (irq_data->args_count != 2)
return -EINVAL;
hwirq = irq_data->args[0];
for (i = 0; i < nr_irqs; i++)
irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
&vf610_mscm_ir_irq_chip,
domain->host_data);
gic_data.np = domain->parent->of_node;
gic_data.args_count = 3;
gic_data.args[0] = GIC_SPI;
gic_data.args[1] = irq_data->args[0];
gic_data.args[2] = irq_data->args[1];
return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_data);
}
static const struct irq_domain_ops mscm_irq_domain_ops = {
.xlate = irq_domain_xlate_twocell,
.alloc = vf610_mscm_ir_domain_alloc,
.free = irq_domain_free_irqs_common,
};
static int __init vf610_mscm_ir_of_init(struct device_node *node,
struct device_node *parent)
{
struct irq_domain *domain, *domain_parent;
struct regmap *mscm_cp_regmap;
int ret, cpuid;
domain_parent = irq_find_host(parent);
if (!domain_parent) {
pr_err("vf610_mscm_ir: interrupt-parent not found\n");
return -EINVAL;
}
mscm_ir_data = kzalloc(sizeof(*mscm_ir_data), GFP_KERNEL);
if (!mscm_ir_data)
return -ENOMEM;
mscm_ir_data->mscm_ir_base = of_io_request_and_map(node, 0, "mscm-ir");
if (!mscm_ir_data->mscm_ir_base) {
pr_err("vf610_mscm_ir: unable to map mscm register\n");
ret = -ENOMEM;
goto out_free;
}
mscm_cp_regmap = syscon_regmap_lookup_by_phandle(node, "fsl,cpucfg");
if (IS_ERR(mscm_cp_regmap)) {
ret = PTR_ERR(mscm_cp_regmap);
pr_err("vf610_mscm_ir: regmap lookup for cpucfg failed\n");
goto out_unmap;
}
regmap_read(mscm_cp_regmap, MSCM_CPxNUM, &cpuid);
mscm_ir_data->cpu_mask = 0x1 << cpuid;
domain = irq_domain_add_hierarchy(domain_parent, 0,
MSCM_IRSPRC_NUM, node,
&mscm_irq_domain_ops, mscm_ir_data);
if (!domain) {
ret = -ENOMEM;
goto out_unmap;
}
cpu_pm_register_notifier(&mscm_ir_notifier_block);
return 0;
out_unmap:
iounmap(mscm_ir_data->mscm_ir_base);
out_free:
kfree(mscm_ir_data);
return ret;
}
IRQCHIP_DECLARE(vf610_mscm_ir, "fsl,vf610-mscm-ir", vf610_mscm_ir_of_init);

5
include/dt-bindings/clock/imx6qdl-clock.h
View File

@ -248,6 +248,9 @@
#define IMX6QDL_PLL6_BYPASS 235
#define IMX6QDL_PLL7_BYPASS 236
#define IMX6QDL_CLK_GPT_3M 237
#define IMX6QDL_CLK_END 238
#define IMX6QDL_CLK_VIDEO_27M 238
#define IMX6QDL_CLK_MIPI_CORE_CFG 239
#define IMX6QDL_CLK_MIPI_IPG 240
#define IMX6QDL_CLK_END 241
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */

1
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
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@ -207,6 +207,7 @@
#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6)
#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0 (0x2 << 6)
#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1 (0x3 << 6)
#define IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT 4
#define IMX6Q_GPR3_MIPI_MUX_CTL_MASK (0x3 << 4)
#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0 (0x0 << 4)
#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1 (0x1 << 4)