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arm64/mte: Make TCF0 naming and field values more standard
In preparation for automatic generation of SCTLR_EL1 register definitions make the macros used to define SCTLR_EL1.TCF0 and the enumeration values it has more standard so they can be used with FIELD_PREP() via the newly defined SYS_FIELD_PREP_ helpers. Since the field also exists in SCTLR_EL2 with the same values also rename the macros to SCTLR_ELx rather than SCTLR_EL1. There should be no functional change as a result of this patch. Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com Link: https://lore.kernel.org/r/20220503170233.507788-3-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -678,10 +678,10 @@
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#define SCTLR_EL1_ATA0 (BIT(42))
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#define SCTLR_EL1_TCF0_SHIFT 38
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#define SCTLR_EL1_TCF0_NONE (UL(0x0) << SCTLR_EL1_TCF0_SHIFT)
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#define SCTLR_EL1_TCF0_SYNC (UL(0x1) << SCTLR_EL1_TCF0_SHIFT)
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#define SCTLR_EL1_TCF0_ASYNC (UL(0x2) << SCTLR_EL1_TCF0_SHIFT)
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#define SCTLR_EL1_TCF0_ASYMM (UL(0x3) << SCTLR_EL1_TCF0_SHIFT)
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#define SCTLR_EL1_TCF0_NONE (UL(0x0))
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#define SCTLR_EL1_TCF0_SYNC (UL(0x1))
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#define SCTLR_EL1_TCF0_ASYNC (UL(0x2))
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#define SCTLR_EL1_TCF0_ASYMM (UL(0x3))
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#define SCTLR_EL1_TCF0_MASK (UL(0x3) << SCTLR_EL1_TCF0_SHIFT)
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#define SCTLR_EL1_BT1 (BIT(36))
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@ -216,11 +216,11 @@ static void mte_update_sctlr_user(struct task_struct *task)
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* default order.
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*/
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if (resolved_mte_tcf & MTE_CTRL_TCF_ASYMM)
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sctlr |= SCTLR_EL1_TCF0_ASYMM;
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sctlr |= SYS_FIELD_PREP_ENUM(SCTLR_EL1, TCF0, ASYMM);
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else if (resolved_mte_tcf & MTE_CTRL_TCF_ASYNC)
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sctlr |= SCTLR_EL1_TCF0_ASYNC;
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sctlr |= SYS_FIELD_PREP_ENUM(SCTLR_EL1, TCF0, ASYNC);
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else if (resolved_mte_tcf & MTE_CTRL_TCF_SYNC)
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sctlr |= SCTLR_EL1_TCF0_SYNC;
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sctlr |= SYS_FIELD_PREP_ENUM(SCTLR_EL1, TCF0, SYNC);
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task->thread.sctlr_user = sctlr;
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}
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