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ASoC: tlv320aic32x4: Dynamically Determine Clocking
The existing code uses a static lookup table to determine the settings of the various clock devices on board the chip. This is limiting in a couple of ways. First, this doesn't allow for any master clock rates other than the three that have been precalculated. Additionally, new sample rates are difficult to add to the table. Witness that the chip is capable of 192000 Hz sampling, but it is not provided by this driver. Last, if the driver is clocked by something that isn't a crystal, the upstream clock may not be able to achieve exactly the rate requested in the driver. This will mean that clocking will be slightly off for the sampling clock or that it won't work at all. This patch determines the settings for all of the clocks at runtime considering the real conditions of the clocks in the system. The rules for the clocks are in TI's SLAA557 application guide on pages 37, 51 and 77. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Annaliese McDermond
Mark Brown
parent
fbafbf6517
commit
96c3bb0023
@ -47,21 +47,6 @@
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#include "tlv320aic32x4.h"
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struct aic32x4_rate_divs {
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u32 mclk;
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u32 rate;
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unsigned long pll_rate;
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u16 dosr;
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unsigned long ndac_rate;
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unsigned long mdac_rate;
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u8 aosr;
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unsigned long nadc_rate;
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unsigned long madc_rate;
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unsigned long bdiv_rate;
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u8 r_block;
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u8 p_block;
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};
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struct aic32x4_priv {
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struct regmap *regmap;
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u32 sysclk;
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@ -307,58 +292,6 @@ static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
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0, 0x0F, 0),
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};
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static const struct aic32x4_rate_divs aic32x4_divs[] = {
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/* 8k rate */
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{ 12000000, 8000, 57120000, 768, 18432000, 6144000, 128, 18432000,
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1024000, 256000, 1, 1 },
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{ 24000000, 8000, 57120000, 768, 6144000, 6144000, 64, 2048000,
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512000, 256000, 1, 1 },
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{ 25000000, 8000, 32620000, 768, 6144000, 6144000, 64, 2048000,
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512000, 256000, 1, 1 },
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/* 11.025k rate */
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{ 12000000, 11025, 44217600, 512, 11289600, 5644800, 128, 11289600,
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1411200, 352800, 1, 1 },
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{ 24000000, 11025, 44217600, 512, 5644800, 5644800, 64, 2822400,
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705600, 352800, 1, 1 },
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/* 16k rate */
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{ 12000000, 16000, 57120000, 384, 18432000, 6144000, 128, 18432000,
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2048000, 512000, 1, 1 },
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{ 24000000, 16000, 57120000, 384, 6144000, 6144000, 64, 5120000,
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1024000, 512000, 1, 1 },
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{ 25000000, 16000, 32620000, 384, 6144000, 6144000, 64, 5120000,
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1024000, 512000, 1, 1 },
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/* 22.05k rate */
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{ 12000000, 22050, 44217600, 256, 22579200, 5644800, 128, 22579200,
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2822400, 705600, 1, 1 },
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{ 24000000, 22050, 44217600, 256, 5644800, 5644800, 64, 5644800,
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1411200, 705600, 1, 1 },
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{ 25000000, 22050, 19713750, 256, 5644800, 5644800, 64, 5644800,
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1411200, 705600, 1, 1 },
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/* 32k rate */
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{ 12000000, 32000, 14112000, 192, 43008000, 6144000, 64, 43008000,
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2048000, 1024000, 1, 1 },
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{ 24000000, 32000, 14112000, 192, 12288000, 6144000, 64, 12288000,
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2048000, 1024000, 1, 1 },
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/* 44.1k rate */
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{ 12000000, 44100, 44217600, 128, 45158400, 5644800, 128, 45158400,
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5644800, 1411200, 1, 1 },
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{ 24000000, 44100, 44217600, 128, 11289600, 5644800, 64, 11289600,
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2822400, 1411200, 1, 1 },
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{ 25000000, 44100, 19713750, 128, 11289600, 5644800, 64, 11289600,
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2822400, 1411200, 1, 1 },
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/* 48k rate */
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{ 12000000, 48000, 18432000, 128, 49152000, 6144000, 128, 49152000,
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6144000, 1536000, 1, 1 },
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{ 24000000, 48000, 18432000, 128, 12288000, 6144000, 64, 12288000,
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3072000, 1536000, 1, 1 },
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{ 25000000, 48000, 75626250, 128, 12288000, 6144000, 64, 12288000,
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3072000, 1536000, 1, 1 },
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/* 96k rate */
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{ 25000000, 96000, 75626250, 64, 24576000, 6144000, 64, 24576000,
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6144000, 3072000, 1, 9 },
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};
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static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
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SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
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SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
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@ -630,20 +563,6 @@ const struct regmap_config aic32x4_regmap_config = {
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};
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EXPORT_SYMBOL(aic32x4_regmap_config);
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static inline int aic32x4_get_divs(int mclk, int rate)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) {
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if ((aic32x4_divs[i].rate == rate)
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&& (aic32x4_divs[i].mclk == mclk)) {
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return i;
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}
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}
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printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n");
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return -EINVAL;
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}
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static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
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int clk_id, unsigned int freq, int dir)
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{
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@ -745,11 +664,17 @@ static int aic32x4_set_processing_blocks(struct snd_soc_component *component,
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}
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static int aic32x4_setup_clocks(struct snd_soc_component *component,
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unsigned int sample_rate,
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unsigned int parent_rate)
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unsigned int sample_rate)
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{
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int i;
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u8 aosr;
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u16 dosr;
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u8 adc_resource_class, dac_resource_class;
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u8 madc, nadc, mdac, ndac, max_nadc, min_mdac, max_ndac;
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u8 dosr_increment;
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u16 max_dosr, min_dosr;
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unsigned long mclk_rate, adc_clock_rate, dac_clock_rate;
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int ret;
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struct clk *mclk;
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struct clk_bulk_data clocks[] = {
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{ .id = "pll" },
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@ -759,30 +684,89 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component,
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{ .id = "mdac" },
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{ .id = "bdiv" },
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};
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i = aic32x4_get_divs(parent_rate, sample_rate);
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if (i < 0) {
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printk(KERN_ERR "aic32x4: sampling rate not supported\n");
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return i;
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}
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ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
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if (ret)
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return ret;
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clk_set_rate(clocks[0].clk, aic32x4_divs[i].pll_rate);
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clk_set_rate(clocks[1].clk, aic32x4_divs[i].nadc_rate);
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clk_set_rate(clocks[2].clk, aic32x4_divs[i].madc_rate);
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clk_set_rate(clocks[3].clk, aic32x4_divs[i].ndac_rate);
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clk_set_rate(clocks[4].clk, aic32x4_divs[i].mdac_rate);
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clk_set_rate(clocks[5].clk, aic32x4_divs[i].bdiv_rate);
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mclk = clk_get_parent(clocks[1].clk);
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mclk_rate = clk_get_rate(mclk);
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aic32x4_set_aosr(component, aic32x4_divs[i].aosr);
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aic32x4_set_dosr(component, aic32x4_divs[i].dosr);
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if (sample_rate <= 48000) {
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aosr = 128;
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adc_resource_class = 6;
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dac_resource_class = 8;
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dosr_increment = 8;
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aic32x4_set_processing_blocks(component, 1, 1);
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} else if (sample_rate <= 96000) {
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aosr = 64;
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adc_resource_class = 6;
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dac_resource_class = 8;
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dosr_increment = 4;
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aic32x4_set_processing_blocks(component, 1, 9);
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} else if (sample_rate == 192000) {
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aosr = 32;
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adc_resource_class = 3;
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dac_resource_class = 4;
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dosr_increment = 2;
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aic32x4_set_processing_blocks(component, 13, 19);
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} else {
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dev_err(component->dev, "Sampling rate not supported\n");
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return -EINVAL;
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}
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aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block);
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madc = DIV_ROUND_UP((32 * adc_resource_class), aosr);
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max_dosr = (AIC32X4_MAX_DOSR_FREQ / sample_rate / dosr_increment) *
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dosr_increment;
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min_dosr = (AIC32X4_MIN_DOSR_FREQ / sample_rate / dosr_increment) *
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dosr_increment;
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max_nadc = AIC32X4_MAX_CODEC_CLKIN_FREQ / (madc * aosr * sample_rate);
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return 0;
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for (nadc = max_nadc; nadc > 0; --nadc) {
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adc_clock_rate = nadc * madc * aosr * sample_rate;
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for (dosr = max_dosr; dosr >= min_dosr;
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dosr -= dosr_increment) {
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min_mdac = DIV_ROUND_UP((32 * dac_resource_class), dosr);
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max_ndac = AIC32X4_MAX_CODEC_CLKIN_FREQ /
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(min_mdac * dosr * sample_rate);
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for (mdac = min_mdac; mdac <= 128; ++mdac) {
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for (ndac = max_ndac; ndac > 0; --ndac) {
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dac_clock_rate = ndac * mdac * dosr *
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sample_rate;
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if (dac_clock_rate == adc_clock_rate) {
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if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0)
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continue;
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clk_set_rate(clocks[0].clk,
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dac_clock_rate);
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clk_set_rate(clocks[1].clk,
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sample_rate * aosr *
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madc);
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clk_set_rate(clocks[2].clk,
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sample_rate * aosr);
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aic32x4_set_aosr(component,
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aosr);
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clk_set_rate(clocks[3].clk,
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sample_rate * dosr *
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mdac);
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clk_set_rate(clocks[4].clk,
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sample_rate * dosr);
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aic32x4_set_dosr(component,
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dosr);
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clk_set_rate(clocks[5].clk,
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sample_rate * 32);
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return 0;
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}
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}
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}
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}
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}
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dev_err(component->dev,
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"Could not set clocks to support sample rate.\n");
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return -EINVAL;
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}
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static int aic32x4_hw_params(struct snd_pcm_substream *substream,
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@ -794,7 +778,7 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream,
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u8 iface1_reg = 0;
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u8 dacsetup_reg = 0;
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aic32x4_setup_clocks(component, params_rate(params), aic32x4->sysclk);
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aic32x4_setup_clocks(component, params_rate(params));
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switch (params_width(params)) {
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case 16:
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@ -211,7 +211,9 @@ int aic32x4_register_clocks(struct device *dev, const char *mclk_name);
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#define AIC32X4_DIV_MASK GENMASK(6, 0)
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/* Clock Limits */
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#define AIC32X4_MAX_DOSR_FREQ 6200000
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#define AIC32X4_MIN_DOSR_FREQ 2800000
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#define AIC32X4_MAX_CODEC_CLKIN_FREQ 110000000
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#define AIC32X4_MAX_PLL_CLKIN 20000000
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#endif /* _TLV320AIC32X4_H */
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