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- Add CONFIG_ option for every hw CPU mitigation. The intent is to support
configurations and scenarios where the mitigations code is irrelevant - Other small fixlets and improvements -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmbfDhUACgkQEsHwGGHe VUrF9A//UkVKmIihXXak0GPqFhu8XrWeYlmwLxWe/uIy2hZCLp9L7n4pg0Ikxqz3 9D9hYk+Jykfu/jsv0sR6LH6OAUTlJi+P0w3x3VeL1sgFPUkwFtOaN2v/t5H3SW5r l+VQpdUXPmLH6QbhvT84U6L/OQYr2cjhiYro47uwM9vO/SNao4HcbC/pdBr2dwxM KzzA9sEDg3Le391phIhEOIogA1lPNV7KMScg2VjPTqQzEJ3NQVzyYmqjPO70sN9F sAuksdF+rnPjc9K/W+qUcvlp8e9lDB8g0oPlyoOeubjXsnZU5YchriPdBbyAl0dJ bjpftXIrBj8Vtmh7Tc0Jx2tlMFXNT5FrzcqdD4sviLnhrKEJSkwAoFgIMp5A+tN8 Kl8MrlABO8I8+zGRQB7TzhwaCC4AxCqUS3UEcYd4CBf5AWqT5i12ijbtIxPtdpG4 5itngIV4HT8casudpC8i8OTjOTggorMa7Pu/bQULhnZwagH8chlBdoOlKKQVkeVG FUi+L/BljL9mASic7NRZI11tk44m9xWWkbbJOPlZaGJw9YzGrxD0YOfhbgcc9iaX SOUMVJEhJVJMBISGiBUQDB6r51ee6B8RKJ3ByxzpAbwsUR9cXyfSYfUyE5reQJy9 3luj/iorL3guYU6EGEAtvbuTLGbKqybrV6zOB/QRXHWyhtUgrUA= =GFld -----END PGP SIGNATURE----- Merge tag 'x86_bugs_for_v6.12_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 hw mitigation updates from Borislav Petkov: - Add CONFIG_ option for every hw CPU mitigation. The intent is to support configurations and scenarios where the mitigations code is irrelevant - Other small fixlets and improvements * tag 'x86_bugs_for_v6.12_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/bugs: Fix handling when SRSO mitigation is disabled x86/bugs: Add missing NO_SSB flag Documentation/srso: Document a method for checking safe RET operates properly x86/bugs: Add a separate config for GDS x86/bugs: Remove GDS Force Kconfig option x86/bugs: Add a separate config for SSB x86/bugs: Add a separate config for Spectre V2 x86/bugs: Add a separate config for SRBDS x86/bugs: Add a separate config for Spectre v1 x86/bugs: Add a separate config for RETBLEED x86/bugs: Add a separate config for L1TF x86/bugs: Add a separate config for MMIO Stable Data x86/bugs: Add a separate config for TAA x86/bugs: Add a separate config for MDS
This commit is contained in:
Linus Torvalds
commit
963d0d60d6
@ -158,3 +158,72 @@ poisoned BTB entry and using that safe one for all function returns.
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In older Zen1 and Zen2, this is accomplished using a reinterpretation
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technique similar to Retbleed one: srso_untrain_ret() and
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srso_safe_ret().
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Checking the safe RET mitigation actually works
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-----------------------------------------------
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In case one wants to validate whether the SRSO safe RET mitigation works
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on a kernel, one could use two performance counters
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* PMC_0xc8 - Count of RET/RET lw retired
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* PMC_0xc9 - Count of RET/RET lw retired mispredicted
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and compare the number of RETs retired properly vs those retired
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mispredicted, in kernel mode. Another way of specifying those events
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is::
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# perf list ex_ret_near_ret
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List of pre-defined events (to be used in -e or -M):
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core:
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ex_ret_near_ret
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[Retired Near Returns]
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ex_ret_near_ret_mispred
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[Retired Near Returns Mispredicted]
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Either the command using the event mnemonics::
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# perf stat -e ex_ret_near_ret:k -e ex_ret_near_ret_mispred:k sleep 10s
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or using the raw PMC numbers::
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# perf stat -e cpu/event=0xc8,umask=0/k -e cpu/event=0xc9,umask=0/k sleep 10s
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should give the same amount. I.e., every RET retired should be
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mispredicted::
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[root@brent: ~/kernel/linux/tools/perf> ./perf stat -e cpu/event=0xc8,umask=0/k -e cpu/event=0xc9,umask=0/k sleep 10s
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Performance counter stats for 'sleep 10s':
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137,167 cpu/event=0xc8,umask=0/k
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137,173 cpu/event=0xc9,umask=0/k
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10.004110303 seconds time elapsed
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0.000000000 seconds user
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0.004462000 seconds sys
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vs the case when the mitigation is disabled (spec_rstack_overflow=off)
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or not functioning properly, showing usually a lot smaller number of
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mispredicted retired RETs vs the overall count of retired RETs during
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a workload::
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[root@brent: ~/kernel/linux/tools/perf> ./perf stat -e cpu/event=0xc8,umask=0/k -e cpu/event=0xc9,umask=0/k sleep 10s
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Performance counter stats for 'sleep 10s':
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201,627 cpu/event=0xc8,umask=0/k
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4,074 cpu/event=0xc9,umask=0/k
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10.003267252 seconds time elapsed
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0.002729000 seconds user
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0.000000000 seconds sys
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Also, there is a selftest which performs the above, go to
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tools/testing/selftests/x86/ and do::
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make srso
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./srso
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124
arch/x86/Kconfig
124
arch/x86/Kconfig
@ -2610,24 +2610,15 @@ config MITIGATION_SLS
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against straight line speculation. The kernel image might be slightly
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larger.
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config MITIGATION_GDS_FORCE
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bool "Force GDS Mitigation"
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config MITIGATION_GDS
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bool "Mitigate Gather Data Sampling"
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depends on CPU_SUP_INTEL
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default n
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default y
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help
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Gather Data Sampling (GDS) is a hardware vulnerability which allows
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unprivileged speculative access to data which was previously stored in
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vector registers.
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This option is equivalent to setting gather_data_sampling=force on the
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command line. The microcode mitigation is used if present, otherwise
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AVX is disabled as a mitigation. On affected systems that are missing
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the microcode any userspace code that unconditionally uses AVX will
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break with this option set.
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Setting this option on systems not vulnerable to GDS has no effect.
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If in doubt, say N.
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Enable mitigation for Gather Data Sampling (GDS). GDS is a hardware
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vulnerability which allows unprivileged speculative access to data
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which was previously stored in vector registers. The attacker uses gather
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instructions to infer the stale vector register data.
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config MITIGATION_RFDS
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bool "RFDS Mitigation"
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@ -2650,6 +2641,107 @@ config MITIGATION_SPECTRE_BHI
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indirect branches.
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See <file:Documentation/admin-guide/hw-vuln/spectre.rst>
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config MITIGATION_MDS
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bool "Mitigate Microarchitectural Data Sampling (MDS) hardware bug"
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depends on CPU_SUP_INTEL
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default y
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help
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Enable mitigation for Microarchitectural Data Sampling (MDS). MDS is
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a hardware vulnerability which allows unprivileged speculative access
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to data which is available in various CPU internal buffers.
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See also <file:Documentation/admin-guide/hw-vuln/mds.rst>
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config MITIGATION_TAA
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bool "Mitigate TSX Asynchronous Abort (TAA) hardware bug"
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depends on CPU_SUP_INTEL
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default y
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help
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Enable mitigation for TSX Asynchronous Abort (TAA). TAA is a hardware
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vulnerability that allows unprivileged speculative access to data
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which is available in various CPU internal buffers by using
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asynchronous aborts within an Intel TSX transactional region.
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See also <file:Documentation/admin-guide/hw-vuln/tsx_async_abort.rst>
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config MITIGATION_MMIO_STALE_DATA
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bool "Mitigate MMIO Stale Data hardware bug"
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depends on CPU_SUP_INTEL
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default y
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help
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Enable mitigation for MMIO Stale Data hardware bugs. Processor MMIO
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Stale Data Vulnerabilities are a class of memory-mapped I/O (MMIO)
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vulnerabilities that can expose data. The vulnerabilities require the
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attacker to have access to MMIO.
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See also
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<file:Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst>
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config MITIGATION_L1TF
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bool "Mitigate L1 Terminal Fault (L1TF) hardware bug"
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depends on CPU_SUP_INTEL
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default y
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help
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Mitigate L1 Terminal Fault (L1TF) hardware bug. L1 Terminal Fault is a
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hardware vulnerability which allows unprivileged speculative access to data
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available in the Level 1 Data Cache.
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See <file:Documentation/admin-guide/hw-vuln/l1tf.rst
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config MITIGATION_RETBLEED
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bool "Mitigate RETBleed hardware bug"
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depends on (CPU_SUP_INTEL && MITIGATION_SPECTRE_V2) || MITIGATION_UNRET_ENTRY || MITIGATION_IBPB_ENTRY
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default y
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help
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Enable mitigation for RETBleed (Arbitrary Speculative Code Execution
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with Return Instructions) vulnerability. RETBleed is a speculative
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execution attack which takes advantage of microarchitectural behavior
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in many modern microprocessors, similar to Spectre v2. An
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unprivileged attacker can use these flaws to bypass conventional
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memory security restrictions to gain read access to privileged memory
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that would otherwise be inaccessible.
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config MITIGATION_SPECTRE_V1
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bool "Mitigate SPECTRE V1 hardware bug"
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default y
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help
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Enable mitigation for Spectre V1 (Bounds Check Bypass). Spectre V1 is a
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class of side channel attacks that takes advantage of speculative
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execution that bypasses conditional branch instructions used for
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memory access bounds check.
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See also <file:Documentation/admin-guide/hw-vuln/spectre.rst>
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config MITIGATION_SPECTRE_V2
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bool "Mitigate SPECTRE V2 hardware bug"
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default y
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help
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Enable mitigation for Spectre V2 (Branch Target Injection). Spectre
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V2 is a class of side channel attacks that takes advantage of
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indirect branch predictors inside the processor. In Spectre variant 2
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attacks, the attacker can steer speculative indirect branches in the
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victim to gadget code by poisoning the branch target buffer of a CPU
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used for predicting indirect branch addresses.
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See also <file:Documentation/admin-guide/hw-vuln/spectre.rst>
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config MITIGATION_SRBDS
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bool "Mitigate Special Register Buffer Data Sampling (SRBDS) hardware bug"
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depends on CPU_SUP_INTEL
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default y
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help
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Enable mitigation for Special Register Buffer Data Sampling (SRBDS).
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SRBDS is a hardware vulnerability that allows Microarchitectural Data
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Sampling (MDS) techniques to infer values returned from special
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register accesses. An unprivileged user can extract values returned
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from RDRAND and RDSEED executed on another core or sibling thread
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using MDS techniques.
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See also
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<file:Documentation/admin-guide/hw-vuln/special-register-buffer-data-sampling.rst>
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config MITIGATION_SSB
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bool "Mitigate Speculative Store Bypass (SSB) hardware bug"
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default y
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help
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Enable mitigation for Speculative Store Bypass (SSB). SSB is a
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hardware security vulnerability and its exploitation takes advantage
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of speculative execution in a similar way to the Meltdown and Spectre
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security vulnerabilities.
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endif
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config ARCH_HAS_ADD_PAGES
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@ -233,7 +233,8 @@ static void x86_amd_ssb_disable(void)
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#define pr_fmt(fmt) "MDS: " fmt
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/* Default mitigation for MDS-affected CPUs */
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static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL;
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static enum mds_mitigations mds_mitigation __ro_after_init =
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IS_ENABLED(CONFIG_MITIGATION_MDS) ? MDS_MITIGATION_FULL : MDS_MITIGATION_OFF;
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static bool mds_nosmt __ro_after_init = false;
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static const char * const mds_strings[] = {
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@ -293,7 +294,8 @@ enum taa_mitigations {
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};
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/* Default mitigation for TAA-affected CPUs */
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static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW;
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static enum taa_mitigations taa_mitigation __ro_after_init =
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IS_ENABLED(CONFIG_MITIGATION_TAA) ? TAA_MITIGATION_VERW : TAA_MITIGATION_OFF;
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static bool taa_nosmt __ro_after_init;
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static const char * const taa_strings[] = {
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@ -391,7 +393,8 @@ enum mmio_mitigations {
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};
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/* Default mitigation for Processor MMIO Stale Data vulnerabilities */
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static enum mmio_mitigations mmio_mitigation __ro_after_init = MMIO_MITIGATION_VERW;
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static enum mmio_mitigations mmio_mitigation __ro_after_init =
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IS_ENABLED(CONFIG_MITIGATION_MMIO_STALE_DATA) ? MMIO_MITIGATION_VERW : MMIO_MITIGATION_OFF;
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static bool mmio_nosmt __ro_after_init = false;
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static const char * const mmio_strings[] = {
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@ -605,7 +608,8 @@ enum srbds_mitigations {
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SRBDS_MITIGATION_HYPERVISOR,
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};
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static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL;
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static enum srbds_mitigations srbds_mitigation __ro_after_init =
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IS_ENABLED(CONFIG_MITIGATION_SRBDS) ? SRBDS_MITIGATION_FULL : SRBDS_MITIGATION_OFF;
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static const char * const srbds_strings[] = {
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[SRBDS_MITIGATION_OFF] = "Vulnerable",
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@ -731,11 +735,8 @@ enum gds_mitigations {
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GDS_MITIGATION_HYPERVISOR,
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};
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#if IS_ENABLED(CONFIG_MITIGATION_GDS_FORCE)
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static enum gds_mitigations gds_mitigation __ro_after_init = GDS_MITIGATION_FORCE;
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#else
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static enum gds_mitigations gds_mitigation __ro_after_init = GDS_MITIGATION_FULL;
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#endif
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static enum gds_mitigations gds_mitigation __ro_after_init =
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IS_ENABLED(CONFIG_MITIGATION_GDS) ? GDS_MITIGATION_FULL : GDS_MITIGATION_OFF;
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static const char * const gds_strings[] = {
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[GDS_MITIGATION_OFF] = "Vulnerable",
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@ -871,7 +872,8 @@ enum spectre_v1_mitigation {
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};
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static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init =
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SPECTRE_V1_MITIGATION_AUTO;
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IS_ENABLED(CONFIG_MITIGATION_SPECTRE_V1) ?
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SPECTRE_V1_MITIGATION_AUTO : SPECTRE_V1_MITIGATION_NONE;
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static const char * const spectre_v1_strings[] = {
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[SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
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@ -986,7 +988,7 @@ static const char * const retbleed_strings[] = {
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static enum retbleed_mitigation retbleed_mitigation __ro_after_init =
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RETBLEED_MITIGATION_NONE;
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static enum retbleed_mitigation_cmd retbleed_cmd __ro_after_init =
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RETBLEED_CMD_AUTO;
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IS_ENABLED(CONFIG_MITIGATION_RETBLEED) ? RETBLEED_CMD_AUTO : RETBLEED_CMD_OFF;
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static int __ro_after_init retbleed_nosmt = false;
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@ -1447,17 +1449,18 @@ static void __init spec_v2_print_cond(const char *reason, bool secure)
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static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
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{
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enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
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enum spectre_v2_mitigation_cmd cmd;
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char arg[20];
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int ret, i;
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cmd = IS_ENABLED(CONFIG_MITIGATION_SPECTRE_V2) ? SPECTRE_V2_CMD_AUTO : SPECTRE_V2_CMD_NONE;
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if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") ||
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cpu_mitigations_off())
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return SPECTRE_V2_CMD_NONE;
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ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
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if (ret < 0)
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return SPECTRE_V2_CMD_AUTO;
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return cmd;
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for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
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if (!match_option(arg, ret, mitigation_options[i].option))
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@ -1467,8 +1470,8 @@ static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
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}
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if (i >= ARRAY_SIZE(mitigation_options)) {
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pr_err("unknown option (%s). Switching to AUTO select\n", arg);
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return SPECTRE_V2_CMD_AUTO;
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pr_err("unknown option (%s). Switching to default mode\n", arg);
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return cmd;
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}
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if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
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@ -2021,10 +2024,12 @@ static const struct {
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static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
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{
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enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
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enum ssb_mitigation_cmd cmd;
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char arg[20];
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int ret, i;
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cmd = IS_ENABLED(CONFIG_MITIGATION_SSB) ?
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SPEC_STORE_BYPASS_CMD_AUTO : SPEC_STORE_BYPASS_CMD_NONE;
|
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if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") ||
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cpu_mitigations_off()) {
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return SPEC_STORE_BYPASS_CMD_NONE;
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@ -2032,7 +2037,7 @@ static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
|
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ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
|
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arg, sizeof(arg));
|
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if (ret < 0)
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return SPEC_STORE_BYPASS_CMD_AUTO;
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return cmd;
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for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
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if (!match_option(arg, ret, ssb_mitigation_options[i].option))
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@ -2043,8 +2048,8 @@ static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
|
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}
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if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
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pr_err("unknown option (%s). Switching to AUTO select\n", arg);
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return SPEC_STORE_BYPASS_CMD_AUTO;
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pr_err("unknown option (%s). Switching to default mode\n", arg);
|
||||
return cmd;
|
||||
}
|
||||
}
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||||
|
||||
@ -2371,7 +2376,8 @@ EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation);
|
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#define pr_fmt(fmt) "L1TF: " fmt
|
||||
|
||||
/* Default mitigation for L1TF-affected CPUs */
|
||||
enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
|
||||
enum l1tf_mitigations l1tf_mitigation __ro_after_init =
|
||||
IS_ENABLED(CONFIG_MITIGATION_L1TF) ? L1TF_MITIGATION_FLUSH : L1TF_MITIGATION_OFF;
|
||||
#if IS_ENABLED(CONFIG_KVM_INTEL)
|
||||
EXPORT_SYMBOL_GPL(l1tf_mitigation);
|
||||
#endif
|
||||
@ -2551,10 +2557,9 @@ static void __init srso_select_mitigation(void)
|
||||
{
|
||||
bool has_microcode = boot_cpu_has(X86_FEATURE_IBPB_BRTYPE);
|
||||
|
||||
if (cpu_mitigations_off())
|
||||
return;
|
||||
|
||||
if (!boot_cpu_has_bug(X86_BUG_SRSO)) {
|
||||
if (!boot_cpu_has_bug(X86_BUG_SRSO) ||
|
||||
cpu_mitigations_off() ||
|
||||
srso_cmd == SRSO_CMD_OFF) {
|
||||
if (boot_cpu_has(X86_FEATURE_SBPB))
|
||||
x86_pred_cmd = PRED_CMD_SBPB;
|
||||
return;
|
||||
@ -2585,11 +2590,6 @@ static void __init srso_select_mitigation(void)
|
||||
}
|
||||
|
||||
switch (srso_cmd) {
|
||||
case SRSO_CMD_OFF:
|
||||
if (boot_cpu_has(X86_FEATURE_SBPB))
|
||||
x86_pred_cmd = PRED_CMD_SBPB;
|
||||
return;
|
||||
|
||||
case SRSO_CMD_MICROCODE:
|
||||
if (has_microcode) {
|
||||
srso_mitigation = SRSO_MITIGATION_MICROCODE;
|
||||
@ -2643,6 +2643,8 @@ static void __init srso_select_mitigation(void)
|
||||
pr_err("WARNING: kernel not compiled with MITIGATION_SRSO.\n");
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
out:
|
||||
|
||||
@ -1165,8 +1165,8 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
|
||||
|
||||
VULNWL_INTEL(INTEL_CORE_YONAH, NO_SSB),
|
||||
|
||||
VULNWL_INTEL(INTEL_ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
|
||||
VULNWL_INTEL(INTEL_ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
|
||||
VULNWL_INTEL(INTEL_ATOM_AIRMONT_MID, NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | MSBDS_ONLY),
|
||||
VULNWL_INTEL(INTEL_ATOM_AIRMONT_NP, NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
|
||||
|
||||
VULNWL_INTEL(INTEL_ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
|
||||
VULNWL_INTEL(INTEL_ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
|
||||
|
||||
@ -77,7 +77,7 @@ all_32: $(BINARIES_32)
|
||||
|
||||
all_64: $(BINARIES_64)
|
||||
|
||||
EXTRA_CLEAN := $(BINARIES_32) $(BINARIES_64)
|
||||
EXTRA_CLEAN := $(BINARIES_32) $(BINARIES_64) srso
|
||||
|
||||
$(BINARIES_32): $(OUTPUT)/%_32: %.c helpers.h
|
||||
$(CC) -m32 -o $@ $(CFLAGS) $(EXTRA_CFLAGS) $< $(EXTRA_FILES) -lrt -ldl -lm
|
||||
|
||||
70
tools/testing/selftests/x86/srso.c
Normal file
70
tools/testing/selftests/x86/srso.c
Normal file
@ -0,0 +1,70 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
#include <linux/perf_event.h>
|
||||
#include <cpuid.h>
|
||||
#include <errno.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <sys/ioctl.h>
|
||||
#include <sys/syscall.h>
|
||||
#include <unistd.h>
|
||||
|
||||
int main(void)
|
||||
{
|
||||
struct perf_event_attr ret_attr, mret_attr;
|
||||
long long count_rets, count_rets_mispred;
|
||||
int rrets_fd, mrrets_fd;
|
||||
unsigned int cpuid1_eax, b, c, d;
|
||||
|
||||
__cpuid(1, cpuid1_eax, b, c, d);
|
||||
|
||||
if (cpuid1_eax < 0x00800f00 ||
|
||||
cpuid1_eax > 0x00afffff) {
|
||||
fprintf(stderr, "This needs to run on a Zen[1-4] machine (CPUID(1).EAX: 0x%x). Exiting...\n", cpuid1_eax);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
memset(&ret_attr, 0, sizeof(struct perf_event_attr));
|
||||
memset(&mret_attr, 0, sizeof(struct perf_event_attr));
|
||||
|
||||
ret_attr.type = mret_attr.type = PERF_TYPE_RAW;
|
||||
ret_attr.size = mret_attr.size = sizeof(struct perf_event_attr);
|
||||
ret_attr.config = 0xc8;
|
||||
mret_attr.config = 0xc9;
|
||||
ret_attr.disabled = mret_attr.disabled = 1;
|
||||
ret_attr.exclude_user = mret_attr.exclude_user = 1;
|
||||
ret_attr.exclude_hv = mret_attr.exclude_hv = 1;
|
||||
|
||||
rrets_fd = syscall(SYS_perf_event_open, &ret_attr, 0, -1, -1, 0);
|
||||
if (rrets_fd == -1) {
|
||||
perror("opening retired RETs fd");
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
mrrets_fd = syscall(SYS_perf_event_open, &mret_attr, 0, -1, -1, 0);
|
||||
if (mrrets_fd == -1) {
|
||||
perror("opening retired mispredicted RETs fd");
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
ioctl(rrets_fd, PERF_EVENT_IOC_RESET, 0);
|
||||
ioctl(mrrets_fd, PERF_EVENT_IOC_RESET, 0);
|
||||
|
||||
ioctl(rrets_fd, PERF_EVENT_IOC_ENABLE, 0);
|
||||
ioctl(mrrets_fd, PERF_EVENT_IOC_ENABLE, 0);
|
||||
|
||||
printf("Sleeping for 10 seconds\n");
|
||||
sleep(10);
|
||||
|
||||
ioctl(rrets_fd, PERF_EVENT_IOC_DISABLE, 0);
|
||||
ioctl(mrrets_fd, PERF_EVENT_IOC_DISABLE, 0);
|
||||
|
||||
read(rrets_fd, &count_rets, sizeof(long long));
|
||||
read(mrrets_fd, &count_rets_mispred, sizeof(long long));
|
||||
|
||||
printf("RETs: (%lld retired <-> %lld mispredicted)\n",
|
||||
count_rets, count_rets_mispred);
|
||||
printf("SRSO Safe-RET mitigation works correctly if both counts are almost equal.\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user