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clocksource: SuperH TMU Timer driver
This patch adds a TMU driver for the SuperH architecture. The TMU driver is a platform driver with early platform support to allow using a TMU channel as clockevent or clocksource during system bootup or later. Clocksource or clockevent can be selected. Both periodic and oneshot clockevents are supported. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
Paul Mundt
parent
3280c8865e
commit
9570ef2042
@ -116,6 +116,9 @@ config SYS_SUPPORTS_CMT
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config SYS_SUPPORTS_MTU2
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bool
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config SYS_SUPPORTS_TMU
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bool
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config STACKTRACE_SUPPORT
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def_bool y
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@ -470,6 +473,15 @@ config SH_TMU
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help
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This enables the use of the TMU as the system timer.
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config SH_TIMER_TMU
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bool "TMU timer driver"
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depends on !SH_TMU && SYS_SUPPORTS_TMU
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default y
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select GENERIC_TIME
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select GENERIC_CLOCKEVENTS
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help
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This enables the build of the TMU timer driver.
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config SH_TIMER_CMT
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bool "CMT timer driver"
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depends on SYS_SUPPORTS_CMT
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@ -4,3 +4,4 @@ obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
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obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
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obj-$(CONFIG_SH_TIMER_CMT) += sh_cmt.o
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obj-$(CONFIG_SH_TIMER_MTU2) += sh_mtu2.o
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obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o
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461
drivers/clocksource/sh_tmu.c
Normal file
461
drivers/clocksource/sh_tmu.c
Normal file
@ -0,0 +1,461 @@
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/*
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* SuperH Timer Support - TMU
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*
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* Copyright (C) 2009 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/irq.h>
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#include <linux/err.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/sh_tmu.h>
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struct sh_tmu_priv {
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void __iomem *mapbase;
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struct clk *clk;
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struct irqaction irqaction;
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struct platform_device *pdev;
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unsigned long rate;
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unsigned long periodic;
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struct clock_event_device ced;
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struct clocksource cs;
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};
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static DEFINE_SPINLOCK(sh_tmu_lock);
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#define TSTR -1 /* shared register */
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#define TCOR 0 /* channel register */
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#define TCNT 1 /* channel register */
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#define TCR 2 /* channel register */
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static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr)
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{
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struct sh_tmu_config *cfg = p->pdev->dev.platform_data;
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void __iomem *base = p->mapbase;
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unsigned long offs;
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if (reg_nr == TSTR)
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return ioread8(base - cfg->channel_offset);
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offs = reg_nr << 2;
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if (reg_nr == TCR)
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return ioread16(base + offs);
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else
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return ioread32(base + offs);
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}
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static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr,
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unsigned long value)
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{
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struct sh_tmu_config *cfg = p->pdev->dev.platform_data;
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void __iomem *base = p->mapbase;
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unsigned long offs;
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if (reg_nr == TSTR) {
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iowrite8(value, base - cfg->channel_offset);
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return;
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}
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offs = reg_nr << 2;
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if (reg_nr == TCR)
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iowrite16(value, base + offs);
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else
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iowrite32(value, base + offs);
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}
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static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
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{
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struct sh_tmu_config *cfg = p->pdev->dev.platform_data;
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unsigned long flags, value;
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/* start stop register shared by multiple timer channels */
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spin_lock_irqsave(&sh_tmu_lock, flags);
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value = sh_tmu_read(p, TSTR);
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if (start)
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value |= 1 << cfg->timer_bit;
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else
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value &= ~(1 << cfg->timer_bit);
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sh_tmu_write(p, TSTR, value);
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spin_unlock_irqrestore(&sh_tmu_lock, flags);
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}
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static int sh_tmu_enable(struct sh_tmu_priv *p)
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{
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struct sh_tmu_config *cfg = p->pdev->dev.platform_data;
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int ret;
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/* enable clock */
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ret = clk_enable(p->clk);
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if (ret) {
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pr_err("sh_tmu: cannot enable clock \"%s\"\n", cfg->clk);
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return ret;
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}
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/* make sure channel is disabled */
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sh_tmu_start_stop_ch(p, 0);
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/* maximum timeout */
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sh_tmu_write(p, TCOR, 0xffffffff);
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sh_tmu_write(p, TCNT, 0xffffffff);
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/* configure channel to parent clock / 4, irq off */
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p->rate = clk_get_rate(p->clk) / 4;
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sh_tmu_write(p, TCR, 0x0000);
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/* enable channel */
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sh_tmu_start_stop_ch(p, 1);
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return 0;
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}
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static void sh_tmu_disable(struct sh_tmu_priv *p)
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{
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/* disable channel */
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sh_tmu_start_stop_ch(p, 0);
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/* stop clock */
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clk_disable(p->clk);
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}
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static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta,
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int periodic)
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{
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/* stop timer */
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sh_tmu_start_stop_ch(p, 0);
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/* acknowledge interrupt */
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sh_tmu_read(p, TCR);
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/* enable interrupt */
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sh_tmu_write(p, TCR, 0x0020);
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/* reload delta value in case of periodic timer */
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if (periodic)
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sh_tmu_write(p, TCOR, delta);
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else
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sh_tmu_write(p, TCOR, 0);
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sh_tmu_write(p, TCNT, delta);
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/* start timer */
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sh_tmu_start_stop_ch(p, 1);
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}
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static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
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{
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struct sh_tmu_priv *p = dev_id;
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/* disable or acknowledge interrupt */
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if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT)
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sh_tmu_write(p, TCR, 0x0000);
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else
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sh_tmu_write(p, TCR, 0x0020);
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/* notify clockevent layer */
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p->ced.event_handler(&p->ced);
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return IRQ_HANDLED;
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}
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static struct sh_tmu_priv *cs_to_sh_tmu(struct clocksource *cs)
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{
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return container_of(cs, struct sh_tmu_priv, cs);
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}
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static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
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{
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struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
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return sh_tmu_read(p, TCNT) ^ 0xffffffff;
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}
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static int sh_tmu_clocksource_enable(struct clocksource *cs)
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{
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struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
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int ret;
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ret = sh_tmu_enable(p);
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if (ret)
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return ret;
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/* TODO: calculate good shift from rate and counter bit width */
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cs->shift = 10;
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cs->mult = clocksource_hz2mult(p->rate, cs->shift);
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return 0;
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}
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static void sh_tmu_clocksource_disable(struct clocksource *cs)
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{
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sh_tmu_disable(cs_to_sh_tmu(cs));
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}
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static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
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char *name, unsigned long rating)
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{
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struct clocksource *cs = &p->cs;
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cs->name = name;
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cs->rating = rating;
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cs->read = sh_tmu_clocksource_read;
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cs->enable = sh_tmu_clocksource_enable;
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cs->disable = sh_tmu_clocksource_disable;
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cs->mask = CLOCKSOURCE_MASK(32);
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cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
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pr_info("sh_tmu: %s used as clock source\n", cs->name);
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clocksource_register(cs);
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return 0;
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}
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static struct sh_tmu_priv *ced_to_sh_tmu(struct clock_event_device *ced)
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{
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return container_of(ced, struct sh_tmu_priv, ced);
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}
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static void sh_tmu_clock_event_start(struct sh_tmu_priv *p, int periodic)
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{
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struct clock_event_device *ced = &p->ced;
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sh_tmu_enable(p);
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/* TODO: calculate good shift from rate and counter bit width */
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ced->shift = 32;
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ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
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ced->max_delta_ns = clockevent_delta2ns(0xffffffff, ced);
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ced->min_delta_ns = 5000;
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if (periodic) {
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p->periodic = (p->rate + HZ/2) / HZ;
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sh_tmu_set_next(p, p->periodic, 1);
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}
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}
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static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
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struct clock_event_device *ced)
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{
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struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
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int disabled = 0;
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/* deal with old setting first */
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switch (ced->mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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case CLOCK_EVT_MODE_ONESHOT:
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sh_tmu_disable(p);
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disabled = 1;
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break;
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default:
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break;
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}
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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pr_info("sh_tmu: %s used for periodic clock events\n",
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ced->name);
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sh_tmu_clock_event_start(p, 1);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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pr_info("sh_tmu: %s used for oneshot clock events\n",
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ced->name);
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sh_tmu_clock_event_start(p, 0);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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if (!disabled)
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sh_tmu_disable(p);
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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break;
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}
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}
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static int sh_tmu_clock_event_next(unsigned long delta,
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struct clock_event_device *ced)
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{
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struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
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BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
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/* program new delta value */
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sh_tmu_set_next(p, delta, 0);
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return 0;
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}
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static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
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char *name, unsigned long rating)
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{
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struct clock_event_device *ced = &p->ced;
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int ret;
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memset(ced, 0, sizeof(*ced));
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ced->name = name;
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ced->features = CLOCK_EVT_FEAT_PERIODIC;
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ced->features |= CLOCK_EVT_FEAT_ONESHOT;
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ced->rating = rating;
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ced->cpumask = cpumask_of(0);
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ced->set_next_event = sh_tmu_clock_event_next;
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ced->set_mode = sh_tmu_clock_event_mode;
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ret = setup_irq(p->irqaction.irq, &p->irqaction);
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if (ret) {
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pr_err("sh_tmu: failed to request irq %d\n",
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p->irqaction.irq);
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return;
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}
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pr_info("sh_tmu: %s used for clock events\n", ced->name);
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clockevents_register_device(ced);
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}
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static int sh_tmu_register(struct sh_tmu_priv *p, char *name,
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unsigned long clockevent_rating,
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unsigned long clocksource_rating)
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{
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if (clockevent_rating)
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sh_tmu_register_clockevent(p, name, clockevent_rating);
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else if (clocksource_rating)
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sh_tmu_register_clocksource(p, name, clocksource_rating);
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return 0;
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}
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static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
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{
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struct sh_tmu_config *cfg = pdev->dev.platform_data;
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struct resource *res;
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int irq, ret;
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ret = -ENXIO;
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memset(p, 0, sizeof(*p));
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p->pdev = pdev;
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if (!cfg) {
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dev_err(&p->pdev->dev, "missing platform data\n");
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goto err0;
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}
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platform_set_drvdata(pdev, p);
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res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&p->pdev->dev, "failed to get I/O memory\n");
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goto err0;
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}
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irq = platform_get_irq(p->pdev, 0);
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if (irq < 0) {
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dev_err(&p->pdev->dev, "failed to get irq\n");
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goto err0;
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}
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/* map memory, let mapbase point to our channel */
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p->mapbase = ioremap_nocache(res->start, resource_size(res));
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if (p->mapbase == NULL) {
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pr_err("sh_tmu: failed to remap I/O memory\n");
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goto err0;
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}
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/* setup data for setup_irq() (too early for request_irq()) */
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p->irqaction.name = cfg->name;
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p->irqaction.handler = sh_tmu_interrupt;
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p->irqaction.dev_id = p;
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p->irqaction.irq = irq;
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p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
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p->irqaction.mask = CPU_MASK_NONE;
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/* get hold of clock */
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p->clk = clk_get(&p->pdev->dev, cfg->clk);
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if (IS_ERR(p->clk)) {
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pr_err("sh_tmu: cannot get clock \"%s\"\n", cfg->clk);
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ret = PTR_ERR(p->clk);
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goto err1;
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}
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return sh_tmu_register(p, cfg->name,
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cfg->clockevent_rating,
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cfg->clocksource_rating);
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err1:
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iounmap(p->mapbase);
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err0:
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return ret;
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}
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static int __devinit sh_tmu_probe(struct platform_device *pdev)
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{
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struct sh_tmu_priv *p = platform_get_drvdata(pdev);
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struct sh_tmu_config *cfg = pdev->dev.platform_data;
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int ret;
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if (p) {
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pr_info("sh_tmu: %s kept as earlytimer\n", cfg->name);
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return 0;
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}
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p = kmalloc(sizeof(*p), GFP_KERNEL);
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if (p == NULL) {
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dev_err(&pdev->dev, "failed to allocate driver data\n");
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return -ENOMEM;
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}
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ret = sh_tmu_setup(p, pdev);
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if (ret) {
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kfree(p);
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platform_set_drvdata(pdev, NULL);
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}
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return ret;
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}
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static int __devexit sh_tmu_remove(struct platform_device *pdev)
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{
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return -EBUSY; /* cannot unregister clockevent and clocksource */
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}
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static struct platform_driver sh_tmu_device_driver = {
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.probe = sh_tmu_probe,
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.remove = __devexit_p(sh_tmu_remove),
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.driver = {
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.name = "sh_tmu",
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}
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};
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|
||||
static int __init sh_tmu_init(void)
|
||||
{
|
||||
return platform_driver_register(&sh_tmu_device_driver);
|
||||
}
|
||||
|
||||
static void __exit sh_tmu_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&sh_tmu_device_driver);
|
||||
}
|
||||
|
||||
early_platform_init("earlytimer", &sh_tmu_device_driver);
|
||||
module_init(sh_tmu_init);
|
||||
module_exit(sh_tmu_exit);
|
||||
|
||||
MODULE_AUTHOR("Magnus Damm");
|
||||
MODULE_DESCRIPTION("SuperH TMU Timer Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
13
include/linux/sh_tmu.h
Normal file
13
include/linux/sh_tmu.h
Normal file
@ -0,0 +1,13 @@
|
||||
#ifndef __SH_TMU_H__
|
||||
#define __SH_TMU_H__
|
||||
|
||||
struct sh_tmu_config {
|
||||
char *name;
|
||||
unsigned long channel_offset;
|
||||
int timer_bit;
|
||||
char *clk;
|
||||
unsigned long clockevent_rating;
|
||||
unsigned long clocksource_rating;
|
||||
};
|
||||
|
||||
#endif /* __SH_TMU_H__ */
|
||||
Loading…
Reference in New Issue
Block a user