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spi: mchp-pci1xxxx: DMA support for copying data to and from SPI Buf
pci1xxxx_spi_transfer_with_dma adds DMA support to copy the data between host cpu buffer and SPI IO Buffer. On DMA Completion interrupt, the next SPI transaction is initiated in isr. Helper functions pci1xxxx_spi_setup, pci1xxxx_spi_setup_dma_from_io, pci1xxxx_spi_setup_dma_to_io and pci1xxxx_start_spi_xfer are added for setting up spi, setting up dma operations, and to start spi transfer respectively. In the existing implementation, codes are replaced with helper functions wherever applicable. Signed-off-by: Thangaraj Samynathan <thangaraj.s@microchip.com> Link: https://lore.kernel.org/r/20240207080621.30742-3-thangaraj.s@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Thangaraj Samynathan
Mark Brown
parent
3e7cfd6ad2
commit
9538edeb72
@ -5,6 +5,7 @@
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// Kumaravel Thiagarajan <Kumaravel.Thiagarajan@microchip.com>
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#include <linux/bitfield.h>
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#include <linux/dma-mapping.h>
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#include <linux/iopoll.h>
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#include <linux/irq.h>
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@ -12,6 +13,7 @@
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#include <linux/msi.h>
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#include <linux/pci_regs.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#include <linux/spi/spi.h>
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#include <linux/delay.h>
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@ -37,6 +39,7 @@
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#define SPI_MST_CTL_MODE_SEL (BIT(2))
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#define SPI_MST_CTL_GO (BIT(0))
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#define SPI_PERI_ADDR_BASE (0x160000)
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#define SPI_SYSTEM_ADDR_BASE (0x2000)
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#define SPI_MST1_ADDR_BASE (0x800)
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@ -48,22 +51,56 @@
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#define DEV_REV_MASK (GENMASK(7, 0))
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#define SPI_SYSLOCK BIT(4)
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#define SPI0 (0)
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#define SPI1 (1)
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/* DMA Related Registers */
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#define SPI_DMA_ADDR_BASE (0x1000)
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#define SPI_DMA_GLOBAL_WR_ENGINE_EN (SPI_DMA_ADDR_BASE + 0x0C)
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#define SPI_DMA_WR_DOORBELL_REG (SPI_DMA_ADDR_BASE + 0x10)
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#define SPI_DMA_GLOBAL_RD_ENGINE_EN (SPI_DMA_ADDR_BASE + 0x2C)
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#define SPI_DMA_RD_DOORBELL_REG (SPI_DMA_ADDR_BASE + 0x30)
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#define SPI_DMA_INTR_WR_STS (SPI_DMA_ADDR_BASE + 0x4C)
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#define SPI_DMA_WR_INT_MASK (SPI_DMA_ADDR_BASE + 0x54)
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#define SPI_DMA_INTR_WR_CLR (SPI_DMA_ADDR_BASE + 0x58)
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#define SPI_DMA_ERR_WR_STS (SPI_DMA_ADDR_BASE + 0x5C)
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#define SPI_DMA_INTR_IMWR_WDONE_LOW (SPI_DMA_ADDR_BASE + 0x60)
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#define SPI_DMA_INTR_IMWR_WDONE_HIGH (SPI_DMA_ADDR_BASE + 0x64)
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#define SPI_DMA_INTR_IMWR_WABORT_LOW (SPI_DMA_ADDR_BASE + 0x68)
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#define SPI_DMA_INTR_IMWR_WABORT_HIGH (SPI_DMA_ADDR_BASE + 0x6C)
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#define SPI_DMA_INTR_WR_IMWR_DATA (SPI_DMA_ADDR_BASE + 0x70)
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#define SPI_DMA_INTR_RD_STS (SPI_DMA_ADDR_BASE + 0xA0)
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#define SPI_DMA_RD_INT_MASK (SPI_DMA_ADDR_BASE + 0xA8)
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#define SPI_DMA_INTR_RD_CLR (SPI_DMA_ADDR_BASE + 0xAC)
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#define SPI_DMA_ERR_RD_STS (SPI_DMA_ADDR_BASE + 0xB8)
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#define SPI_DMA_INTR_IMWR_RDONE_LOW (SPI_DMA_ADDR_BASE + 0xCC)
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#define SPI_DMA_INTR_IMWR_RDONE_HIGH (SPI_DMA_ADDR_BASE + 0xD0)
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#define SPI_DMA_INTR_IMWR_RABORT_LOW (SPI_DMA_ADDR_BASE + 0xD4)
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#define SPI_DMA_INTR_IMWR_RABORT_HIGH (SPI_DMA_ADDR_BASE + 0xD8)
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#define SPI_DMA_INTR_RD_IMWR_DATA (SPI_DMA_ADDR_BASE + 0xDC)
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#define SPI_DMA_CH0_WR_BASE (SPI_DMA_ADDR_BASE + 0x200)
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#define SPI_DMA_CH0_RD_BASE (SPI_DMA_ADDR_BASE + 0x300)
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#define SPI_DMA_CH1_WR_BASE (SPI_DMA_ADDR_BASE + 0x400)
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#define SPI_DMA_CH1_RD_BASE (SPI_DMA_ADDR_BASE + 0x500)
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#define SPI_DMA_CH_CTL1_OFFSET (0x00)
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#define SPI_DMA_CH_XFER_LEN_OFFSET (0x08)
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#define SPI_DMA_CH_SAR_LO_OFFSET (0x0C)
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#define SPI_DMA_CH_SAR_HI_OFFSET (0x10)
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#define SPI_DMA_CH_DAR_LO_OFFSET (0x14)
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#define SPI_DMA_CH_DAR_HI_OFFSET (0x18)
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#define SPI_DMA_CH0_DONE_INT BIT(0)
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#define SPI_DMA_CH1_DONE_INT BIT(1)
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#define SPI_DMA_CH0_ABORT_INT BIT(16)
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#define SPI_DMA_CH1_ABORT_INT BIT(17)
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#define SPI_DMA_DONE_INT_MASK (SPI_DMA_CH0_DONE_INT | SPI_DMA_CH1_DONE_INT)
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#define SPI_DMA_ABORT_INT_MASK (SPI_DMA_CH0_ABORT_INT | SPI_DMA_CH1_ABORT_INT)
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#define DMA_CH_CONTROL_LIE BIT(3)
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#define DMA_CH_CONTROL_RIE BIT(4)
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#define DMA_INTR_EN (DMA_CH_CONTROL_RIE | DMA_CH_CONTROL_LIE)
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/* x refers to SPI Host Controller HW instance id in the below macros - 0 or 1 */
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#define SPI_MST_CMD_BUF_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x00)
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@ -82,6 +119,7 @@
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#define PCI1XXXX_SPI_TIMEOUT (msecs_to_jiffies(100))
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#define SYSLOCK_RETRY_CNT (1000)
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#define SPI_DMA_ENGINE_EN (0x1)
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#define SPI_DMA_ENGINE_DIS (0x0)
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#define SPI_INTR BIT(8)
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#define SPI_FORCE_CE BIT(4)
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@ -94,11 +132,21 @@
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struct pci1xxxx_spi_internal {
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u8 hw_inst;
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bool spi_xfer_in_progress;
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u8 clkdiv;
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int irq;
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int mode;
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bool spi_xfer_in_progress;
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void *rx_buf;
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bool dma_aborted_rd;
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u32 bytes_recvd;
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u32 tx_sgl_len;
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u32 rx_sgl_len;
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struct scatterlist *tx_sgl, *rx_sgl;
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bool dma_aborted_wr;
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struct completion spi_xfer_done;
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struct spi_controller *spi_host;
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struct pci1xxxx_spi *parent;
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struct spi_transfer *xfer;
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struct {
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unsigned int dev_sel : 3;
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unsigned int msi_vector_sel : 1;
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@ -111,6 +159,8 @@ struct pci1xxxx_spi {
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u8 dev_rev;
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void __iomem *reg_base;
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void __iomem *dma_offset_bar;
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/* lock to safely access the DMA registers in isr */
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spinlock_t dma_reg_lock;
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bool can_dma;
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struct pci1xxxx_spi_internal *spi_int[] __counted_by(total_hw_instances);
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};
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@ -230,6 +280,7 @@ static int pci1xxxx_spi_dma_init(struct pci1xxxx_spi *spi_bus, int irq)
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if (ret)
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return ret;
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spin_lock_init(&spi_bus->dma_reg_lock);
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get_cached_msi_msg(irq, &msi);
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writel(SPI_DMA_ENGINE_EN, spi_bus->dma_offset_bar + SPI_DMA_GLOBAL_WR_ENGINE_EN);
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writel(SPI_DMA_ENGINE_EN, spi_bus->dma_offset_bar + SPI_DMA_GLOBAL_RD_ENGINE_EN);
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@ -243,6 +294,7 @@ static int pci1xxxx_spi_dma_init(struct pci1xxxx_spi *spi_bus, int irq)
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writel(msi.address_lo, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_RABORT_LOW);
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writel(msi.data, spi_bus->dma_offset_bar + SPI_DMA_INTR_WR_IMWR_DATA);
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writel(msi.data, spi_bus->dma_offset_bar + SPI_DMA_INTR_RD_IMWR_DATA);
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dma_set_max_seg_size(&spi_bus->dev->dev, PCI1XXXX_SPI_BUFFER_SIZE);
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spi_bus->can_dma = true;
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return 0;
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}
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@ -287,12 +339,79 @@ static u8 pci1xxxx_get_clock_div(u32 hz)
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return val;
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}
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static int pci1xxxx_spi_transfer_one(struct spi_controller *spi_ctlr,
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struct spi_device *spi, struct spi_transfer *xfer)
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static void pci1xxxx_spi_setup_dma_to_io(struct pci1xxxx_spi_internal *p,
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dma_addr_t dma_addr, u32 len)
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{
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void __iomem *base;
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if (!p->hw_inst)
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base = p->parent->dma_offset_bar + SPI_DMA_CH0_RD_BASE;
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else
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base = p->parent->dma_offset_bar + SPI_DMA_CH1_RD_BASE;
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writel(DMA_INTR_EN, base + SPI_DMA_CH_CTL1_OFFSET);
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writel(len, base + SPI_DMA_CH_XFER_LEN_OFFSET);
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writel(lower_32_bits(dma_addr), base + SPI_DMA_CH_SAR_LO_OFFSET);
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writel(upper_32_bits(dma_addr), base + SPI_DMA_CH_SAR_HI_OFFSET);
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/* Updated SPI Command Registers */
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writel(lower_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_CMD_BUF_OFFSET(p->hw_inst)),
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base + SPI_DMA_CH_DAR_LO_OFFSET);
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writel(upper_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_CMD_BUF_OFFSET(p->hw_inst)),
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base + SPI_DMA_CH_DAR_HI_OFFSET);
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}
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static void pci1xxxx_spi_setup_dma_from_io(struct pci1xxxx_spi_internal *p,
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dma_addr_t dma_addr, u32 len)
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{
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void *base;
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if (!p->hw_inst)
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base = p->parent->dma_offset_bar + SPI_DMA_CH0_WR_BASE;
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else
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base = p->parent->dma_offset_bar + SPI_DMA_CH1_WR_BASE;
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writel(DMA_INTR_EN, base + SPI_DMA_CH_CTL1_OFFSET);
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writel(len, base + SPI_DMA_CH_XFER_LEN_OFFSET);
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writel(lower_32_bits(dma_addr), base + SPI_DMA_CH_DAR_LO_OFFSET);
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writel(upper_32_bits(dma_addr), base + SPI_DMA_CH_DAR_HI_OFFSET);
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writel(lower_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_RSP_BUF_OFFSET(p->hw_inst)),
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base + SPI_DMA_CH_SAR_LO_OFFSET);
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writel(upper_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_RSP_BUF_OFFSET(p->hw_inst)),
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base + SPI_DMA_CH_SAR_HI_OFFSET);
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}
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static void pci1xxxx_spi_setup(struct pci1xxxx_spi *par, u8 hw_inst, u32 mode,
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u8 clkdiv, u32 len)
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{
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u32 regval;
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regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst));
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regval &= ~(SPI_MST_CTL_MODE_SEL | SPI_MST_CTL_CMD_LEN_MASK |
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SPI_MST_CTL_SPEED_MASK);
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if (mode == SPI_MODE_3)
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regval |= SPI_MST_CTL_MODE_SEL;
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regval |= FIELD_PREP(SPI_MST_CTL_CMD_LEN_MASK, len);
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regval |= FIELD_PREP(SPI_MST_CTL_SPEED_MASK, clkdiv);
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writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst));
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}
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static void pci1xxxx_start_spi_xfer(struct pci1xxxx_spi_internal *p, u8 hw_inst)
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{
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u32 regval;
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regval = readl(p->parent->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst));
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regval |= SPI_MST_CTL_GO;
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writel(regval, p->parent->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst));
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}
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static int pci1xxxx_spi_transfer_with_io(struct spi_controller *spi_ctlr,
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struct spi_device *spi, struct spi_transfer *xfer)
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{
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struct pci1xxxx_spi_internal *p = spi_controller_get_devdata(spi_ctlr);
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int mode, len, loop_iter, transfer_len;
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struct pci1xxxx_spi *par = p->parent;
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int len, loop_iter, transfer_len;
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unsigned long bytes_transfered;
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unsigned long bytes_recvd;
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unsigned long loop_count;
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@ -302,7 +421,7 @@ static int pci1xxxx_spi_transfer_one(struct spi_controller *spi_ctlr,
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u8 clkdiv;
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p->spi_xfer_in_progress = true;
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mode = spi->mode;
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p->bytes_recvd = 0;
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clkdiv = pci1xxxx_get_clock_div(xfer->speed_hz);
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tx_buf = xfer->tx_buf;
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rx_buf = xfer->rx_buf;
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@ -327,26 +446,8 @@ static int pci1xxxx_spi_transfer_one(struct spi_controller *spi_ctlr,
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memcpy_toio(par->reg_base + SPI_MST_CMD_BUF_OFFSET(p->hw_inst),
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&tx_buf[bytes_transfered], len);
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bytes_transfered += len;
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regval = readl(par->reg_base +
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SPI_MST_CTL_REG_OFFSET(p->hw_inst));
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regval &= ~(SPI_MST_CTL_MODE_SEL | SPI_MST_CTL_CMD_LEN_MASK |
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SPI_MST_CTL_SPEED_MASK);
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if (mode == SPI_MODE_3)
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regval |= SPI_MST_CTL_MODE_SEL;
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else
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regval &= ~SPI_MST_CTL_MODE_SEL;
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regval |= (clkdiv << 5);
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regval &= ~SPI_MST_CTL_CMD_LEN_MASK;
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regval |= (len << 8);
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writel(regval, par->reg_base +
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SPI_MST_CTL_REG_OFFSET(p->hw_inst));
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regval = readl(par->reg_base +
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SPI_MST_CTL_REG_OFFSET(p->hw_inst));
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regval |= SPI_MST_CTL_GO;
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writel(regval, par->reg_base +
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SPI_MST_CTL_REG_OFFSET(p->hw_inst));
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pci1xxxx_spi_setup(par, p->hw_inst, spi->mode, clkdiv, len);
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pci1xxxx_start_spi_xfer(p, p->hw_inst);
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/* Wait for DMA_TERM interrupt */
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result = wait_for_completion_timeout(&p->spi_xfer_done,
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@ -366,7 +467,113 @@ static int pci1xxxx_spi_transfer_one(struct spi_controller *spi_ctlr,
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return 0;
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}
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static irqreturn_t pci1xxxx_spi_isr(int irq, void *dev)
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static int pci1xxxx_spi_transfer_with_dma(struct spi_controller *spi_ctlr,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct pci1xxxx_spi_internal *p = spi_controller_get_devdata(spi_ctlr);
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struct pci1xxxx_spi *par = p->parent;
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dma_addr_t rx_dma_addr = 0;
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dma_addr_t tx_dma_addr = 0;
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int ret = 0;
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u32 regval;
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p->spi_xfer_in_progress = true;
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p->tx_sgl = xfer->tx_sg.sgl;
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p->rx_sgl = xfer->rx_sg.sgl;
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p->rx_buf = xfer->rx_buf;
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regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
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writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
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if (!xfer->tx_buf || !p->tx_sgl) {
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ret = -EINVAL;
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goto error;
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}
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p->xfer = xfer;
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p->mode = spi->mode;
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p->clkdiv = pci1xxxx_get_clock_div(xfer->speed_hz);
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p->bytes_recvd = 0;
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p->rx_buf = xfer->rx_buf;
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regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
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writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
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tx_dma_addr = sg_dma_address(p->tx_sgl);
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rx_dma_addr = sg_dma_address(p->rx_sgl);
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p->tx_sgl_len = sg_dma_len(p->tx_sgl);
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p->rx_sgl_len = sg_dma_len(p->rx_sgl);
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pci1xxxx_spi_setup(par, p->hw_inst, p->mode, p->clkdiv, p->tx_sgl_len);
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pci1xxxx_spi_setup_dma_to_io(p, (tx_dma_addr), p->tx_sgl_len);
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if (rx_dma_addr)
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pci1xxxx_spi_setup_dma_from_io(p, rx_dma_addr, p->rx_sgl_len);
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writel(p->hw_inst, par->dma_offset_bar + SPI_DMA_RD_DOORBELL_REG);
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reinit_completion(&p->spi_xfer_done);
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/* Wait for DMA_TERM interrupt */
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ret = wait_for_completion_timeout(&p->spi_xfer_done, PCI1XXXX_SPI_TIMEOUT);
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if (!ret) {
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ret = -ETIMEDOUT;
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if (p->dma_aborted_rd) {
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writel(SPI_DMA_ENGINE_DIS,
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par->dma_offset_bar + SPI_DMA_GLOBAL_RD_ENGINE_EN);
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/*
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* DMA ENGINE reset takes time if any TLP
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* completeion in progress, should wait
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* till DMA Engine reset is completed.
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*/
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ret = readl_poll_timeout(par->dma_offset_bar +
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SPI_DMA_GLOBAL_RD_ENGINE_EN, regval,
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(regval == 0x0), 0, USEC_PER_MSEC);
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if (ret) {
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ret = -ECANCELED;
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goto error;
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}
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writel(SPI_DMA_ENGINE_EN,
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par->dma_offset_bar + SPI_DMA_GLOBAL_RD_ENGINE_EN);
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p->dma_aborted_rd = false;
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ret = -ECANCELED;
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}
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if (p->dma_aborted_wr) {
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writel(SPI_DMA_ENGINE_DIS,
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par->dma_offset_bar + SPI_DMA_GLOBAL_WR_ENGINE_EN);
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/*
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* DMA ENGINE reset takes time if any TLP
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* completeion in progress, should wait
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* till DMA Engine reset is completed.
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*/
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ret = readl_poll_timeout(par->dma_offset_bar +
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SPI_DMA_GLOBAL_WR_ENGINE_EN, regval,
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(regval == 0x0), 0, USEC_PER_MSEC);
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if (ret) {
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ret = -ECANCELED;
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goto error;
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}
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writel(SPI_DMA_ENGINE_EN,
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par->dma_offset_bar + SPI_DMA_GLOBAL_WR_ENGINE_EN);
|
||||
p->dma_aborted_wr = false;
|
||||
ret = -ECANCELED;
|
||||
}
|
||||
goto error;
|
||||
}
|
||||
ret = 0;
|
||||
|
||||
error:
|
||||
p->spi_xfer_in_progress = false;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int pci1xxxx_spi_transfer_one(struct spi_controller *spi_ctlr,
|
||||
struct spi_device *spi, struct spi_transfer *xfer)
|
||||
{
|
||||
if (spi_ctlr->can_dma(spi_ctlr, spi, xfer) && spi_ctlr->cur_msg_mapped)
|
||||
return pci1xxxx_spi_transfer_with_dma(spi_ctlr, spi, xfer);
|
||||
else
|
||||
return pci1xxxx_spi_transfer_with_io(spi_ctlr, spi, xfer);
|
||||
}
|
||||
|
||||
static irqreturn_t pci1xxxx_spi_isr_io(int irq, void *dev)
|
||||
{
|
||||
struct pci1xxxx_spi_internal *p = dev;
|
||||
irqreturn_t spi_int_fired = IRQ_NONE;
|
||||
@ -376,15 +583,117 @@ static irqreturn_t pci1xxxx_spi_isr(int irq, void *dev)
|
||||
regval = readl(p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
|
||||
if (regval & SPI_INTR) {
|
||||
/* Clear xfer_done */
|
||||
complete(&p->spi_xfer_done);
|
||||
if (p->parent->can_dma && p->rx_buf)
|
||||
writel(p->hw_inst, p->parent->dma_offset_bar +
|
||||
SPI_DMA_WR_DOORBELL_REG);
|
||||
else
|
||||
complete(&p->parent->spi_int[p->hw_inst]->spi_xfer_done);
|
||||
spi_int_fired = IRQ_HANDLED;
|
||||
}
|
||||
|
||||
writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
|
||||
|
||||
return spi_int_fired;
|
||||
}
|
||||
|
||||
static void pci1xxxx_spi_setup_next_dma_transfer(struct pci1xxxx_spi_internal *p)
|
||||
{
|
||||
dma_addr_t tx_dma_addr = 0;
|
||||
dma_addr_t rx_dma_addr = 0;
|
||||
u32 prev_len;
|
||||
|
||||
p->tx_sgl = sg_next(p->tx_sgl);
|
||||
if (p->rx_sgl)
|
||||
p->rx_sgl = sg_next(p->rx_sgl);
|
||||
if (!p->tx_sgl) {
|
||||
/* Clear xfer_done */
|
||||
complete(&p->spi_xfer_done);
|
||||
} else {
|
||||
tx_dma_addr = sg_dma_address(p->tx_sgl);
|
||||
prev_len = p->tx_sgl_len;
|
||||
p->tx_sgl_len = sg_dma_len(p->tx_sgl);
|
||||
if (prev_len != p->tx_sgl_len)
|
||||
pci1xxxx_spi_setup(p->parent,
|
||||
p->hw_inst, p->mode, p->clkdiv, p->tx_sgl_len);
|
||||
pci1xxxx_spi_setup_dma_to_io(p, tx_dma_addr, p->tx_sgl_len);
|
||||
if (p->rx_sgl) {
|
||||
rx_dma_addr = sg_dma_address(p->rx_sgl);
|
||||
p->rx_sgl_len = sg_dma_len(p->rx_sgl);
|
||||
pci1xxxx_spi_setup_dma_from_io(p, rx_dma_addr, p->rx_sgl_len);
|
||||
}
|
||||
writel(p->hw_inst, p->parent->dma_offset_bar + SPI_DMA_RD_DOORBELL_REG);
|
||||
}
|
||||
}
|
||||
|
||||
static irqreturn_t pci1xxxx_spi_isr_dma(int irq, void *dev)
|
||||
{
|
||||
struct pci1xxxx_spi_internal *p = dev;
|
||||
irqreturn_t spi_int_fired = IRQ_NONE;
|
||||
unsigned long flags;
|
||||
u32 regval;
|
||||
|
||||
spin_lock_irqsave(&p->parent->dma_reg_lock, flags);
|
||||
/* Clear the DMA RD INT and start spi xfer*/
|
||||
regval = readl(p->parent->dma_offset_bar + SPI_DMA_INTR_RD_STS);
|
||||
if (regval & SPI_DMA_DONE_INT_MASK) {
|
||||
if (regval & SPI_DMA_CH0_DONE_INT)
|
||||
pci1xxxx_start_spi_xfer(p, SPI0);
|
||||
if (regval & SPI_DMA_CH1_DONE_INT)
|
||||
pci1xxxx_start_spi_xfer(p, SPI1);
|
||||
spi_int_fired = IRQ_HANDLED;
|
||||
}
|
||||
if (regval & SPI_DMA_ABORT_INT_MASK) {
|
||||
p->dma_aborted_rd = true;
|
||||
spi_int_fired = IRQ_HANDLED;
|
||||
}
|
||||
writel(regval, p->parent->dma_offset_bar + SPI_DMA_INTR_RD_CLR);
|
||||
|
||||
/* Clear the DMA WR INT */
|
||||
regval = readl(p->parent->dma_offset_bar + SPI_DMA_INTR_WR_STS);
|
||||
if (regval & SPI_DMA_DONE_INT_MASK) {
|
||||
if (regval & SPI_DMA_CH0_DONE_INT)
|
||||
pci1xxxx_spi_setup_next_dma_transfer(p->parent->spi_int[SPI0]);
|
||||
|
||||
if (regval & SPI_DMA_CH1_DONE_INT)
|
||||
pci1xxxx_spi_setup_next_dma_transfer(p->parent->spi_int[SPI1]);
|
||||
|
||||
spi_int_fired = IRQ_HANDLED;
|
||||
}
|
||||
if (regval & SPI_DMA_ABORT_INT_MASK) {
|
||||
p->dma_aborted_wr = true;
|
||||
spi_int_fired = IRQ_HANDLED;
|
||||
}
|
||||
writel(regval, p->parent->dma_offset_bar + SPI_DMA_INTR_WR_CLR);
|
||||
spin_unlock_irqrestore(&p->parent->dma_reg_lock, flags);
|
||||
|
||||
/* Clear the SPI GO_BIT Interrupt */
|
||||
regval = readl(p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
|
||||
if (regval & SPI_INTR) {
|
||||
writel(p->hw_inst, p->parent->dma_offset_bar + SPI_DMA_WR_DOORBELL_REG);
|
||||
spi_int_fired = IRQ_HANDLED;
|
||||
}
|
||||
writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
|
||||
return spi_int_fired;
|
||||
}
|
||||
|
||||
static irqreturn_t pci1xxxx_spi_isr(int irq, void *dev)
|
||||
{
|
||||
struct pci1xxxx_spi_internal *p = dev;
|
||||
|
||||
if (p->spi_host->can_dma(p->spi_host, NULL, p->xfer))
|
||||
return pci1xxxx_spi_isr_dma(irq, dev);
|
||||
else
|
||||
return pci1xxxx_spi_isr_io(irq, dev);
|
||||
}
|
||||
|
||||
static bool pci1xxxx_spi_can_dma(struct spi_controller *host,
|
||||
struct spi_device *spi,
|
||||
struct spi_transfer *xfer)
|
||||
{
|
||||
struct pci1xxxx_spi_internal *p = spi_controller_get_devdata(host);
|
||||
struct pci1xxxx_spi *par = p->parent;
|
||||
|
||||
return par->can_dma;
|
||||
}
|
||||
|
||||
static int pci1xxxx_spi_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
u8 hw_inst_cnt, iter, start, only_sec_inst;
|
||||
@ -505,7 +814,9 @@ static int pci1xxxx_spi_probe(struct pci_dev *pdev, const struct pci_device_id *
|
||||
spi_host->num_chipselect = SPI_CHIP_SEL_COUNT;
|
||||
spi_host->mode_bits = SPI_MODE_0 | SPI_MODE_3 | SPI_RX_DUAL |
|
||||
SPI_TX_DUAL | SPI_LOOP;
|
||||
spi_host->can_dma = pci1xxxx_spi_can_dma;
|
||||
spi_host->transfer_one = pci1xxxx_spi_transfer_one;
|
||||
|
||||
spi_host->set_cs = pci1xxxx_spi_set_cs;
|
||||
spi_host->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
spi_host->max_speed_hz = PCI1XXXX_SPI_MAX_CLOCK_HZ;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user