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[PATCH] x86_64: Use the extended RIP MSR for machine check reporting if available.
They are rumoured to be much more reliable than the RIP in the stack frame on P4s. This is a borderline case because the code is very simple. Please note there are no plans to add support for all the MCE register MSRs. Cc: <venkatesh.pallipadi@intel.com> Cc: <racing.guo@intel.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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@ -33,6 +33,7 @@ static int banks;
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static unsigned long bank[NR_BANKS] = { [0 ... NR_BANKS-1] = ~0UL };
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static unsigned long console_logged;
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static int notify_user;
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static int rip_msr;
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/*
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* Lockless MCE logging infrastructure.
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@ -124,6 +125,23 @@ static int mce_available(struct cpuinfo_x86 *c)
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test_bit(X86_FEATURE_MCA, &c->x86_capability);
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}
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static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
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{
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if (regs && (m->mcgstatus & MCG_STATUS_RIPV)) {
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m->rip = regs->rip;
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m->cs = regs->cs;
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} else {
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m->rip = 0;
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m->cs = 0;
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}
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if (rip_msr) {
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/* Assume the RIP in the MSR is exact. Is this true? */
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m->mcgstatus |= MCG_STATUS_EIPV;
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rdmsrl(rip_msr, m->rip);
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m->cs = 0;
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}
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}
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/*
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* The actual machine check handler
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*/
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@ -176,14 +194,7 @@ void do_machine_check(struct pt_regs * regs, long error_code)
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if (m.status & MCI_STATUS_ADDRV)
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rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr);
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if (regs && (m.mcgstatus & MCG_STATUS_RIPV)) {
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m.rip = regs->rip;
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m.cs = regs->cs;
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} else {
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m.rip = 0;
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m.cs = 0;
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}
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mce_get_rip(&m, regs);
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if (error_code != -1)
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rdtscll(m.tsc);
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wrmsrl(MSR_IA32_MC0_STATUS + i*4, 0);
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@ -296,6 +307,9 @@ static void mce_init(void *dummy)
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printk(KERN_INFO "MCE: warning: using only %d banks\n", banks);
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banks = NR_BANKS;
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}
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/* Use accurate RIP reporting if available. */
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if ((cap & (1<<9)) && ((cap >> 16) & 0xff) >= 9)
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rip_msr = MSR_IA32_MCG_EIP;
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/* Log the machine checks left over from the previous reset.
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This also clears all registers */
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