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arm64: dts: imx8mp-phyboard-pollux-rdk: Add support for PCIe
Add support for the Mini PCIe slot. Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de> Reviewed-by: Yannic Moog <y.moog@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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52e6774ac3
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9454132128
@ -6,6 +6,7 @@
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/dts-v1/;
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/dts-v1/;
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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#include <dt-bindings/leds/leds-pca9532.h>
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#include <dt-bindings/leds/leds-pca9532.h>
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#include <dt-bindings/pwm/pwm.h>
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#include <dt-bindings/pwm/pwm.h>
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#include "imx8mp-phycore-som.dtsi"
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#include "imx8mp-phycore-som.dtsi"
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@ -221,6 +222,23 @@
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status = "okay";
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status = "okay";
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};
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};
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&pcie_phy {
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clocks = <&hsio_blk_ctrl>;
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clock-names = "ref";
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fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
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fsl,clkreq-unsupported;
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status = "okay";
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};
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/* Mini PCIe */
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&pcie {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie0>;
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reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
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vpcie-supply = <®_vcc_3v3_sw>;
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status = "okay";
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};
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&pwm3 {
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&pwm3 {
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status = "okay";
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status = "okay";
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pinctrl-names = "default";
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pinctrl-names = "default";
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@ -405,6 +423,15 @@
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>;
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>;
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};
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};
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pinctrl_pcie0: pcie0grp {
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fsl,pins = <
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MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40
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MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x60
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MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x60 /* open drain, pull up */
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MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x40
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>;
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};
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pinctrl_pwm3: pwm3grp {
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pinctrl_pwm3: pwm3grp {
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fsl,pins = <
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fsl,pins = <
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MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x12
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MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x12
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