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[MIPS] Make SB1 cache flushes not to use on_each_cpu

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This fixes the

  start_kernel(): bug: interrupts were enabled early

messages.

Signed-off-by: Manish Lachwani <mlachwani@mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manish Lachwani 2006-10-05 16:30:44 -07:00 committed by Ralf Baechle
parent f0ec69e529
commit 9448b8f6a0
1 changed files with 13 additions and 4 deletions
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17
arch/mips/mm/c-sb1.c
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@ -49,6 +49,15 @@ static unsigned short dcache_sets;
static unsigned int icache_range_cutoff; static unsigned int icache_range_cutoff;
static unsigned int dcache_range_cutoff; static unsigned int dcache_range_cutoff;
static inline void sb1_on_each_cpu(void (*func) (void *info), void *info,
int retry, int wait)
{
preempt_disable();
smp_call_function(func, info, retry, wait);
func(info);
preempt_enable();
}
/* /*
* The dcache is fully coherent to the system, with one * The dcache is fully coherent to the system, with one
* big caveat: the instruction stream. In other words, * big caveat: the instruction stream. In other words,
@ -226,7 +235,7 @@ static void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr,
args.vma = vma; args.vma = vma;
args.addr = addr; args.addr = addr;
args.pfn = pfn; args.pfn = pfn;
on_each_cpu(sb1_flush_cache_page_ipi, (void *) &args, 1, 1); sb1_on_each_cpu(sb1_flush_cache_page_ipi, (void *) &args, 1, 1);
} }
#else #else
void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn) void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
@ -249,7 +258,7 @@ void sb1___flush_cache_all_ipi(void *ignored)
static void sb1___flush_cache_all(void) static void sb1___flush_cache_all(void)
{ {
on_each_cpu(sb1___flush_cache_all_ipi, 0, 1, 1); sb1_on_each_cpu(sb1___flush_cache_all_ipi, 0, 1, 1);
} }
#else #else
void sb1___flush_cache_all(void) void sb1___flush_cache_all(void)
@ -299,7 +308,7 @@ void sb1_flush_icache_range(unsigned long start, unsigned long end)
args.start = start; args.start = start;
args.end = end; args.end = end;
on_each_cpu(sb1_flush_icache_range_ipi, &args, 1, 1); sb1_on_each_cpu(sb1_flush_icache_range_ipi, &args, 1, 1);
} }
#else #else
void sb1_flush_icache_range(unsigned long start, unsigned long end) void sb1_flush_icache_range(unsigned long start, unsigned long end)
@ -326,7 +335,7 @@ static void sb1_flush_cache_sigtramp_ipi(void *info)
static void sb1_flush_cache_sigtramp(unsigned long addr) static void sb1_flush_cache_sigtramp(unsigned long addr)
{ {
on_each_cpu(sb1_flush_cache_sigtramp_ipi, (void *) addr, 1, 1); sb1_on_each_cpu(sb1_flush_cache_sigtramp_ipi, (void *) addr, 1, 1);
} }
#else #else
void sb1_flush_cache_sigtramp(unsigned long addr) void sb1_flush_cache_sigtramp(unsigned long addr)