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USB: r8a66597-hcd: Add support for SH7366 USB host
R8A66597 is similar to SH7366 USB 2.0 Host/Function module. It can support SH7366 USB host by changing several R8A66597 code. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Yoshihiro Shimoda
Greg Kroah-Hartman
parent
29fab0cd89
commit
9424ea2965
@ -260,3 +260,9 @@ config USB_R8A66597_HCD
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To compile this driver as a module, choose M here: the
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module will be called r8a66597-hcd.
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config SUPERH_ON_CHIP_R8A66597
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boolean "Enable SuperH on-chip USB like the R8A66597"
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depends on USB_R8A66597_HCD && CPU_SUBTYPE_SH7366
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help
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Renesas SuperH processor has USB like the R8A66597.
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This driver supported processor is SH7366.
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@ -51,10 +51,12 @@ MODULE_ALIAS("platform:r8a66597_hcd");
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static const char hcd_name[] = "r8a66597_hcd";
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/* module parameters */
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#if !defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
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static unsigned short clock = XTAL12;
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module_param(clock, ushort, 0644);
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MODULE_PARM_DESC(clock, "input clock: 48MHz=32768, 24MHz=16384, 12MHz=0 "
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"(default=0)");
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#endif
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static unsigned short vif = LDRV;
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module_param(vif, ushort, 0644);
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@ -106,11 +108,22 @@ static void set_devadd_reg(struct r8a66597 *r8a66597, u8 r8a66597_address,
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r8a66597_write(r8a66597, val, devadd_reg);
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}
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static int enable_controller(struct r8a66597 *r8a66597)
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static int r8a66597_clock_enable(struct r8a66597 *r8a66597)
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{
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u16 tmp;
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int i = 0;
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#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
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do {
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r8a66597_write(r8a66597, SCKE, SYSCFG0);
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tmp = r8a66597_read(r8a66597, SYSCFG0);
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if (i++ > 1000) {
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err("register access fail.");
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return -ENXIO;
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}
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} while ((tmp & SCKE) != SCKE);
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r8a66597_write(r8a66597, 0x04, 0x02);
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#else
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do {
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r8a66597_write(r8a66597, USBE, SYSCFG0);
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tmp = r8a66597_read(r8a66597, SYSCFG0);
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@ -132,13 +145,63 @@ static int enable_controller(struct r8a66597 *r8a66597)
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return -ENXIO;
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}
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} while ((tmp & SCKE) != SCKE);
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#endif /* #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) */
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r8a66597_bset(r8a66597, DCFM | DRPD, SYSCFG0);
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r8a66597_bset(r8a66597, DRPD, SYSCFG1);
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return 0;
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}
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static void r8a66597_clock_disable(struct r8a66597 *r8a66597)
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{
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r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
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udelay(1);
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#if !defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
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r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
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r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
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r8a66597_bclr(r8a66597, USBE, SYSCFG0);
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#endif
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}
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static void r8a66597_enable_port(struct r8a66597 *r8a66597, int port)
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{
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u16 val;
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val = port ? DRPD : DCFM | DRPD;
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r8a66597_bset(r8a66597, val, get_syscfg_reg(port));
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r8a66597_bset(r8a66597, HSE, get_syscfg_reg(port));
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r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR, get_dmacfg_reg(port));
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r8a66597_bclr(r8a66597, DTCHE, get_intenb_reg(port));
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r8a66597_bset(r8a66597, ATTCHE, get_intenb_reg(port));
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}
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static void r8a66597_disable_port(struct r8a66597 *r8a66597, int port)
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{
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u16 val, tmp;
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r8a66597_write(r8a66597, 0, get_intenb_reg(port));
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r8a66597_write(r8a66597, 0, get_intsts_reg(port));
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r8a66597_port_power(r8a66597, port, 0);
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do {
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tmp = r8a66597_read(r8a66597, SOFCFG) & EDGESTS;
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udelay(640);
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} while (tmp == EDGESTS);
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val = port ? DRPD : DCFM | DRPD;
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r8a66597_bclr(r8a66597, val, get_syscfg_reg(port));
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r8a66597_bclr(r8a66597, HSE, get_syscfg_reg(port));
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}
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static int enable_controller(struct r8a66597 *r8a66597)
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{
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int ret, port;
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ret = r8a66597_clock_enable(r8a66597);
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if (ret < 0)
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return ret;
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r8a66597_bset(r8a66597, vif & LDRV, PINCFG);
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r8a66597_bset(r8a66597, HSE, SYSCFG0);
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r8a66597_bset(r8a66597, HSE, SYSCFG1);
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r8a66597_bset(r8a66597, USBE, SYSCFG0);
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r8a66597_bset(r8a66597, BEMPE | NRDYE | BRDYE, INTENB0);
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@ -146,53 +209,30 @@ static int enable_controller(struct r8a66597 *r8a66597)
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r8a66597_bset(r8a66597, BRDY0, BRDYENB);
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r8a66597_bset(r8a66597, BEMP0, BEMPENB);
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r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR, DMA0CFG);
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r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR, DMA1CFG);
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r8a66597_bset(r8a66597, endian & BIGEND, CFIFOSEL);
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r8a66597_bset(r8a66597, endian & BIGEND, D0FIFOSEL);
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r8a66597_bset(r8a66597, endian & BIGEND, D1FIFOSEL);
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r8a66597_bset(r8a66597, TRNENSEL, SOFCFG);
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r8a66597_bset(r8a66597, SIGNE | SACKE, INTENB1);
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r8a66597_bclr(r8a66597, DTCHE, INTENB1);
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r8a66597_bset(r8a66597, ATTCHE, INTENB1);
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r8a66597_bclr(r8a66597, DTCHE, INTENB2);
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r8a66597_bset(r8a66597, ATTCHE, INTENB2);
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for (port = 0; port < R8A66597_MAX_ROOT_HUB; port++)
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r8a66597_enable_port(r8a66597, port);
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return 0;
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}
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static void disable_controller(struct r8a66597 *r8a66597)
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{
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u16 tmp;
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int port;
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r8a66597_write(r8a66597, 0, INTENB0);
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r8a66597_write(r8a66597, 0, INTENB1);
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r8a66597_write(r8a66597, 0, INTENB2);
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r8a66597_write(r8a66597, 0, INTSTS0);
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r8a66597_write(r8a66597, 0, INTSTS1);
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r8a66597_write(r8a66597, 0, INTSTS2);
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r8a66597_port_power(r8a66597, 0, 0);
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r8a66597_port_power(r8a66597, 1, 0);
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for (port = 0; port < R8A66597_MAX_ROOT_HUB; port++)
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r8a66597_disable_port(r8a66597, port);
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do {
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tmp = r8a66597_read(r8a66597, SOFCFG) & EDGESTS;
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udelay(640);
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} while (tmp == EDGESTS);
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r8a66597_bclr(r8a66597, DCFM | DRPD, SYSCFG0);
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r8a66597_bclr(r8a66597, DRPD, SYSCFG1);
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r8a66597_bclr(r8a66597, HSE, SYSCFG0);
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r8a66597_bclr(r8a66597, HSE, SYSCFG1);
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r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
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udelay(1);
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r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
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r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
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r8a66597_bclr(r8a66597, USBE, SYSCFG0);
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r8a66597_clock_disable(r8a66597);
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}
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static int get_parent_r8a66597_address(struct r8a66597 *r8a66597,
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@ -711,6 +751,7 @@ static void enable_r8a66597_pipe_dma(struct r8a66597 *r8a66597,
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struct r8a66597_pipe *pipe,
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struct urb *urb)
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{
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#if !defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
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int i;
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struct r8a66597_pipe_info *info = &pipe->info;
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@ -738,6 +779,7 @@ static void enable_r8a66597_pipe_dma(struct r8a66597 *r8a66597,
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break;
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}
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}
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#endif /* #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) */
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}
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/* this function must be called with interrupt disabled */
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@ -1054,8 +1096,7 @@ static void prepare_status_packet(struct r8a66597 *r8a66597,
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r8a66597_mdfy(r8a66597, ISEL, ISEL | CURPIPE, CFIFOSEL);
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r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0);
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r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
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r8a66597_write(r8a66597, BCLR, CFIFOCTR);
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r8a66597_write(r8a66597, BVAL, CFIFOCTR);
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r8a66597_write(r8a66597, BCLR | BVAL, CFIFOCTR);
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enable_irq_empty(r8a66597, 0);
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} else {
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r8a66597_bclr(r8a66597, R8A66597_DIR, DCPCFG);
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@ -187,7 +187,11 @@
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#define REW 0x4000 /* b14: Buffer rewind */
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#define DCLRM 0x2000 /* b13: DMA buffer clear mode */
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#define DREQE 0x1000 /* b12: DREQ output enable */
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#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
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#define MBW 0x0800
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#else
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#define MBW 0x0400 /* b10: Maximum bit width for FIFO access */
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#endif
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#define MBW_8 0x0000 /* 8bit */
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#define MBW_16 0x0400 /* 16bit */
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#define BIGEND 0x0100 /* b8: Big endian mode */
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@ -395,7 +399,11 @@
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#define R8A66597_MAX_NUM_PIPE 10
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#define R8A66597_BUF_BSIZE 8
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#define R8A66597_MAX_DEVICE 10
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#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
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#define R8A66597_MAX_ROOT_HUB 1
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#else
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#define R8A66597_MAX_ROOT_HUB 2
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#endif
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#define R8A66597_MAX_SAMPLING 5
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#define R8A66597_RH_POLL_TIME 10
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#define R8A66597_MAX_DMA_CHANNEL 2
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@ -530,8 +538,21 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
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unsigned long offset, u16 *buf,
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int len)
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{
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#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
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unsigned long fifoaddr = r8a66597->reg + offset;
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unsigned long count;
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count = len / 4;
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insl(fifoaddr, buf, count);
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if (len & 0x00000003) {
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unsigned long tmp = inl(fifoaddr);
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memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03);
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}
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#else
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len = (len + 1) / 2;
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insw(r8a66597->reg + offset, buf, len);
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#endif
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}
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static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
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@ -545,6 +566,24 @@ static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
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int len)
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{
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unsigned long fifoaddr = r8a66597->reg + offset;
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#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
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unsigned long count;
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unsigned char *pb;
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int i;
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count = len / 4;
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outsl(fifoaddr, buf, count);
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if (len & 0x00000003) {
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pb = (unsigned char *)buf + count * 4;
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for (i = 0; i < (len & 0x00000003); i++) {
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if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
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outb(pb[i], fifoaddr + i);
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else
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outb(pb[i], fifoaddr + 3 - i);
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}
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}
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#else
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int odd = len & 0x0001;
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len = len / 2;
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@ -553,6 +592,7 @@ static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
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buf = &buf[len];
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outb((unsigned char)*buf, fifoaddr);
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}
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#endif
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}
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static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
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@ -585,6 +625,11 @@ static inline unsigned long get_dvstctr_reg(int port)
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return port == 0 ? DVSTCTR0 : DVSTCTR1;
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}
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static inline unsigned long get_dmacfg_reg(int port)
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{
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return port == 0 ? DMA0CFG : DMA1CFG;
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}
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static inline unsigned long get_intenb_reg(int port)
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{
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return port == 0 ? INTENB1 : INTENB2;
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