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clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs

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The default PLL2/3/4/6 multiplier and divider configurations are no
longer used after the conversion to fixed or variable fractional PLL
clock types.

Note that the default configurations are still documented in the
comments above the individual rcar_gen4_cpg_pll_config instances.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/d13526a86066992d6afdf9bee7c1a18da72f914f.1721648548.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2024-07-22 13:50:35 +02:00
parent f7444f0fde
commit 93d46d465f
5 changed files with 20 additions and 28 deletions
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10
drivers/clk/renesas/r8a779a0-cpg-mssr.c
View File

@ -259,11 +259,11 @@ static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] __initconst = {
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
{ 1, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 16, },
{ 1, 106, 1, 0, 0, 0, 0, 120, 1, 160, 1, 0, 0, 19, },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
{ 2, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 32, },
/* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */
{ 1, 128, 1, 192, 1, 16, },
{ 1, 106, 1, 160, 1, 19, },
{ 0, 0, 0, 0, 0, 0, },
{ 2, 128, 1, 192, 1, 32, },
};

10
drivers/clk/renesas/r8a779f0-cpg-mssr.c
View File

@ -188,11 +188,11 @@ static const unsigned int r8a779f0_crit_mod_clks[] __initconst = {
(((md) & BIT(13)) >> 13))
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] __initconst = {
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
{ 1, 200, 1, 150, 1, 200, 1, 0, 0, 200, 1, 134, 1, 15, },
{ 1, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 19, },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
{ 2, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 38, },
/* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */
{ 1, 200, 1, 200, 1, 15, },
{ 1, 160, 1, 160, 1, 19, },
{ 0, 0, 0, 0, 0, 0, },
{ 2, 160, 1, 160, 1, 38, },
};
static int __init r8a779f0_cpg_mssr_init(struct device *dev)

10
drivers/clk/renesas/r8a779g0-cpg-mssr.c
View File

@ -259,11 +259,11 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
(((md) & BIT(13)) >> 13))
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] __initconst = {
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
{ 1, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 16, },
{ 1, 160, 1, 170, 1, 160, 1, 120, 1, 160, 1, 140, 1, 19, },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
{ 2, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 32, },
/* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */
{ 1, 192, 1, 192, 1, 16, },
{ 1, 160, 1, 160, 1, 19, },
{ 0, 0, 0, 0, 0, 0, },
{ 2, 192, 1, 192, 1, 32, },
};
static int __init r8a779g0_cpg_mssr_init(struct device *dev)

10
drivers/clk/renesas/r8a779h0-cpg-mssr.c
View File

@ -254,11 +254,11 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = {
(((md) & BIT(13)) >> 13))
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] __initconst = {
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
{ 1, 192, 1, 240, 1, 192, 1, 240, 1, 192, 1, 168, 1, 16, },
{ 1, 160, 1, 200, 1, 160, 1, 200, 1, 160, 1, 140, 1, 19, },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
{ 2, 192, 1, 240, 1, 192, 1, 240, 1, 192, 1, 168, 1, 32, },
/* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */
{ 1, 192, 1, 192, 1, 16, },
{ 1, 160, 1, 160, 1, 19, },
{ 0, 0, 0, 0, 0, 0, },
{ 2, 192, 1, 192, 1, 32, },
};
static int __init r8a779h0_cpg_mssr_init(struct device *dev)

8
drivers/clk/renesas/rcar-gen4-cpg.h
View File

@ -65,16 +65,8 @@ struct rcar_gen4_cpg_pll_config {
u8 extal_div;
u8 pll1_mult;
u8 pll1_div;
u8 pll2_mult;
u8 pll2_div;
u8 pll3_mult;
u8 pll3_div;
u8 pll4_mult;
u8 pll4_div;
u8 pll5_mult;
u8 pll5_div;
u8 pll6_mult;
u8 pll6_div;
u8 osc_prediv;
};