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KVM: x86: Set emulated/transmuted feature bits via kvm_cpu_caps

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Set emulated and transmuted (set based on other features) feature bits
via kvm_cpu_caps now that the CPUID output for KVM_GET_SUPPORTED_CPUID
is direcly overidden with kvm_cpu_caps.

Note, VMX emulation of UMIP already sets kvm_cpu_caps.

No functional change intended.

Reviewed-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Sean Christopherson 2020-03-02 15:56:54 -08:00 committed by Paolo Bonzini
parent bd79199990
commit 93c380e7b5
3 changed files with 41 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

72
arch/x86/kvm/cpuid.c
View File

@ -306,6 +306,8 @@ void kvm_set_cpu_caps(void)
0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
F(F16C) | F(RDRAND) F(F16C) | F(RDRAND)
); );
/* KVM emulates x2apic in software irrespective of host support. */
kvm_cpu_cap_set(X86_FEATURE_X2APIC);
kvm_cpu_cap_mask(CPUID_1_EDX, kvm_cpu_cap_mask(CPUID_1_EDX,
F(FPU) | F(VME) | F(DE) | F(PSE) | F(FPU) | F(VME) | F(DE) | F(PSE) |
@ -342,6 +344,17 @@ void kvm_set_cpu_caps(void)
F(MD_CLEAR) F(MD_CLEAR)
); );
/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST);
kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES);
if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS))
kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL);
if (boot_cpu_has(X86_FEATURE_STIBP))
kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP);
if (boot_cpu_has(X86_FEATURE_AMD_SSBD))
kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
kvm_cpu_cap_mask(CPUID_7_1_EAX, kvm_cpu_cap_mask(CPUID_7_1_EAX,
F(AVX512_BF16) F(AVX512_BF16)
); );
@ -378,6 +391,29 @@ void kvm_set_cpu_caps(void)
F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON)
); );
/*
* AMD has separate bits for each SPEC_CTRL bit.
* arch/x86/kernel/cpu/bugs.c is kind enough to
* record that in cpufeatures so use them.
*/
if (boot_cpu_has(X86_FEATURE_IBPB))
kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB);
if (boot_cpu_has(X86_FEATURE_IBRS))
kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS);
if (boot_cpu_has(X86_FEATURE_STIBP))
kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP);
if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD);
if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO);
/*
* The preference is to use SPEC CTRL MSR instead of the
* VIRT_SPEC MSR.
*/
if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
!boot_cpu_has(X86_FEATURE_AMD_SSBD))
kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
/* /*
* Hide all SVM features by default, SVM will set the cap bits for * Hide all SVM features by default, SVM will set the cap bits for
* features it emulates and/or exposes for L1. * features it emulates and/or exposes for L1.
@ -487,9 +523,6 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
case 1: case 1:
cpuid_entry_override(entry, CPUID_1_EDX); cpuid_entry_override(entry, CPUID_1_EDX);
cpuid_entry_override(entry, CPUID_1_ECX); cpuid_entry_override(entry, CPUID_1_ECX);
/* we support x2apic emulation even if host does not support
* it since we emulate x2apic in software */
cpuid_entry_set(entry, X86_FEATURE_X2APIC);
break; break;
case 2: case 2:
/* /*
@ -535,17 +568,6 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
cpuid_entry_override(entry, CPUID_7_ECX); cpuid_entry_override(entry, CPUID_7_ECX);
cpuid_entry_override(entry, CPUID_7_EDX); cpuid_entry_override(entry, CPUID_7_EDX);
/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
cpuid_entry_set(entry, X86_FEATURE_TSC_ADJUST);
cpuid_entry_set(entry, X86_FEATURE_ARCH_CAPABILITIES);
if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS))
cpuid_entry_set(entry, X86_FEATURE_SPEC_CTRL);
if (boot_cpu_has(X86_FEATURE_STIBP))
cpuid_entry_set(entry, X86_FEATURE_INTEL_STIBP);
if (boot_cpu_has(X86_FEATURE_AMD_SSBD))
cpuid_entry_set(entry, X86_FEATURE_SPEC_CTRL_SSBD);
/* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */ /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */
if (entry->eax == 1) { if (entry->eax == 1) {
entry = do_host_cpuid(array, function, 1); entry = do_host_cpuid(array, function, 1);
@ -717,28 +739,6 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
entry->eax = g_phys_as | (virt_as << 8); entry->eax = g_phys_as | (virt_as << 8);
entry->edx = 0; entry->edx = 0;
cpuid_entry_override(entry, CPUID_8000_0008_EBX); cpuid_entry_override(entry, CPUID_8000_0008_EBX);
/*
* AMD has separate bits for each SPEC_CTRL bit.
* arch/x86/kernel/cpu/bugs.c is kind enough to
* record that in cpufeatures so use them.
*/
if (boot_cpu_has(X86_FEATURE_IBPB))
cpuid_entry_set(entry, X86_FEATURE_AMD_IBPB);
if (boot_cpu_has(X86_FEATURE_IBRS))
cpuid_entry_set(entry, X86_FEATURE_AMD_IBRS);
if (boot_cpu_has(X86_FEATURE_STIBP))
cpuid_entry_set(entry, X86_FEATURE_AMD_STIBP);
if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
cpuid_entry_set(entry, X86_FEATURE_AMD_SSBD);
if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
cpuid_entry_set(entry, X86_FEATURE_AMD_SSB_NO);
/*
* The preference is to use SPEC CTRL MSR instead of the
* VIRT_SPEC MSR.
*/
if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
!boot_cpu_has(X86_FEATURE_AMD_SSBD))
cpuid_entry_set(entry, X86_FEATURE_VIRT_SSBD);
break; break;
} }
case 0x80000019: case 0x80000019:

18
arch/x86/kvm/svm.c
View File

@ -1375,6 +1375,11 @@ static __init void svm_set_cpu_caps(void)
if (nested) if (nested)
kvm_cpu_cap_set(X86_FEATURE_SVM); kvm_cpu_cap_set(X86_FEATURE_SVM);
/* CPUID 0x80000008 */
if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
boot_cpu_has(X86_FEATURE_AMD_SSBD))
kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
/* CPUID 0x8000000A */ /* CPUID 0x8000000A */
/* Support next_rip if host supports it */ /* Support next_rip if host supports it */
kvm_cpu_cap_check_and_set(X86_FEATURE_NRIPS); kvm_cpu_cap_check_and_set(X86_FEATURE_NRIPS);
@ -6051,22 +6056,9 @@ static void svm_cpuid_update(struct kvm_vcpu *vcpu)
APICV_INHIBIT_REASON_NESTED); APICV_INHIBIT_REASON_NESTED);
} }
/*
* Vendor specific emulation must be handled via ->set_supported_cpuid(), not
* svm_set_cpu_caps(), as capabilities configured during hardware_setup() are
* masked against hardware/kernel support, i.e. they'd be lost.
*
* Note, setting a flag based on a *different* feature, e.g. setting VIRT_SSBD
* if LS_CFG_SSBD or AMD_SSBD is supported, is effectively emulation.
*/
static void svm_set_supported_cpuid(struct kvm_cpuid_entry2 *entry) static void svm_set_supported_cpuid(struct kvm_cpuid_entry2 *entry)
{ {
switch (entry->function) { switch (entry->function) {
case 0x80000008:
if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
boot_cpu_has(X86_FEATURE_AMD_SSBD))
cpuid_entry_set(entry, X86_FEATURE_VIRT_SSBD);
break;
case 0x8000000A: case 0x8000000A:
entry->eax = 1; /* SVM revision 1 */ entry->eax = 1; /* SVM revision 1 */
entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper

5
arch/x86/kvm/vmx/vmx.c
View File

@ -7123,11 +7123,6 @@ static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
} }
} }
/*
* Vendor specific emulation must be handled via ->set_supported_cpuid(), not
* vmx_set_cpu_caps(), as capabilities configured during hardware_setup() are
* masked against hardware/kernel support, i.e. they'd be lost.
*/
static void vmx_set_supported_cpuid(struct kvm_cpuid_entry2 *entry) static void vmx_set_supported_cpuid(struct kvm_cpuid_entry2 *entry)
{ {
} }