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Pin control fixes for v4.17:

Browse Source 
- Two major fixes for the Intel Cherryview and Sunrisepoint
   pin controllers, adjusting numberspaces so that they do
   get aligned with various messed-up numbers encoded into
   the BIOS.
 
 - A fix for the Meson driver GPIO pin range.
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Merge tag 'pinctrl-v4.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:
 "Here are three pin control fixes.

  The Intel fixes are the most serious and important things I had queued
  since it affects a large portion of deployed Chromebooks.

   - Two major fixes for the Intel Cherryview and Sunrisepoint pin
     controllers, adjusting numberspaces so that they get aligned with
     various messed-up numbers encoded into the BIOS.

   - A fix for the Meson driver GPIO pin range"

* tag 'pinctrl-v4.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: sunrisepoint: Align GPIO number space with Windows
  pinctrl: cherryview: Associate IRQ descriptors to irqdomain
  pinctrl: meson-axg: fix the range of aobus bank
This commit is contained in:
Linus Torvalds 2018-05-08 05:37:17 -10:00
commit 93a0d34024
3 changed files with 55 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/pinctrl/intel/pinctrl-cherryview.c
View File

@ -1622,22 +1622,30 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
if (!need_valid_mask) {
irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
chip->ngpio, NUMA_NO_NODE);
community->npins, NUMA_NO_NODE);
if (irq_base < 0) {
dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
return irq_base;
}
} else {
irq_base = 0;
}
ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, irq_base,
ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0,
handle_bad_irq, IRQ_TYPE_NONE);
if (ret) {
dev_err(pctrl->dev, "failed to add IRQ chip\n");
return ret;
}
if (!need_valid_mask) {
for (i = 0; i < community->ngpio_ranges; i++) {
range = &community->gpio_ranges[i];
irq_domain_associate_many(chip->irq.domain, irq_base,
range->base, range->npins);
irq_base += range->npins;
}
}
gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq,
chv_gpio_irq_handler);
return 0;

45
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
View File

@ -36,6 +36,27 @@
.npins = ((e) - (s) + 1), \
}
#define SPTH_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define SPTH_COMMUNITY(b, s, e, g) \
{ \
.barno = (b), \
.padown_offset = SPT_PAD_OWN, \
.padcfglock_offset = SPT_PADCFGLOCK, \
.hostown_offset = SPT_HOSTSW_OWN, \
.ie_offset = SPT_GPI_IE, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
.ngpps = ARRAY_SIZE(g), \
}
/* Sunrisepoint-LP */
static const struct pinctrl_pin_desc sptlp_pins[] = {
/* GPP_A */
@ -531,10 +552,28 @@ static const struct intel_function spth_functions[] = {
FUNCTION("i2c2", spth_i2c2_groups),
};
static const struct intel_padgroup spth_community0_gpps[] = {
SPTH_GPP(0, 0, 23, 0), /* GPP_A */
SPTH_GPP(1, 24, 47, 24), /* GPP_B */
};
static const struct intel_padgroup spth_community1_gpps[] = {
SPTH_GPP(0, 48, 71, 48), /* GPP_C */
SPTH_GPP(1, 72, 95, 72), /* GPP_D */
SPTH_GPP(2, 96, 108, 96), /* GPP_E */
SPTH_GPP(3, 109, 132, 120), /* GPP_F */
SPTH_GPP(4, 133, 156, 144), /* GPP_G */
SPTH_GPP(5, 157, 180, 168), /* GPP_H */
};
static const struct intel_padgroup spth_community3_gpps[] = {
SPTH_GPP(0, 181, 191, 192), /* GPP_I */
};
static const struct intel_community spth_communities[] = {
SPT_COMMUNITY(0, 0, 47),
SPT_COMMUNITY(1, 48, 180),
SPT_COMMUNITY(2, 181, 191),
SPTH_COMMUNITY(0, 0, 47, spth_community0_gpps),
SPTH_COMMUNITY(1, 48, 180, spth_community1_gpps),
SPTH_COMMUNITY(2, 181, 191, spth_community3_gpps),
};
static const struct intel_pinctrl_soc_data spth_soc_data = {

2
drivers/pinctrl/meson/pinctrl-meson-axg.c
View File

@ -898,7 +898,7 @@ static struct meson_bank meson_axg_periphs_banks[] = {
static struct meson_bank meson_axg_aobus_banks[] = {
/* name first last irq pullen pull dir out in */
BANK("AO", GPIOAO_0, GPIOAO_9, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
BANK("AO", GPIOAO_0, GPIOAO_13, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
};
static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = {