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KVM: arm64: Plumb cp10 ID traps through the AArch64 sysreg handler
In order to enable HCR_EL2.TID3 for AArch32 guests KVM needs to handle traps where ESR_EL2.EC=0x8, which corresponds to an attempted VMRS access from an ID group register. Specifically, the MVFR{0-2} registers are accessed this way from AArch32. Conveniently, these registers are architecturally mapped to MVFR{0-2}_EL1 in AArch64. Furthermore, KVM already handles reads to these aliases in AArch64. Plumb VMRS read traps through to the general AArch64 system register handler. Signed-off-by: Oliver Upton <oupton@google.com> Reviewed-by: Reiji Watanabe <reijiw@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220503060205.2823727-5-oupton@google.com
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@ -683,6 +683,7 @@ int kvm_handle_cp14_64(struct kvm_vcpu *vcpu);
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int kvm_handle_cp15_32(struct kvm_vcpu *vcpu);
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int kvm_handle_cp15_64(struct kvm_vcpu *vcpu);
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int kvm_handle_sys_reg(struct kvm_vcpu *vcpu);
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int kvm_handle_cp10_id(struct kvm_vcpu *vcpu);
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void kvm_reset_sys_regs(struct kvm_vcpu *vcpu);
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@ -167,6 +167,7 @@ static exit_handle_fn arm_exit_handlers[] = {
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[ESR_ELx_EC_CP15_64] = kvm_handle_cp15_64,
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[ESR_ELx_EC_CP14_MR] = kvm_handle_cp14_32,
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[ESR_ELx_EC_CP14_LS] = kvm_handle_cp14_load_store,
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[ESR_ELx_EC_CP10_ID] = kvm_handle_cp10_id,
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[ESR_ELx_EC_CP14_64] = kvm_handle_cp14_64,
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[ESR_ELx_EC_HVC32] = handle_hvc,
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[ESR_ELx_EC_SMC32] = handle_smc,
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@ -2346,6 +2346,77 @@ static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
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static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params);
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/*
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* The CP10 ID registers are architecturally mapped to AArch64 feature
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* registers. Abuse that fact so we can rely on the AArch64 handler for accesses
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* from AArch32.
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*/
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static bool kvm_esr_cp10_id_to_sys64(u32 esr, struct sys_reg_params *params)
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{
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u8 reg_id = (esr >> 10) & 0xf;
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bool valid;
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params->is_write = ((esr & 1) == 0);
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params->Op0 = 3;
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params->Op1 = 0;
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params->CRn = 0;
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params->CRm = 3;
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/* CP10 ID registers are read-only */
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valid = !params->is_write;
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switch (reg_id) {
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/* MVFR0 */
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case 0b0111:
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params->Op2 = 0;
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break;
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/* MVFR1 */
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case 0b0110:
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params->Op2 = 1;
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break;
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/* MVFR2 */
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case 0b0101:
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params->Op2 = 2;
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break;
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default:
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valid = false;
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}
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if (valid)
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return true;
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kvm_pr_unimpl("Unhandled cp10 register %s: %u\n",
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params->is_write ? "write" : "read", reg_id);
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return false;
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}
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/**
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* kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and
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* VFP Register' from AArch32.
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* @vcpu: The vCPU pointer
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*
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* MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers.
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* Work out the correct AArch64 system register encoding and reroute to the
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* AArch64 system register emulation.
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*/
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int kvm_handle_cp10_id(struct kvm_vcpu *vcpu)
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{
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int Rt = kvm_vcpu_sys_get_rt(vcpu);
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u32 esr = kvm_vcpu_get_esr(vcpu);
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struct sys_reg_params params;
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/* UNDEF on any unhandled register access */
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if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) {
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kvm_inject_undefined(vcpu);
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return 1;
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}
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if (emulate_sys_reg(vcpu, ¶ms))
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vcpu_set_reg(vcpu, Rt, params.regval);
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return 1;
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}
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/**
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* kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where
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* CRn=0, which corresponds to the AArch32 feature
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