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ARM: tegra: re-calculate the LP1 data for Tegra30/114
This patch re-calculates the LP1 data of tegra30/114_sdram_pad_address to base on its label not rely on others. This can make easier to maintain if some other Tegra chips keep re-using these codes in the future. And change the name of tegra30_sdram_pad_save to tegra_sdram_pad_save to make it more common to other chips. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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@ -383,7 +383,7 @@ _pll_m_c_x_done:
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add r1, r1, #LOCK_DELAY
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wait_until r1, r7, r3
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adr r5, tegra30_sdram_pad_save
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adr r5, tegra_sdram_pad_save
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ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT
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str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
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@ -538,6 +538,7 @@ tegra30_sdram_pad_address:
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.word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
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.word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
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.word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
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tegra30_sdram_pad_address_end:
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tegra114_sdram_pad_address:
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.word TEGRA_EMC0_BASE + EMC_CFG @0x0
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@ -553,16 +554,17 @@ tegra114_sdram_pad_address:
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.word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28
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.word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c
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.word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30
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tegra114_sdram_pad_adress_end:
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tegra30_sdram_pad_size:
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.word tegra114_sdram_pad_address - tegra30_sdram_pad_address
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.word tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
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tegra114_sdram_pad_size:
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.word tegra30_sdram_pad_size - tegra114_sdram_pad_address
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.word tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
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.type tegra30_sdram_pad_save, %object
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tegra30_sdram_pad_save:
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.rept (tegra30_sdram_pad_size - tegra114_sdram_pad_address) / 4
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.type tegra_sdram_pad_save, %object
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tegra_sdram_pad_save:
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.rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
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.long 0
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.endr
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@ -693,7 +695,7 @@ halted:
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*/
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tegra30_sdram_self_refresh:
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adr r8, tegra30_sdram_pad_save
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adr r8, tegra_sdram_pad_save
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tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
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cmp r10, #TEGRA30
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adreq r2, tegra30_sdram_pad_address
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