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arm64: dts: mt8195: add display node for vdosys1
Add display node for vdosys1. Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230323013730.1378-1-nancy.lin@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Nancy.Lin
Matthias Brugger
parent
61ac25e529
commit
92d2c23dc2
@ -24,6 +24,22 @@
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aliases {
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gce0 = &gce0;
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gce1 = &gce1;
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ethdr0 = ðdr0;
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mutex0 = &mutex;
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mutex1 = &mutex1;
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merge1 = &merge1;
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merge2 = &merge2;
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merge3 = &merge3;
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merge4 = &merge4;
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merge5 = &merge5;
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vdo1-rdma0 = &vdo1_rdma0;
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vdo1-rdma1 = &vdo1_rdma1;
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vdo1-rdma2 = &vdo1_rdma2;
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vdo1-rdma3 = &vdo1_rdma3;
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vdo1-rdma4 = &vdo1_rdma4;
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vdo1-rdma5 = &vdo1_rdma5;
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vdo1-rdma6 = &vdo1_rdma6;
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vdo1-rdma7 = &vdo1_rdma7;
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};
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cpus {
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@ -2666,7 +2682,10 @@
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vdosys1: syscon@1c100000 {
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compatible = "mediatek,mt8195-vdosys1", "syscon";
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reg = <0 0x1c100000 0 0x1000>;
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mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
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mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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smi_common_vdo: smi@1c01b000 {
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@ -2695,6 +2714,17 @@
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power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
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};
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mutex1: mutex@1c101000 {
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compatible = "mediatek,mt8195-disp-mutex";
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reg = <0 0x1c101000 0 0x1000>;
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reg-names = "vdo1_mutex";
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interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
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power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
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clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
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clock-names = "vdo1_mutex";
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mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
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};
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larb2: larb@1c102000 {
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compatible = "mediatek,mt8195-smi-larb";
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reg = <0 0x1c102000 0 0x1000>;
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@ -2719,6 +2749,151 @@
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power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
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};
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vdo1_rdma0: rdma@1c104000 {
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compatible = "mediatek,mt8195-vdo1-rdma";
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reg = <0 0x1c104000 0 0x1000>;
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interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
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power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
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iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
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mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
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};
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vdo1_rdma1: rdma@1c105000 {
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compatible = "mediatek,mt8195-vdo1-rdma";
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reg = <0 0x1c105000 0 0x1000>;
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interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
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power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
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iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
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mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
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};
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vdo1_rdma2: rdma@1c106000 {
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compatible = "mediatek,mt8195-vdo1-rdma";
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reg = <0 0x1c106000 0 0x1000>;
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interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
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power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
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iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
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mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
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};
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vdo1_rdma3: rdma@1c107000 {
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compatible = "mediatek,mt8195-vdo1-rdma";
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reg = <0 0x1c107000 0 0x1000>;
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interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
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power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
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iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
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mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
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};
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vdo1_rdma4: rdma@1c108000 {
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compatible = "mediatek,mt8195-vdo1-rdma";
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reg = <0 0x1c108000 0 0x1000>;
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interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
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power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
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iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
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mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
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};
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vdo1_rdma5: rdma@1c109000 {
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compatible = "mediatek,mt8195-vdo1-rdma";
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reg = <0 0x1c109000 0 0x1000>;
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interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
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power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
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iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
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mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
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};
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vdo1_rdma6: rdma@1c10a000 {
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compatible = "mediatek,mt8195-vdo1-rdma";
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reg = <0 0x1c10a000 0 0x1000>;
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interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
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power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
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iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
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mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
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};
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vdo1_rdma7: rdma@1c10b000 {
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compatible = "mediatek,mt8195-vdo1-rdma";
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reg = <0 0x1c10b000 0 0x1000>;
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interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
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power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
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iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
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mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
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};
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merge1: vpp-merge@1c10c000 {
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compatible = "mediatek,mt8195-disp-merge";
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reg = <0 0x1c10c000 0 0x1000>;
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interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
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<&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
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clock-names = "merge","merge_async";
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power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
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mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
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mediatek,merge-mute = <1>;
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resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
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};
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merge2: vpp-merge@1c10d000 {
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compatible = "mediatek,mt8195-disp-merge";
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reg = <0 0x1c10d000 0 0x1000>;
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interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
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<&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
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clock-names = "merge","merge_async";
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power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
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mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
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mediatek,merge-mute = <1>;
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resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;
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};
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merge3: vpp-merge@1c10e000 {
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compatible = "mediatek,mt8195-disp-merge";
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reg = <0 0x1c10e000 0 0x1000>;
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interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
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<&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
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clock-names = "merge","merge_async";
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power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
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mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
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mediatek,merge-mute = <1>;
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resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;
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};
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merge4: vpp-merge@1c10f000 {
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compatible = "mediatek,mt8195-disp-merge";
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reg = <0 0x1c10f000 0 0x1000>;
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interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
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<&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
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clock-names = "merge","merge_async";
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power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
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mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
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mediatek,merge-mute = <1>;
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resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;
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};
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merge5: vpp-merge@1c110000 {
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compatible = "mediatek,mt8195-disp-merge";
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reg = <0 0x1c110000 0 0x1000>;
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interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
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<&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
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clock-names = "merge","merge_async";
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power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
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mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
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mediatek,merge-fifo-en = <1>;
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resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
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};
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dp_intf1: dp-intf@1c113000 {
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compatible = "mediatek,mt8195-dp-intf";
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reg = <0 0x1c113000 0 0x1000>;
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@ -2731,6 +2906,54 @@
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status = "disabled";
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};
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ethdr0: hdr-engine@1c114000 {
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compatible = "mediatek,mt8195-disp-ethdr";
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reg = <0 0x1c114000 0 0x1000>,
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<0 0x1c115000 0 0x1000>,
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<0 0x1c117000 0 0x1000>,
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<0 0x1c119000 0 0x1000>,
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<0 0x1c11a000 0 0x1000>,
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<0 0x1c11b000 0 0x1000>,
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<0 0x1c11c000 0 0x1000>;
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reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
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"vdo_be", "adl_ds";
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mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
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<&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
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<&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
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<&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
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<&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>,
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<&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>,
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<&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>;
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clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
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<&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
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<&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
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<&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
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<&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
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<&vdosys1 CLK_VDO1_HDR_VDO_BE>,
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<&vdosys1 CLK_VDO1_26M_SLOW>,
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<&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
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<&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
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<&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
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<&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
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<&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
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<&topckgen CLK_TOP_ETHDR>;
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clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
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"vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
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"gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
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"ethdr_top";
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power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
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iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
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<&iommu_vpp M4U_PORT_L3_HDR_ADL>;
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interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
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resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
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<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
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<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
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<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
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<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
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reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
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"gfx_fe1_async", "vdo_be_async";
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};
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edp_tx: edp-tx@1c500000 {
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compatible = "mediatek,mt8195-edp-tx";
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reg = <0 0x1c500000 0 0x8000>;
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