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riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1

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Add I2Srx/I2Stx0/I2Stx1 nodes and pins configuration for the
StarFive JH7110 SoC.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Xingyu Wu 2023-08-21 22:41:51 +08:00 committed by Conor Dooley
parent 4e1abae568
commit 92cfc35838
2 changed files with 123 additions and 0 deletions
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58
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
View File

@ -203,6 +203,24 @@
status = "okay";
};
&i2srx {
pinctrl-names = "default";
pinctrl-0 = <&i2srx_pins>;
status = "okay";
};
&i2stx0 {
pinctrl-names = "default";
pinctrl-0 = <&mclk_ext_pins>;
status = "okay";
};
&i2stx1 {
pinctrl-names = "default";
pinctrl-0 = <&i2stx1_pins>;
status = "okay";
};
&mmc0 {
max-frequency = <100000000>;
bus-width = <8>;
@ -337,6 +355,46 @@
};
};
i2srx_pins: i2srx-0 {
clk-sd-pins {
pinmux = <GPIOMUX(38, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_I2SRX_BCLK)>,
<GPIOMUX(63, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_I2SRX_LRCK)>,
<GPIOMUX(38, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_I2STX1_BCLK)>,
<GPIOMUX(63, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_I2STX1_LRCK)>,
<GPIOMUX(61, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_I2SRX_SDIN0)>;
input-enable;
};
};
i2stx1_pins: i2stx1-0 {
sd-pins {
pinmux = <GPIOMUX(44, GPOUT_SYS_I2STX1_SDO0,
GPOEN_ENABLE,
GPI_NONE)>;
bias-disable;
input-disable;
};
};
mclk_ext_pins: mclk-ext-0 {
mclk-ext-pins {
pinmux = <GPIOMUX(4, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_MCLK_EXT)>;
input-enable;
};
};
mmc0_pins: mmc0-0 {
rst-pins {
pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,

65
arch/riscv/boot/dts/starfive/jh7110.dtsi
View File

@ -512,6 +512,30 @@
status = "disabled";
};
i2srx: i2s@100e0000 {
compatible = "starfive,jh7110-i2srx";
reg = <0x0 0x100e0000 0x0 0x1000>;
clocks = <&syscrg JH7110_SYSCLK_I2SRX_BCLK_MST>,
<&syscrg JH7110_SYSCLK_I2SRX_APB>,
<&syscrg JH7110_SYSCLK_MCLK>,
<&syscrg JH7110_SYSCLK_MCLK_INNER>,
<&mclk_ext>,
<&syscrg JH7110_SYSCLK_I2SRX_BCLK>,
<&syscrg JH7110_SYSCLK_I2SRX_LRCK>,
<&i2srx_bclk_ext>,
<&i2srx_lrck_ext>;
clock-names = "i2sclk", "apb", "mclk",
"mclk_inner", "mclk_ext", "bclk",
"lrck", "bclk_ext", "lrck_ext";
resets = <&syscrg JH7110_SYSRST_I2SRX_APB>,
<&syscrg JH7110_SYSRST_I2SRX_BCLK>;
dmas = <0>, <&dma 24>;
dma-names = "tx", "rx";
starfive,syscon = <&sys_syscon 0x18 0x2>;
#sound-dai-cells = <0>;
status = "disabled";
};
usb0: usb@10100000 {
compatible = "starfive,jh7110-usb";
ranges = <0x0 0x0 0x10100000 0x100000>;
@ -736,6 +760,47 @@
status = "disabled";
};
i2stx0: i2s@120b0000 {
compatible = "starfive,jh7110-i2stx0";
reg = <0x0 0x120b0000 0x0 0x1000>;
clocks = <&syscrg JH7110_SYSCLK_I2STX0_BCLK_MST>,
<&syscrg JH7110_SYSCLK_I2STX0_APB>,
<&syscrg JH7110_SYSCLK_MCLK>,
<&syscrg JH7110_SYSCLK_MCLK_INNER>,
<&mclk_ext>;
clock-names = "i2sclk", "apb", "mclk",
"mclk_inner","mclk_ext";
resets = <&syscrg JH7110_SYSRST_I2STX0_APB>,
<&syscrg JH7110_SYSRST_I2STX0_BCLK>;
dmas = <&dma 47>;
dma-names = "tx";
#sound-dai-cells = <0>;
status = "disabled";
};
i2stx1: i2s@120c0000 {
compatible = "starfive,jh7110-i2stx1";
reg = <0x0 0x120c0000 0x0 0x1000>;
clocks = <&syscrg JH7110_SYSCLK_I2STX1_BCLK_MST>,
<&syscrg JH7110_SYSCLK_I2STX1_APB>,
<&syscrg JH7110_SYSCLK_MCLK>,
<&syscrg JH7110_SYSCLK_MCLK_INNER>,
<&mclk_ext>,
<&syscrg JH7110_SYSCLK_I2STX1_BCLK>,
<&syscrg JH7110_SYSCLK_I2STX1_LRCK>,
<&i2stx_bclk_ext>,
<&i2stx_lrck_ext>;
clock-names = "i2sclk", "apb", "mclk",
"mclk_inner", "mclk_ext", "bclk",
"lrck", "bclk_ext", "lrck_ext";
resets = <&syscrg JH7110_SYSRST_I2STX1_APB>,
<&syscrg JH7110_SYSRST_I2STX1_BCLK>;
dmas = <&dma 48>;
dma-names = "tx";
#sound-dai-cells = <0>;
status = "disabled";
};
sfctemp: temperature-sensor@120e0000 {
compatible = "starfive,jh7110-temp";
reg = <0x0 0x120e0000 0x0 0x10000>;