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arm64: dts: ti: k3-j721e-*: add DP & DP PHY

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Add DT nodes for DisplayPort and DisplayPort PHY. The DP is Cadence MHDP
8546 and the PHY is a Cadence Torrent PHY with TI WIZ wrapper.

Also add the required phy link nodes in the board dts files.

A slight irregularity in the bindings is the DPTX PHY register block,
which is in the MHDP IP, but is needed and mapped by the PHY.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Rahul T R <r-ravikumar@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com>
Link: https://lore.kernel.org/r/20220429112639.13004-2-r-ravikumar@ti.com
This commit is contained in:
Tomi Valkeinen 2022-04-29 16:56:38 +05:30 committed by Vignesh Raghavendra
parent c024c46fe1
commit 92c996f4ce
3 changed files with 105 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
View File

@ -793,6 +793,22 @@
};
};
&serdes4 {
torrent_phy_dp: phy@0 {
reg = <0>;
resets = <&serdes_wiz4 1>;
cdns,phy-type = <PHY_TYPE_DP>;
cdns,num-lanes = <4>;
cdns,max-bit-rate = <5400>;
#phy-cells = <0>;
};
};
&mhdp {
phys = <&torrent_phy_dp>;
phy-names = "dpphy";
};
&pcie0_rc {
reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
phys = <&serdes0_pcie_link>;

75
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
View File

@ -5,6 +5,7 @@
* Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/phy/phy-ti.h>
#include <dt-bindings/mux/mux.h>
#include <dt-bindings/mux/ti-serdes.h>
@ -789,6 +790,47 @@
#size-cells = <2>;
};
serdes_wiz4: wiz@5050000 {
compatible = "ti,am64-wiz-10g";
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 297 9>;
assigned-clock-parents = <&k3_clks 297 10>;
assigned-clock-rates = <19200000>;
num-lanes = <4>;
#reset-cells = <1>;
#clock-cells = <1>;
ranges = <0x05050000 0x00 0x05050000 0x010000>,
<0x0a030a00 0x00 0x0a030a00 0x40>;
serdes4: serdes@5050000 {
/*
* Note: we also map DPTX PHY registers as the Torrent
* needs to manage those.
*/
compatible = "ti,j721e-serdes-10g";
reg = <0x05050000 0x010000>,
<0x0a030a00 0x40>; /* DPTX PHY */
reg-names = "torrent_phy", "dptx_phy";
resets = <&serdes_wiz4 0>;
reset-names = "torrent_reset";
clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>;
clock-names = "refclk";
assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
<&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
assigned-clock-parents = <&k3_clks 297 9>,
<&k3_clks 297 9>,
<&k3_clks 297 9>;
#address-cells = <1>;
#size-cells = <0>;
};
};
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
@ -1267,6 +1309,37 @@
};
};
mhdp: dp-bridge@a000000 {
compatible = "ti,j721e-mhdp8546";
/*
* Note: we do not map DPTX PHY area, as that is handled by
* the PHY driver.
*/
reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
<0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */
reg-names = "mhdptx", "j721e-intg";
clocks = <&k3_clks 151 36>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
dp0_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@4 {
reg = <4>;
};
};
};
dss: dss@4a00000 {
compatible = "ti,j721e-dss";
reg =
@ -1317,8 +1390,6 @@
"common_s2";
dss_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
};
};

16
arch/arm64/boot/dts/ti/k3-j721e-sk.dts
View File

@ -624,6 +624,22 @@
};
};
&serdes4 {
torrent_phy_dp: phy@0 {
reg = <0>;
resets = <&serdes_wiz4 1>;
cdns,phy-type = <PHY_TYPE_DP>;
cdns,num-lanes = <4>;
cdns,max-bit-rate = <5400>;
#phy-cells = <0>;
};
};
&mhdp {
phys = <&torrent_phy_dp>;
phy-names = "dpphy";
};
&usbss0 {
pinctrl-names = "default";
pinctrl-0 = <&main_usbss0_pins_default>;