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drm/amdgpu/gfx8: apply dynamic cu mask to APUs as well
Confirmed with the hw team. It's the same for all asics. Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -4622,12 +4622,10 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
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mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
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mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
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mqd->compute_misc_reserved = 0x00000003;
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if (!(adev->flags & AMD_IS_APU)) {
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mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr
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+ offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
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mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr
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+ offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
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}
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mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr
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+ offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
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mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr
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+ offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
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eop_base_addr = ring->eop_gpu_addr >> 8;
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mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
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mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
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