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The mxs cleanup for 3.10:

Browse Source 
* Clean up timer code and move it into drivers/clocksource
 * Clean up icoll code and move it into drivers/irqchip
 * Clean up clock code to not include <mach/*> headers
 * Clean up rtc-stmp3xxx, mxs-lradc and mxs-saif to not include <mach/*>
   headers
 * Clean up mach-mxs code to get it prepared for multiplatform support
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Merge tag 'mxs-cleanup-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/cleanup

From Shawn Guo <shawn.guo@linaro.org>:

The mxs cleanup for 3.10:

* Clean up timer code and move it into drivers/clocksource
* Clean up icoll code and move it into drivers/irqchip
* Clean up clock code to not include <mach/*> headers
* Clean up rtc-stmp3xxx, mxs-lradc and mxs-saif to not include <mach/*>
  headers
* Clean up mach-mxs code to get it prepared for multiplatform support

* tag 'mxs-cleanup-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6: (26 commits)
  clocksource: mxs_timer: Add semicolon at end of line
  ARM: mxs: remove unused headers
  ARM: mxs: merge imx23 and imx28 into one machine_desc
  ARM: mxs: remove common.h
  ARM: mxs: move mxs_get_ocotp() into mach-mxs.c
  ARM: mxs: remove mm.c
  ARM: mxs: use debug_ll_io_init for low-level debug
  ARM: mxs: get ocotp base address from device tree
  ARM: mxs: remove system.c
  ARM: mxs: get reset address from device tree
  ARM: mxs: remove empty hardware.h
  ASoC: mxs-saif: remove mach header inclusion
  iio: mxs-lradc: remove unneeded mach header inclusion
  rtc: stmp3xxx: use stmp_reset_block() instead
  clk: mxs: remove the use of mach level IO accessor
  clk: mxs: get base address from device tree
  ARM: mxs: remove unneeded mach-types.h inclusion
  ARM: mxs: move icoll driver into drivers/irqchip
  ARM: mxs: call stmp_reset_block() in icoll
  ARM: mxs: get icoll base address from device tree
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2013-04-09 15:29:52 +02:00
commit 92202876a3
26 changed files with 280 additions and 991 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/Kconfig
View File

@ -473,12 +473,14 @@ config ARCH_MXS
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CLKSRC_OF
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select HAVE_CLK_PREPARE
select MULTI_IRQ_HANDLER
select PINCTRL
select SPARSE_IRQ
select STMP_DEVICE
select USE_OF
help
Support for Freescale MXS-based family of processors

5
arch/arm/boot/dts/imx23.dtsi
View File

@ -295,6 +295,7 @@
};
digctl@8001c000 {
compatible = "fsl,imx23-digctl";
reg = <0x8001c000 2000>;
status = "disabled";
};
@ -321,6 +322,7 @@
};
ocotp@8002c000 {
compatible = "fsl,ocotp";
reg = <0x8002c000 0x2000>;
status = "disabled";
};
@ -360,7 +362,7 @@
ranges;
clks: clkctrl@80040000 {
compatible = "fsl,imx23-clkctrl";
compatible = "fsl,imx23-clkctrl", "fsl,clkctrl";
reg = <0x80040000 0x2000>;
#clock-cells = <1>;
};
@ -426,6 +428,7 @@
compatible = "fsl,imx23-timrot", "fsl,timrot";
reg = <0x80068000 0x2000>;
interrupts = <28 29 30 31>;
clocks = <&clks 28>;
};
auart0: serial@8006c000 {

5
arch/arm/boot/dts/imx28.dtsi
View File

@ -647,6 +647,7 @@
};
digctl@8001c000 {
compatible = "fsl,imx28-digctl";
reg = <0x8001c000 0x2000>;
interrupts = <89>;
status = "disabled";
@ -676,6 +677,7 @@
};
ocotp@8002c000 {
compatible = "fsl,ocotp";
reg = <0x8002c000 0x2000>;
status = "disabled";
};
@ -755,7 +757,7 @@
ranges;
clks: clkctrl@80040000 {
compatible = "fsl,imx28-clkctrl";
compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
reg = <0x80040000 0x2000>;
#clock-cells = <1>;
};
@ -838,6 +840,7 @@
compatible = "fsl,imx28-timrot", "fsl,timrot";
reg = <0x80068000 0x2000>;
interrupts = <48 49 50 51>;
clocks = <&clks 26>;
};
auart0: serial@8006a000 {

4
arch/arm/mach-mxs/Makefile
View File

@ -1,6 +1,2 @@
# Common support
obj-y := icoll.o ocotp.o system.o timer.o mm.o
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o

29
arch/arm/mach-mxs/include/mach/common.h
View File

@ -1,29 +0,0 @@
/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __MACH_MXS_COMMON_H__
#define __MACH_MXS_COMMON_H__
extern const u32 *mxs_get_ocotp(void);
extern int mxs_reset_block(void __iomem *);
extern void mxs_timer_init(void);
extern void mxs_restart(char, const char *);
extern int mxs_saif_clkmux_select(unsigned int clkmux);
extern int mx23_clocks_init(void);
extern void mx23_map_io(void);
extern int mx28_clocks_init(void);
extern void mx28_map_io(void);
extern void icoll_init_irq(void);
extern void icoll_handle_irq(struct pt_regs *);
#endif /* __MACH_MXS_COMMON_H__ */

9
arch/arm/mach-mxs/include/mach/debug-macro.S
View File

@ -11,16 +11,13 @@
*
*/
#include <mach/mx23.h>
#include <mach/mx28.h>
#ifdef CONFIG_DEBUG_IMX23_UART
#define UART_PADDR MX23_DUART_BASE_ADDR
#define UART_PADDR 0x80070000
#elif defined (CONFIG_DEBUG_IMX28_UART)
#define UART_PADDR MX28_DUART_BASE_ADDR
#define UART_PADDR 0x80074000
#endif
#define UART_VADDR MXS_IO_ADDRESS(UART_PADDR)
#define UART_VADDR 0xfe100000
.macro addruart, rp, rv, tmp
ldr \rp, =UART_PADDR @ physical

22
arch/arm/mach-mxs/include/mach/digctl.h
View File

@ -1,22 +0,0 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __MACH_DIGCTL_H__
#define __MACH_DIGCTL_H__
/* MXS DIGCTL SAIF CLKMUX */
#define MXS_DIGCTL_SAIF_CLKMUX_DIRECT 0x0
#define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT 0x1
#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0 0x2
#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1 0x3
#define HW_DIGCTL_CTRL 0x0
#define BP_DIGCTL_CTRL_SAIF_CLKMUX 10
#define BM_DIGCTL_CTRL_SAIF_CLKMUX (0x3 << 10)
#define HW_DIGCTL_CHIPID 0x310
#endif

23
arch/arm/mach-mxs/include/mach/hardware.h
View File

@ -1,23 +0,0 @@
/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#ifndef __MACH_MXS_HARDWARE_H__
#define __MACH_MXS_HARDWARE_H__
#endif /* __MACH_MXS_HARDWARE_H__ */

169
arch/arm/mach-mxs/include/mach/mx23.h
View File

@ -1,169 +0,0 @@
/*
* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#ifndef __MACH_MX23_H__
#define __MACH_MX23_H__
#include <mach/mxs.h>
/*
* OCRAM
*/
#define MX23_OCRAM_BASE_ADDR 0x00000000
#define MX23_OCRAM_SIZE SZ_32K
/*
* IO
*/
#define MX23_IO_BASE_ADDR 0x80000000
#define MX23_IO_SIZE SZ_1M
#define MX23_ICOLL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x000000)
#define MX23_APBH_DMA_BASE_ADDR (MX23_IO_BASE_ADDR + 0x004000)
#define MX23_BCH_BASE_ADDR (MX23_IO_BASE_ADDR + 0x00a000)
#define MX23_GPMI_BASE_ADDR (MX23_IO_BASE_ADDR + 0x00c000)
#define MX23_SSP1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x010000)
#define MX23_PINCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x018000)
#define MX23_DIGCTL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x01c000)
#define MX23_ETM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x020000)
#define MX23_APBX_DMA_BASE_ADDR (MX23_IO_BASE_ADDR + 0x024000)
#define MX23_DCP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x028000)
#define MX23_PXP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02a000)
#define MX23_OCOTP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02c000)
#define MX23_AXI_AHB0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02e000)
#define MX23_LCDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x030000)
#define MX23_SSP2_BASE_ADDR (MX23_IO_BASE_ADDR + 0x034000)
#define MX23_TVENC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x038000)
#define MX23_CLKCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x040000)
#define MX23_SAIF0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x042000)
#define MX23_POWER_BASE_ADDR (MX23_IO_BASE_ADDR + 0x044000)
#define MX23_SAIF1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x046000)
#define MX23_AUDIOOUT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x048000)
#define MX23_AUDIOIN_BASE_ADDR (MX23_IO_BASE_ADDR + 0x04c000)
#define MX23_LRADC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x050000)
#define MX23_SPDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x054000)
#define MX23_I2C_BASE_ADDR (MX23_IO_BASE_ADDR + 0x058000)
#define MX23_RTC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x05c000)
#define MX23_PWM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x064000)
#define MX23_TIMROT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x068000)
#define MX23_AUART1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x06c000)
#define MX23_AUART2_BASE_ADDR (MX23_IO_BASE_ADDR + 0x06e000)
#define MX23_DUART_BASE_ADDR (MX23_IO_BASE_ADDR + 0x070000)
#define MX23_USBPHY_BASE_ADDR (MX23_IO_BASE_ADDR + 0x07c000)
#define MX23_USBCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x080000)
#define MX23_DRAM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x0e0000)
#define MX23_IO_P2V(x) MXS_IO_P2V(x)
#define MX23_IO_ADDRESS(x) IOMEM(MX23_IO_P2V(x))
/*
* IRQ
*/
#define MX23_INT_DUART 0
#define MX23_INT_COMMS_RX 1
#define MX23_INT_COMMS_TX 1
#define MX23_INT_SSP2_ERROR 2
#define MX23_INT_VDD5V 3
#define MX23_INT_HEADPHONE_SHORT 4
#define MX23_INT_DAC_DMA 5
#define MX23_INT_DAC_ERROR 6
#define MX23_INT_ADC_DMA 7
#define MX23_INT_ADC_ERROR 8
#define MX23_INT_SPDIF_DMA 9
#define MX23_INT_SAIF2_DMA 9
#define MX23_INT_SPDIF_ERROR 10
#define MX23_INT_SAIF1_IRQ 10
#define MX23_INT_SAIF2_IRQ 10
#define MX23_INT_USB_CTRL 11
#define MX23_INT_USB_WAKEUP 12
#define MX23_INT_GPMI_DMA 13
#define MX23_INT_SSP1_DMA 14
#define MX23_INT_SSP1_ERROR 15
#define MX23_INT_GPIO0 16
#define MX23_INT_GPIO1 17
#define MX23_INT_GPIO2 18
#define MX23_INT_SAIF1_DMA 19
#define MX23_INT_SSP2_DMA 20
#define MX23_INT_ECC8_IRQ 21
#define MX23_INT_RTC_ALARM 22
#define MX23_INT_AUART1_TX_DMA 23
#define MX23_INT_AUART1 24
#define MX23_INT_AUART1_RX_DMA 25
#define MX23_INT_I2C_DMA 26
#define MX23_INT_I2C_ERROR 27
#define MX23_INT_TIMER0 28
#define MX23_INT_TIMER1 29
#define MX23_INT_TIMER2 30
#define MX23_INT_TIMER3 31
#define MX23_INT_BATT_BRNOUT 32
#define MX23_INT_VDDD_BRNOUT 33
#define MX23_INT_VDDIO_BRNOUT 34
#define MX23_INT_VDD18_BRNOUT 35
#define MX23_INT_TOUCH_DETECT 36
#define MX23_INT_LRADC_CH0 37
#define MX23_INT_LRADC_CH1 38
#define MX23_INT_LRADC_CH2 39
#define MX23_INT_LRADC_CH3 40
#define MX23_INT_LRADC_CH4 41
#define MX23_INT_LRADC_CH5 42
#define MX23_INT_LRADC_CH6 43
#define MX23_INT_LRADC_CH7 44
#define MX23_INT_LCDIF_DMA 45
#define MX23_INT_LCDIF_ERROR 46
#define MX23_INT_DIGCTL_DEBUG_TRAP 47
#define MX23_INT_RTC_1MSEC 48
#define MX23_INT_DRI_DMA 49
#define MX23_INT_DRI_ATTENTION 50
#define MX23_INT_GPMI_ATTENTION 51
#define MX23_INT_IR 52
#define MX23_INT_DCP_VMI 53
#define MX23_INT_DCP 54
#define MX23_INT_BCH 56
#define MX23_INT_PXP 57
#define MX23_INT_AUART2_TX_DMA 58
#define MX23_INT_AUART2 59
#define MX23_INT_AUART2_RX_DMA 60
#define MX23_INT_VDAC_DETECT 61
#define MX23_INT_VDD5V_DROOP 64
#define MX23_INT_DCDC4P2_BO 65
/*
* APBH DMA
*/
#define MX23_DMA_SSP1 1
#define MX23_DMA_SSP2 2
#define MX23_DMA_GPMI0 4
#define MX23_DMA_GPMI1 5
#define MX23_DMA_GPMI2 6
#define MX23_DMA_GPMI3 7
/*
* APBX DMA
*/
#define MX23_DMA_ADC 0
#define MX23_DMA_DAC 1
#define MX23_DMA_SPDIF 2
#define MX23_DMA_I2C 3
#define MX23_DMA_SAIF0 4
#define MX23_DMA_UART0_RX 6
#define MX23_DMA_UART0_TX 7
#define MX23_DMA_UART1_RX 8
#define MX23_DMA_UART1_TX 9
#define MX23_DMA_SAIF1 10
#endif /* __MACH_MX23_H__ */

225
arch/arm/mach-mxs/include/mach/mx28.h
View File

@ -1,225 +0,0 @@
/*
* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#ifndef __MACH_MX28_H__
#define __MACH_MX28_H__
#include <mach/mxs.h>
/*
* OCRAM
*/
#define MX28_OCRAM_BASE_ADDR 0x00000000
#define MX28_OCRAM_SIZE SZ_128K
/*
* IO
*/
#define MX28_IO_BASE_ADDR 0x80000000
#define MX28_IO_SIZE SZ_1M
#define MX28_ICOLL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x000000)
#define MX28_HSADC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x002000)
#define MX28_APBH_DMA_BASE_ADDR (MX28_IO_BASE_ADDR + 0x004000)
#define MX28_PERFMON_BASE_ADDR (MX28_IO_BASE_ADDR + 0x006000)
#define MX28_BCH_BASE_ADDR (MX28_IO_BASE_ADDR + 0x00a000)
#define MX28_GPMI_BASE_ADDR (MX28_IO_BASE_ADDR + 0x00c000)
#define MX28_SSP0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x010000)
#define MX28_SSP1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x012000)
#define MX28_SSP2_BASE_ADDR (MX28_IO_BASE_ADDR + 0x014000)
#define MX28_SSP3_BASE_ADDR (MX28_IO_BASE_ADDR + 0x016000)
#define MX28_PINCTRL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x018000)
#define MX28_DIGCTL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x01c000)
#define MX28_ETM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x022000)
#define MX28_APBX_DMA_BASE_ADDR (MX28_IO_BASE_ADDR + 0x024000)
#define MX28_DCP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x028000)
#define MX28_PXP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02a000)
#define MX28_OCOTP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02c000)
#define MX28_AXI_AHB0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02e000)
#define MX28_LCDIF_BASE_ADDR (MX28_IO_BASE_ADDR + 0x030000)
#define MX28_CAN0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x032000)
#define MX28_CAN1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x034000)
#define MX28_SIMDBG_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c000)
#define MX28_SIMGPMISEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c200)
#define MX28_SIMSSPSEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c300)
#define MX28_SIMMEMSEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c400)
#define MX28_GPIOMON_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c500)
#define MX28_SIMENET_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c700)
#define MX28_ARMJTAG_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c800)
#define MX28_CLKCTRL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x040000)
#define MX28_SAIF0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x042000)
#define MX28_POWER_BASE_ADDR (MX28_IO_BASE_ADDR + 0x044000)
#define MX28_SAIF1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x046000)
#define MX28_LRADC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x050000)
#define MX28_SPDIF_BASE_ADDR (MX28_IO_BASE_ADDR + 0x054000)
#define MX28_RTC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x056000)
#define MX28_I2C0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x058000)
#define MX28_I2C1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x05a000)
#define MX28_PWM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x064000)
#define MX28_TIMROT_BASE_ADDR (MX28_IO_BASE_ADDR + 0x068000)
#define MX28_AUART0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06a000)
#define MX28_AUART1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06c000)
#define MX28_AUART2_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06e000)
#define MX28_AUART3_BASE_ADDR (MX28_IO_BASE_ADDR + 0x070000)
#define MX28_AUART4_BASE_ADDR (MX28_IO_BASE_ADDR + 0x072000)
#define MX28_DUART_BASE_ADDR (MX28_IO_BASE_ADDR + 0x074000)
#define MX28_USBPHY0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x07C000)
#define MX28_USBPHY1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x07e000)
#define MX28_USBCTRL0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x080000)
#define MX28_USBCTRL1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x090000)
#define MX28_DFLPT_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0c0000)
#define MX28_DRAM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0e0000)
#define MX28_ENET_MAC0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0f0000)
#define MX28_ENET_MAC1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0f4000)
#define MX28_IO_P2V(x) MXS_IO_P2V(x)
#define MX28_IO_ADDRESS(x) IOMEM(MX28_IO_P2V(x))
/*
* IRQ
*/
#define MX28_INT_BATT_BRNOUT 0
#define MX28_INT_VDDD_BRNOUT 1
#define MX28_INT_VDDIO_BRNOUT 2
#define MX28_INT_VDDA_BRNOUT 3
#define MX28_INT_VDD5V_DROOP 4
#define MX28_INT_DCDC4P2_BRNOUT 5
#define MX28_INT_VDD5V 6
#define MX28_INT_CAN0 8
#define MX28_INT_CAN1 9
#define MX28_INT_LRADC_TOUCH 10
#define MX28_INT_HSADC 13
#define MX28_INT_LRADC_THRESH0 14
#define MX28_INT_LRADC_THRESH1 15
#define MX28_INT_LRADC_CH0 16
#define MX28_INT_LRADC_CH1 17
#define MX28_INT_LRADC_CH2 18
#define MX28_INT_LRADC_CH3 19
#define MX28_INT_LRADC_CH4 20
#define MX28_INT_LRADC_CH5 21
#define MX28_INT_LRADC_CH6 22
#define MX28_INT_LRADC_CH7 23
#define MX28_INT_LRADC_BUTTON0 24
#define MX28_INT_LRADC_BUTTON1 25
#define MX28_INT_PERFMON 27
#define MX28_INT_RTC_1MSEC 28
#define MX28_INT_RTC_ALARM 29
#define MX28_INT_COMMS 31
#define MX28_INT_EMI_ERR 32
#define MX28_INT_LCDIF 38
#define MX28_INT_PXP 39
#define MX28_INT_BCH 41
#define MX28_INT_GPMI 42
#define MX28_INT_SPDIF_ERROR 45
#define MX28_INT_DUART 47
#define MX28_INT_TIMER0 48
#define MX28_INT_TIMER1 49
#define MX28_INT_TIMER2 50
#define MX28_INT_TIMER3 51
#define MX28_INT_DCP_VMI 52
#define MX28_INT_DCP 53
#define MX28_INT_DCP_SECURE 54
#define MX28_INT_SAIF1 58
#define MX28_INT_SAIF0 59
#define MX28_INT_SPDIF_DMA 66
#define MX28_INT_I2C0_DMA 68
#define MX28_INT_I2C1_DMA 69
#define MX28_INT_AUART0_RX_DMA 70
#define MX28_INT_AUART0_TX_DMA 71
#define MX28_INT_AUART1_RX_DMA 72
#define MX28_INT_AUART1_TX_DMA 73
#define MX28_INT_AUART2_RX_DMA 74
#define MX28_INT_AUART2_TX_DMA 75
#define MX28_INT_AUART3_RX_DMA 76
#define MX28_INT_AUART3_TX_DMA 77
#define MX28_INT_AUART4_RX_DMA 78
#define MX28_INT_AUART4_TX_DMA 79
#define MX28_INT_SAIF0_DMA 80
#define MX28_INT_SAIF1_DMA 81
#define MX28_INT_SSP0_DMA 82
#define MX28_INT_SSP1_DMA 83
#define MX28_INT_SSP2_DMA 84
#define MX28_INT_SSP3_DMA 85
#define MX28_INT_LCDIF_DMA 86
#define MX28_INT_HSADC_DMA 87
#define MX28_INT_GPMI_DMA 88
#define MX28_INT_DIGCTL_DEBUG_TRAP 89
#define MX28_INT_USB1 92
#define MX28_INT_USB0 93
#define MX28_INT_USB1_WAKEUP 94
#define MX28_INT_USB0_WAKEUP 95
#define MX28_INT_SSP0_ERROR 96
#define MX28_INT_SSP1_ERROR 97
#define MX28_INT_SSP2_ERROR 98
#define MX28_INT_SSP3_ERROR 99
#define MX28_INT_ENET_SWI 100
#define MX28_INT_ENET_MAC0 101
#define MX28_INT_ENET_MAC1 102
#define MX28_INT_ENET_MAC0_1588 103
#define MX28_INT_ENET_MAC1_1588 104
#define MX28_INT_I2C1_ERROR 110
#define MX28_INT_I2C0_ERROR 111
#define MX28_INT_AUART0 112
#define MX28_INT_AUART1 113
#define MX28_INT_AUART2 114
#define MX28_INT_AUART3 115
#define MX28_INT_AUART4 116
#define MX28_INT_GPIO4 123
#define MX28_INT_GPIO3 124
#define MX28_INT_GPIO2 125
#define MX28_INT_GPIO1 126
#define MX28_INT_GPIO0 127
/*
* APBH DMA
*/
#define MX28_DMA_SSP0 0
#define MX28_DMA_SSP1 1
#define MX28_DMA_SSP2 2
#define MX28_DMA_SSP3 3
#define MX28_DMA_GPMI0 4
#define MX28_DMA_GPMI1 5
#define MX28_DMA_GPMI2 6
#define MX28_DMA_GPMI3 7
#define MX28_DMA_GPMI4 8
#define MX28_DMA_GPMI5 9
#define MX28_DMA_GPMI6 10
#define MX28_DMA_GPMI7 11
#define MX28_DMA_HSADC 12
#define MX28_DMA_LCDIF 13
/*
* APBX DMA
*/
#define MX28_DMA_AUART4_RX 0
#define MX28_DMA_AUART4_TX 1
#define MX28_DMA_SPDIF_TX 2
#define MX28_DMA_SAIF0 4
#define MX28_DMA_SAIF1 5
#define MX28_DMA_I2C0 6
#define MX28_DMA_I2C1 7
#define MX28_DMA_AUART0_RX 8
#define MX28_DMA_AUART0_TX 9
#define MX28_DMA_AUART1_RX 10
#define MX28_DMA_AUART1_TX 11
#define MX28_DMA_AUART2_RX 12
#define MX28_DMA_AUART2_TX 13
#define MX28_DMA_AUART3_RX 14
#define MX28_DMA_AUART3_TX 15
#endif /* __MACH_MX28_H__ */

117
arch/arm/mach-mxs/include/mach/mxs.h
View File

@ -1,117 +0,0 @@
/*
* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#ifndef __MACH_MXS_H__
#define __MACH_MXS_H__
#ifndef __ASSEMBLER__
#include <linux/io.h>
#endif
#include <asm/mach-types.h>
#include <mach/digctl.h>
#include <mach/hardware.h>
/*
* IO addresses common to MXS-based
*/
#define MXS_IO_BASE_ADDR 0x80000000
#define MXS_IO_SIZE SZ_1M
#define MXS_ICOLL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x000000)
#define MXS_APBH_DMA_BASE_ADDR (MXS_IO_BASE_ADDR + 0x004000)
#define MXS_BCH_BASE_ADDR (MXS_IO_BASE_ADDR + 0x00a000)
#define MXS_GPMI_BASE_ADDR (MXS_IO_BASE_ADDR + 0x00c000)
#define MXS_PINCTRL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x018000)
#define MXS_DIGCTL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x01c000)
#define MXS_APBX_DMA_BASE_ADDR (MXS_IO_BASE_ADDR + 0x024000)
#define MXS_DCP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x028000)
#define MXS_PXP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02a000)
#define MXS_OCOTP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02c000)
#define MXS_AXI_AHB0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02e000)
#define MXS_LCDIF_BASE_ADDR (MXS_IO_BASE_ADDR + 0x030000)
#define MXS_CLKCTRL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x040000)
#define MXS_SAIF0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x042000)
#define MXS_POWER_BASE_ADDR (MXS_IO_BASE_ADDR + 0x044000)
#define MXS_SAIF1_BASE_ADDR (MXS_IO_BASE_ADDR + 0x046000)
#define MXS_LRADC_BASE_ADDR (MXS_IO_BASE_ADDR + 0x050000)
#define MXS_SPDIF_BASE_ADDR (MXS_IO_BASE_ADDR + 0x054000)
#define MXS_I2C0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x058000)
#define MXS_PWM_BASE_ADDR (MXS_IO_BASE_ADDR + 0x064000)
#define MXS_TIMROT_BASE_ADDR (MXS_IO_BASE_ADDR + 0x068000)
#define MXS_AUART1_BASE_ADDR (MXS_IO_BASE_ADDR + 0x06c000)
#define MXS_AUART2_BASE_ADDR (MXS_IO_BASE_ADDR + 0x06e000)
#define MXS_DRAM_BASE_ADDR (MXS_IO_BASE_ADDR + 0x0e0000)
/*
* It maps the whole address space to [0xf4000000, 0xf50fffff].
*
* OCRAM 0x00000000+0x020000 -> 0xf4000000+0x020000
* IO 0x80000000+0x100000 -> 0xf5000000+0x100000
*/
#define MXS_IO_P2V(x) (0xf4000000 + \
(((x) & 0x80000000) >> 7) + \
(((x) & 0x000fffff)))
#define MXS_IO_ADDRESS(x) IOMEM(MXS_IO_P2V(x))
#define mxs_map_entry(soc, name, _type) { \
.virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
.pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \
.length = soc ## _ ## name ## _SIZE, \
.type = _type, \
}
#define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr))
#define MXS_SET_ADDR 0x4
#define MXS_CLR_ADDR 0x8
#define MXS_TOG_ADDR 0xc
#ifndef __ASSEMBLER__
static inline void __mxs_setl(u32 mask, void __iomem *reg)
{
__raw_writel(mask, reg + MXS_SET_ADDR);
}
static inline void __mxs_clrl(u32 mask, void __iomem *reg)
{
__raw_writel(mask, reg + MXS_CLR_ADDR);
}
static inline void __mxs_togl(u32 mask, void __iomem *reg)
{
__raw_writel(mask, reg + MXS_TOG_ADDR);
}
/*
* MXS CPU types
*/
#define MXS_CHIPID (MXS_IO_ADDRESS(MXS_DIGCTL_BASE_ADDR) + HW_DIGCTL_CHIPID)
static inline int cpu_is_mx23(void)
{
return ((__raw_readl(MXS_CHIPID) >> 16) == 0x3780);
}
static inline int cpu_is_mx28(void)
{
return ((__raw_readl(MXS_CHIPID) >> 16) == 0x2800);
}
#endif
#endif /* __MACH_MXS_H__ */

187
arch/arm/mach-mxs/mach-mxs.c
View File

@ -11,22 +11,53 @@
*/
#include <linux/clk.h>
#include <linux/clk/mxs.h>
#include <linux/clkdev.h>
#include <linux/clocksource.h>
#include <linux/can/platform/flexcan.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/irqchip.h>
#include <linux/irqchip/mxs.h>
#include <linux/micrel_phy.h>
#include <linux/mxsfb.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/phy.h>
#include <linux/pinctrl/consumer.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/common.h>
#include <mach/digctl.h>
#include <mach/mxs.h>
#include <asm/system_misc.h>
/* MXS DIGCTL SAIF CLKMUX */
#define MXS_DIGCTL_SAIF_CLKMUX_DIRECT 0x0
#define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT 0x1
#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0 0x2
#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1 0x3
#define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr))
#define MXS_SET_ADDR 0x4
#define MXS_CLR_ADDR 0x8
#define MXS_TOG_ADDR 0xc
static inline void __mxs_setl(u32 mask, void __iomem *reg)
{
__raw_writel(mask, reg + MXS_SET_ADDR);
}
static inline void __mxs_clrl(u32 mask, void __iomem *reg)
{
__raw_writel(mask, reg + MXS_CLR_ADDR);
}
static inline void __mxs_togl(u32 mask, void __iomem *reg)
{
__raw_writel(mask, reg + MXS_TOG_ADDR);
}
static struct fb_videomode mx23evk_video_modes[] = {
{
@ -165,14 +196,80 @@ static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = {
{ /* sentinel */ }
};
static void __init imx23_timer_init(void)
{
mx23_clocks_init();
}
#define OCOTP_WORD_OFFSET 0x20
#define OCOTP_WORD_COUNT 0x20
static void __init imx28_timer_init(void)
#define BM_OCOTP_CTRL_BUSY (1 << 8)
#define BM_OCOTP_CTRL_ERROR (1 << 9)
#define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12)
static DEFINE_MUTEX(ocotp_mutex);
static u32 ocotp_words[OCOTP_WORD_COUNT];
static const u32 *mxs_get_ocotp(void)
{
mx28_clocks_init();
struct device_node *np;
void __iomem *ocotp_base;
int timeout = 0x400;
size_t i;
static int once;
if (once)
return ocotp_words;
np = of_find_compatible_node(NULL, NULL, "fsl,ocotp");
ocotp_base = of_iomap(np, 0);
WARN_ON(!ocotp_base);
mutex_lock(&ocotp_mutex);
/*
* clk_enable(hbus_clk) for ocotp can be skipped
* as it must be on when system is running.
*/
/* try to clear ERROR bit */
__mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base);
/* check both BUSY and ERROR cleared */
while ((__raw_readl(ocotp_base) &
(BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout)
cpu_relax();
if (unlikely(!timeout))
goto error_unlock;
/* open OCOTP banks for read */
__mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
/* approximately wait 32 hclk cycles */
udelay(1);
/* poll BUSY bit becoming cleared */
timeout = 0x400;
while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout)
cpu_relax();
if (unlikely(!timeout))
goto error_unlock;
for (i = 0; i < OCOTP_WORD_COUNT; i++)
ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET +
i * 0x10);
/* close banks for power saving */
__mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
once = 1;
mutex_unlock(&ocotp_mutex);
return ocotp_words;
error_unlock:
mutex_unlock(&ocotp_mutex);
pr_err("%s: timeout in reading OCOTP\n", __func__);
return NULL;
}
enum mac_oui {
@ -454,32 +551,62 @@ static void __init mxs_machine_init(void)
imx28_evk_post_init();
}
static const char *imx23_dt_compat[] __initdata = {
#define MX23_CLKCTRL_RESET_OFFSET 0x120
#define MX28_CLKCTRL_RESET_OFFSET 0x1e0
#define MXS_CLKCTRL_RESET_CHIP (1 << 1)
/*
* Reset the system. It is called by machine_restart().
*/
static void mxs_restart(char mode, const char *cmd)
{
struct device_node *np;
void __iomem *reset_addr;
np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl");
reset_addr = of_iomap(np, 0);
if (!reset_addr)
goto soft;
if (of_device_is_compatible(np, "fsl,imx23-clkctrl"))
reset_addr += MX23_CLKCTRL_RESET_OFFSET;
else
reset_addr += MX28_CLKCTRL_RESET_OFFSET;
/* reset the chip */
__mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr);
pr_err("Failed to assert the chip reset\n");
/* Delay to allow the serial port to show the message */
mdelay(50);
soft:
/* We'll take a jump through zero as a poor second */
soft_restart(0);
}
static void __init mxs_timer_init(void)
{
if (of_machine_is_compatible("fsl,imx23"))
mx23_clocks_init();
else
mx28_clocks_init();
clocksource_of_init();
}
static const char *mxs_dt_compat[] __initdata = {
"fsl,imx28",
"fsl,imx23",
NULL,
};
static const char *imx28_dt_compat[] __initdata = {
"fsl,imx28",
NULL,
};
DT_MACHINE_START(IMX23, "Freescale i.MX23 (Device Tree)")
.map_io = mx23_map_io,
.init_irq = icoll_init_irq,
DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)")
.map_io = debug_ll_io_init,
.init_irq = irqchip_init,
.handle_irq = icoll_handle_irq,
.init_time = imx23_timer_init,
.init_time = mxs_timer_init,
.init_machine = mxs_machine_init,
.dt_compat = imx23_dt_compat,
.restart = mxs_restart,
MACHINE_END
DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
.map_io = mx28_map_io,
.init_irq = icoll_init_irq,
.handle_irq = icoll_handle_irq,
.init_time = imx28_timer_init,
.init_machine = mxs_machine_init,
.dt_compat = imx28_dt_compat,
.dt_compat = mxs_dt_compat,
.restart = mxs_restart,
MACHINE_END

52
arch/arm/mach-mxs/mm.c
View File

@ -1,52 +0,0 @@
/*
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*
* Create static mapping between physical to virtual memory.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <asm/mach/map.h>
#include <mach/mx23.h>
#include <mach/mx28.h>
#include <mach/common.h>
/*
* Define the MX23 memory map.
*/
static struct map_desc mx23_io_desc[] __initdata = {
mxs_map_entry(MX23, OCRAM, MT_DEVICE),
mxs_map_entry(MX23, IO, MT_DEVICE),
};
/*
* Define the MX28 memory map.
*/
static struct map_desc mx28_io_desc[] __initdata = {
mxs_map_entry(MX28, OCRAM, MT_DEVICE),
mxs_map_entry(MX28, IO, MT_DEVICE),
};
/*
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory mappings
* for the IO modules.
*/
void __init mx23_map_io(void)
{
iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc));
}
void __init mx28_map_io(void)
{
iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc));
}

93
arch/arm/mach-mxs/ocotp.c
View File

@ -1,93 +0,0 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <asm/processor.h> /* for cpu_relax() */
#include <mach/mxs.h>
#include <mach/common.h>
#define OCOTP_WORD_OFFSET 0x20
#define OCOTP_WORD_COUNT 0x20
#define BM_OCOTP_CTRL_BUSY (1 << 8)
#define BM_OCOTP_CTRL_ERROR (1 << 9)
#define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12)
static DEFINE_MUTEX(ocotp_mutex);
static u32 ocotp_words[OCOTP_WORD_COUNT];
const u32 *mxs_get_ocotp(void)
{
void __iomem *ocotp_base = MXS_IO_ADDRESS(MXS_OCOTP_BASE_ADDR);
int timeout = 0x400;
size_t i;
static int once = 0;
if (once)
return ocotp_words;
mutex_lock(&ocotp_mutex);
/*
* clk_enable(hbus_clk) for ocotp can be skipped
* as it must be on when system is running.
*/
/* try to clear ERROR bit */
__mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base);
/* check both BUSY and ERROR cleared */
while ((__raw_readl(ocotp_base) &
(BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout)
cpu_relax();
if (unlikely(!timeout))
goto error_unlock;
/* open OCOTP banks for read */
__mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
/* approximately wait 32 hclk cycles */
udelay(1);
/* poll BUSY bit becoming cleared */
timeout = 0x400;
while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout)
cpu_relax();
if (unlikely(!timeout))
goto error_unlock;
for (i = 0; i < OCOTP_WORD_COUNT; i++)
ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET +
i * 0x10);
/* close banks for power saving */
__mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
once = 1;
mutex_unlock(&ocotp_mutex);
return ocotp_words;
error_unlock:
mutex_unlock(&ocotp_mutex);
pr_err("%s: timeout in reading OCOTP\n", __func__);
return NULL;
}

139
arch/arm/mach-mxs/system.c
View File

@ -1,139 +0,0 @@
/*
* Copyright (C) 1999 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright 2006-2007,2010 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
* Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/module.h>
#include <asm/proc-fns.h>
#include <asm/system_misc.h>
#include <mach/mxs.h>
#include <mach/common.h>
#define MX23_CLKCTRL_RESET_OFFSET 0x120
#define MX28_CLKCTRL_RESET_OFFSET 0x1e0
#define MXS_CLKCTRL_RESET_CHIP (1 << 1)
#define MXS_MODULE_CLKGATE (1 << 30)
#define MXS_MODULE_SFTRST (1 << 31)
static void __iomem *mxs_clkctrl_reset_addr;
/*
* Reset the system. It is called by machine_restart().
*/
void mxs_restart(char mode, const char *cmd)
{
/* reset the chip */
__mxs_setl(MXS_CLKCTRL_RESET_CHIP, mxs_clkctrl_reset_addr);
pr_err("Failed to assert the chip reset\n");
/* Delay to allow the serial port to show the message */
mdelay(50);
/* We'll take a jump through zero as a poor second */
soft_restart(0);
}
static int __init mxs_arch_reset_init(void)
{
struct clk *clk;
mxs_clkctrl_reset_addr = MXS_IO_ADDRESS(MXS_CLKCTRL_BASE_ADDR) +
(cpu_is_mx23() ? MX23_CLKCTRL_RESET_OFFSET :
MX28_CLKCTRL_RESET_OFFSET);
clk = clk_get_sys("rtc", NULL);
if (!IS_ERR(clk))
clk_prepare_enable(clk);
return 0;
}
core_initcall(mxs_arch_reset_init);
/*
* Clear the bit and poll it cleared. This is usually called with
* a reset address and mask being either SFTRST(bit 31) or CLKGATE
* (bit 30).
*/
static int clear_poll_bit(void __iomem *addr, u32 mask)
{
int timeout = 0x400;
/* clear the bit */
__mxs_clrl(mask, addr);
/*
* SFTRST needs 3 GPMI clocks to settle, the reference manual
* recommends to wait 1us.
*/
udelay(1);
/* poll the bit becoming clear */
while ((__raw_readl(addr) & mask) && --timeout)
/* nothing */;
return !timeout;
}
int mxs_reset_block(void __iomem *reset_addr)
{
int ret;
int timeout = 0x400;
/* clear and poll SFTRST */
ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST);
if (unlikely(ret))
goto error;
/* clear CLKGATE */
__mxs_clrl(MXS_MODULE_CLKGATE, reset_addr);
/* set SFTRST to reset the block */
__mxs_setl(MXS_MODULE_SFTRST, reset_addr);
udelay(1);
/* poll CLKGATE becoming set */
while ((!(__raw_readl(reset_addr) & MXS_MODULE_CLKGATE)) && --timeout)
/* nothing */;
if (unlikely(!timeout))
goto error;
/* clear and poll SFTRST */
ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST);
if (unlikely(ret))
goto error;
/* clear and poll CLKGATE */
ret = clear_poll_bit(reset_addr, MXS_MODULE_CLKGATE);
if (unlikely(ret))
goto error;
return 0;
error:
pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
return -ETIMEDOUT;
}
EXPORT_SYMBOL(mxs_reset_block);

42
drivers/clk/mxs/clk-imx23.c
View File

@ -15,12 +15,15 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <mach/common.h>
#include <mach/mx23.h>
#include <linux/of_address.h>
#include "clk.h"
#define DIGCTRL MX23_IO_ADDRESS(MX23_DIGCTL_BASE_ADDR)
#define CLKCTRL MX23_IO_ADDRESS(MX23_CLKCTRL_BASE_ADDR)
static void __iomem *clkctrl;
static void __iomem *digctrl;
#define CLKCTRL clkctrl
#define DIGCTRL digctrl
#define PLLCTRL0 (CLKCTRL + 0x0000)
#define CPU (CLKCTRL + 0x0020)
#define HBUS (CLKCTRL + 0x0030)
@ -48,10 +51,10 @@ static void __init clk_misc_init(void)
u32 val;
/* Gate off cpu clock in WFI for power saving */
__mxs_setl(1 << BP_CPU_INTERRUPT_WAIT, CPU);
writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
/* Clear BYPASS for SAIF */
__mxs_clrl(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ);
writel_relaxed(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ + CLR);
/* SAIF has to use frac div for functional operation */
val = readl_relaxed(SAIF);
@ -62,14 +65,14 @@ static void __init clk_misc_init(void)
* Source ssp clock from ref_io than ref_xtal,
* as ref_xtal only provides 24 MHz as maximum.
*/
__mxs_clrl(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ);
writel_relaxed(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ + CLR);
/*
* 480 MHz seems too high to be ssp clock source directly,
* so set frac to get a 288 MHz ref_io.
*/
__mxs_clrl(0x3f << BP_FRAC_IOFRAC, FRAC);
__mxs_setl(30 << BP_FRAC_IOFRAC, FRAC);
writel_relaxed(0x3f << BP_FRAC_IOFRAC, FRAC + CLR);
writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET);
}
static const char *sel_pll[] __initconst = { "pll", "ref_xtal", };
@ -101,6 +104,14 @@ int __init mx23_clocks_init(void)
struct device_node *np;
u32 i;
np = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl");
digctrl = of_iomap(np, 0);
WARN_ON(!digctrl);
np = of_find_compatible_node(NULL, NULL, "fsl,imx23-clkctrl");
clkctrl = of_iomap(np, 0);
WARN_ON(!clkctrl);
clk_misc_init();
clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
@ -153,19 +164,12 @@ int __init mx23_clocks_init(void)
return PTR_ERR(clks[i]);
}
np = of_find_compatible_node(NULL, NULL, "fsl,imx23-clkctrl");
if (np) {
clk_data.clks = clks;
clk_data.clk_num = ARRAY_SIZE(clks);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
}
clk_register_clkdev(clks[clk32k], NULL, "timrot");
clk_data.clks = clks;
clk_data.clk_num = ARRAY_SIZE(clks);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
clk_prepare_enable(clks[clks_init_on[i]]);
mxs_timer_init();
return 0;
}

42
drivers/clk/mxs/clk-imx28.c
View File

@ -15,11 +15,12 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <mach/common.h>
#include <mach/mx28.h>
#include <linux/of_address.h>
#include "clk.h"
#define CLKCTRL MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR)
static void __iomem *clkctrl;
#define CLKCTRL clkctrl
#define PLL0CTRL0 (CLKCTRL + 0x0000)
#define PLL1CTRL0 (CLKCTRL + 0x0020)
#define PLL2CTRL0 (CLKCTRL + 0x0040)
@ -53,7 +54,8 @@
#define BP_FRAC0_IO1FRAC 16
#define BP_FRAC0_IO0FRAC 24
#define DIGCTRL MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR)
static void __iomem *digctrl;
#define DIGCTRL digctrl
#define BP_SAIF_CLKMUX 10
/*
@ -72,8 +74,8 @@ int mxs_saif_clkmux_select(unsigned int clkmux)
if (clkmux > 0x3)
return -EINVAL;
__mxs_clrl(0x3 << BP_SAIF_CLKMUX, DIGCTRL);
__mxs_setl(clkmux << BP_SAIF_CLKMUX, DIGCTRL);
writel_relaxed(0x3 << BP_SAIF_CLKMUX, DIGCTRL + CLR);
writel_relaxed(clkmux << BP_SAIF_CLKMUX, DIGCTRL + SET);
return 0;
}
@ -83,13 +85,13 @@ static void __init clk_misc_init(void)
u32 val;
/* Gate off cpu clock in WFI for power saving */
__mxs_setl(1 << BP_CPU_INTERRUPT_WAIT, CPU);
writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
/* 0 is a bad default value for a divider */
__mxs_setl(1 << BP_ENET_DIV_TIME, ENET);
writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET);
/* Clear BYPASS for SAIF */
__mxs_clrl(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ);
writel_relaxed(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ + CLR);
/* SAIF has to use frac div for functional operation */
val = readl_relaxed(SAIF0);
@ -109,7 +111,7 @@ static void __init clk_misc_init(void)
* Source ssp clock from ref_io than ref_xtal,
* as ref_xtal only provides 24 MHz as maximum.
*/
__mxs_clrl(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ);
writel_relaxed(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ + CLR);
/*
* 480 MHz seems too high to be ssp clock source directly,
@ -156,6 +158,14 @@ int __init mx28_clocks_init(void)
struct device_node *np;
u32 i;
np = of_find_compatible_node(NULL, NULL, "fsl,imx28-digctl");
digctrl = of_iomap(np, 0);
WARN_ON(!digctrl);
np = of_find_compatible_node(NULL, NULL, "fsl,imx28-clkctrl");
clkctrl = of_iomap(np, 0);
WARN_ON(!clkctrl);
clk_misc_init();
clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
@ -231,20 +241,14 @@ int __init mx28_clocks_init(void)
return PTR_ERR(clks[i]);
}
np = of_find_compatible_node(NULL, NULL, "fsl,imx28-clkctrl");
if (np) {
clk_data.clks = clks;
clk_data.clk_num = ARRAY_SIZE(clks);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
}
clk_data.clks = clks;
clk_data.clk_num = ARRAY_SIZE(clks);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
clk_register_clkdev(clks[xbus], NULL, "timrot");
clk_register_clkdev(clks[enet_out], NULL, "enet_out");
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
clk_prepare_enable(clks[clks_init_on[i]]);
mxs_timer_init();
return 0;
}

1
drivers/clocksource/Makefile
View File

@ -16,6 +16,7 @@ obj-$(CONFIG_CLKSRC_NOMADIK_MTU) += nomadik-mtu.o
obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o
obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o
obj-$(CONFIG_ARCH_MXS) += mxs_timer.o
obj-$(CONFIG_SUNXI_TIMER) += sunxi_timer.o
obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o
obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o

36
arch/arm/mach-mxs/timer.c → drivers/clocksource/mxs_timer.c
View File

@ -26,12 +26,12 @@
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/stmp_device.h>
#include <asm/mach/time.h>
#include <asm/sched_clock.h>
#include <mach/mxs.h>
#include <mach/common.h>
/*
* There are 2 versions of the timrot on Freescale MXS-based SoCs.
@ -79,25 +79,25 @@
static struct clock_event_device mxs_clockevent_device;
static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED;
static void __iomem *mxs_timrot_base = MXS_IO_ADDRESS(MXS_TIMROT_BASE_ADDR);
static void __iomem *mxs_timrot_base;
static u32 timrot_major_version;
static inline void timrot_irq_disable(void)
{
__mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ_EN,
mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
__raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR);
}
static inline void timrot_irq_enable(void)
{
__mxs_setl(BM_TIMROT_TIMCTRLn_IRQ_EN,
mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
__raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_SET);
}
static void timrot_irq_acknowledge(void)
{
__mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ,
mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
__raw_writel(BM_TIMROT_TIMCTRLn_IRQ, mxs_timrot_base +
HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR);
}
static cycle_t timrotv1_get_cycles(struct clocksource *cs)
@ -242,19 +242,15 @@ static int __init mxs_clocksource_init(struct clk *timer_clk)
return 0;
}
void __init mxs_timer_init(void)
static void __init mxs_timer_init(struct device_node *np)
{
struct device_node *np;
struct clk *timer_clk;
int irq;
np = of_find_compatible_node(NULL, NULL, "fsl,timrot");
if (!np) {
pr_err("%s: failed find timrot node\n", __func__);
return;
}
mxs_timrot_base = of_iomap(np, 0);
WARN_ON(!mxs_timrot_base);
timer_clk = clk_get_sys("timrot", NULL);
timer_clk = of_clk_get(np, 0);
if (IS_ERR(timer_clk)) {
pr_err("%s: failed to get clk\n", __func__);
return;
@ -265,11 +261,12 @@ void __init mxs_timer_init(void)
/*
* Initialize timers to a known state
*/
mxs_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
stmp_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
/* get timrot version */
timrot_major_version = __raw_readl(mxs_timrot_base +
(cpu_is_mx23() ? MX23_TIMROT_VERSION_OFFSET :
(of_device_is_compatible(np, "fsl,imx23-timrot") ?
MX23_TIMROT_VERSION_OFFSET :
MX28_TIMROT_VERSION_OFFSET));
timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;
@ -304,3 +301,4 @@ void __init mxs_timer_init(void)
irq = irq_of_parse_and_map(np, 0);
setup_irq(irq, &mxs_timer_irq);
}
CLOCKSOURCE_OF_DECLARE(mxs, "fsl,timrot", mxs_timer_init);

1
drivers/irqchip/Makefile
View File

@ -2,6 +2,7 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
obj-$(CONFIG_METAG) += irq-metag-ext.o
obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o

24
arch/arm/mach-mxs/icoll.c → drivers/irqchip/irq-mxs.c
View File

@ -22,10 +22,12 @@
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/stmp_device.h>
#include <asm/exception.h>
#include <mach/mxs.h>
#include <mach/common.h>
#include "irqchip.h"
#define HW_ICOLL_VECTOR 0x0000
#define HW_ICOLL_LEVELACK 0x0010
@ -38,7 +40,7 @@
#define ICOLL_NUM_IRQS 128
static void __iomem *icoll_base = MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR);
static void __iomem *icoll_base;
static struct irq_domain *icoll_domain;
static void icoll_ack_irq(struct irq_data *d)
@ -103,23 +105,17 @@ static struct irq_domain_ops icoll_irq_domain_ops = {
static void __init icoll_of_init(struct device_node *np,
struct device_node *interrupt_parent)
{
icoll_base = of_iomap(np, 0);
WARN_ON(!icoll_base);
/*
* Interrupt Collector reset, which initializes the priority
* for each irq to level 0.
*/
mxs_reset_block(icoll_base + HW_ICOLL_CTRL);
stmp_reset_block(icoll_base + HW_ICOLL_CTRL);
icoll_domain = irq_domain_add_linear(np, ICOLL_NUM_IRQS,
&icoll_irq_domain_ops, NULL);
WARN_ON(!icoll_domain);
}
static const struct of_device_id icoll_of_match[] __initconst = {
{.compatible = "fsl,icoll", .data = icoll_of_init},
{ /* sentinel */ }
};
void __init icoll_init_irq(void)
{
of_irq_init(icoll_of_match);
}
IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init);

6
drivers/rtc/rtc-stmp3xxx.c
View File

@ -30,8 +30,6 @@
#include <linux/stmp_device.h>
#include <linux/stmp3xxx_rtc_wdt.h>
#include <mach/common.h>
#define STMP3XXX_RTC_CTRL 0x0
#define STMP3XXX_RTC_CTRL_SET 0x4
#define STMP3XXX_RTC_CTRL_CLR 0x8
@ -271,7 +269,7 @@ static int stmp3xxx_rtc_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, rtc_data);
mxs_reset_block(rtc_data->io);
stmp_reset_block(rtc_data->io);
writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
@ -319,7 +317,7 @@ static int stmp3xxx_rtc_resume(struct platform_device *dev)
{
struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(dev);
mxs_reset_block(rtc_data->io);
stmp_reset_block(rtc_data->io);
writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,

3
drivers/staging/iio/adc/mxs-lradc.c
View File

@ -36,9 +36,6 @@
#include <linux/delay.h>
#include <linux/input.h>
#include <mach/mxs.h>
#include <mach/common.h>
#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger.h>

16
include/linux/clk/mxs.h Normal file
View File

@ -0,0 +1,16 @@
/*
* Copyright (C) 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_CLK_MXS_H
#define __LINUX_CLK_MXS_H
int mx23_clocks_init(void);
int mx28_clocks_init(void);
int mxs_saif_clkmux_select(unsigned int clkmux);
#endif

14
include/linux/irqchip/mxs.h Normal file
View File

@ -0,0 +1,14 @@
/*
* Copyright (C) 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_IRQCHIP_MXS_H
#define __LINUX_IRQCHIP_MXS_H
extern void icoll_handle_irq(struct pt_regs *);
#endif

5
sound/soc/mxs/mxs-saif.c
View File

@ -33,11 +33,12 @@
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <mach/mxs.h>
#include "mxs-saif.h"
#define MXS_SET_ADDR 0x4
#define MXS_CLR_ADDR 0x8
static struct mxs_saif *mxs_saif[2];
/*