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arm64: dts: mt8183: Add display nodes for MT8183

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Add display subsystem device nodes to allow video output.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20201127104930.1981497-4-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Enric Balletbo i Serra 2020-11-27 11:49:30 +01:00 committed by Matthias Brugger
parent c608091631
commit 91f9c963ce
1 changed files with 114 additions and 0 deletions
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114
arch/arm64/boot/dts/mediatek/mt8183.dtsi
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@ -6,6 +6,7 @@
*/ */
#include <dt-bindings/clock/mt8183-clk.h> #include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/gce/mt8173-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/mt8183-larb-port.h> #include <dt-bindings/memory/mt8183-larb-port.h>
@ -33,6 +34,11 @@
i2c9 = &i2c9; i2c9 = &i2c9;
i2c10 = &i2c10; i2c10 = &i2c10;
i2c11 = &i2c11; i2c11 = &i2c11;
ovl0 = &ovl0;
ovl-2l0 = &ovl_2l0;
ovl-2l1 = &ovl_2l1;
rdma0 = &rdma0;
rdma1 = &rdma1;
}; };
cpus { cpus {
@ -964,6 +970,107 @@
#clock-cells = <1>; #clock-cells = <1>;
}; };
ovl0: ovl@14008000 {
compatible = "mediatek,mt8183-disp-ovl";
reg = <0 0x14008000 0 0x1000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_OVL0>;
iommus = <&iommu M4U_PORT_DISP_OVL0>;
mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
};
ovl_2l0: ovl@14009000 {
compatible = "mediatek,mt8183-disp-ovl-2l";
reg = <0 0x14009000 0 0x1000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
};
ovl_2l1: ovl@1400a000 {
compatible = "mediatek,mt8183-disp-ovl-2l";
reg = <0 0x1400a000 0 0x1000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>;
mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
};
rdma0: rdma@1400b000 {
compatible = "mediatek,mt8183-disp-rdma";
reg = <0 0x1400b000 0 0x1000>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
mediatek,larb = <&larb0>;
mediatek,rdma_fifo_size = <5120>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
};
rdma1: rdma@1400c000 {
compatible = "mediatek,mt8183-disp-rdma";
reg = <0 0x1400c000 0 0x1000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
mediatek,larb = <&larb0>;
mediatek,rdma_fifo_size = <2048>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
};
color0: color@1400e000 {
compatible = "mediatek,mt8183-disp-color",
"mediatek,mt8173-disp-color";
reg = <0 0x1400e000 0 0x1000>;
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
};
ccorr0: ccorr@1400f000 {
compatible = "mediatek,mt8183-disp-ccorr";
reg = <0 0x1400f000 0 0x1000>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_CCORR0>;
};
aal0: aal@14010000 {
compatible = "mediatek,mt8183-disp-aal",
"mediatek,mt8173-disp-aal";
reg = <0 0x14010000 0 0x1000>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_AAL0>;
};
gamma0: gamma@14011000 {
compatible = "mediatek,mt8183-disp-gamma",
"mediatek,mt8173-disp-gamma";
reg = <0 0x14011000 0 0x1000>;
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
};
dither0: dither@14012000 {
compatible = "mediatek,mt8183-disp-dither";
reg = <0 0x14012000 0 0x1000>;
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
};
dsi0: dsi@14014000 { dsi0: dsi@14014000 {
compatible = "mediatek,mt8183-dsi"; compatible = "mediatek,mt8183-dsi";
reg = <0 0x14014000 0 0x1000>; reg = <0 0x14014000 0 0x1000>;
@ -978,6 +1085,13 @@
phy-names = "dphy"; phy-names = "dphy";
}; };
mutex: mutex@14016000 {
compatible = "mediatek,mt8183-disp-mutex";
reg = <0 0x14016000 0 0x1000>;
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
};
larb0: larb@14017000 { larb0: larb@14017000 {
compatible = "mediatek,mt8183-smi-larb"; compatible = "mediatek,mt8183-smi-larb";
reg = <0 0x14017000 0 0x1000>; reg = <0 0x14017000 0 0x1000>;