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arm64: dts: marvell: replace cpm by cp0, cps by cp1
In preparation for the introduction of more than 2 CPs in upcoming SoCs, it makes sense to move away from the "CP master" (cpm) and "CP slave" (cps) naming, and use instead cp0/cp1. This commit is the result of: sed 's%cpm%cp0g%' arch/arm64/boot/dts/marvell/* sed 's%cps%cp1g%' arch/arm64/boot/dts/marvell/* So it is a purely mechaninal change. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Suggested-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This commit is contained in:
Thomas Petazzoni
Gregory CLEMENT
parent
72a3713fad
commit
91f1be92eb
@ -61,7 +61,7 @@
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus {
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cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb3h0-vbus";
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regulator-min-microvolt = <5000000>;
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@ -70,7 +70,7 @@
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gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
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};
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cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus {
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cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb3h1-vbus";
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regulator-min-microvolt = <5000000>;
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@ -79,14 +79,14 @@
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gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
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};
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cpm_usb3_0_phy: cpm-usb3-0-phy {
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cp0_usb3_0_phy: cp0-usb3-0-phy {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&cpm_reg_usb3_0_vbus>;
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vcc-supply = <&cp0_reg_usb3_0_vbus>;
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};
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cpm_usb3_1_phy: cpm-usb3-1-phy {
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cp0_usb3_1_phy: cp0-usb3-1-phy {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&cpm_reg_usb3_1_vbus>;
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vcc-supply = <&cp0_reg_usb3_1_vbus>;
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};
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};
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@ -129,11 +129,11 @@
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};
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&cpm_pcie2 {
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&cp0_pcie2 {
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status = "okay";
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};
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&cpm_i2c0 {
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&cp0_i2c0 {
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status = "okay";
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clock-frequency = <100000>;
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@ -156,7 +156,7 @@
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};
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};
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&cpm_nand {
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&cp0_nand {
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/*
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* SPI on CPM and NAND have common pins on this board. We can
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* use only one at a time. To enable the NAND (whihch will
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@ -186,7 +186,7 @@
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};
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&cpm_spi1 {
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&cp0_spi1 {
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status = "okay";
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spi-flash@0 {
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@ -214,17 +214,17 @@
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};
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};
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&cpm_sata0 {
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&cp0_sata0 {
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status = "okay";
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};
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&cpm_usb3_0 {
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usb-phy = <&cpm_usb3_0_phy>;
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&cp0_usb3_0 {
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usb-phy = <&cp0_usb3_0_phy>;
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status = "okay";
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};
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&cpm_usb3_1 {
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usb-phy = <&cpm_usb3_1_phy>;
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&cp0_usb3_1 {
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usb-phy = <&cp0_usb3_1_phy>;
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status = "okay";
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};
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@ -235,14 +235,14 @@
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non-removable;
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};
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&cpm_sdhci0 {
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&cp0_sdhci0 {
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status = "okay";
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bus-width = <4>;
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no-1-8-v;
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cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
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};
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&cpm_mdio {
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&cp0_mdio {
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status = "okay";
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phy0: ethernet-phy@0 {
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@ -253,28 +253,28 @@
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};
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};
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&cpm_ethernet {
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&cp0_ethernet {
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status = "okay";
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};
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&cpm_eth0 {
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&cp0_eth0 {
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status = "okay";
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/* Network PHY */
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phy-mode = "10gbase-kr";
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/* Generic PHY, providing serdes lanes */
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phys = <&cpm_comphy2 0>;
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phys = <&cp0_comphy2 0>;
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};
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&cpm_eth1 {
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&cp0_eth1 {
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status = "okay";
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/* Network PHY */
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phy = <&phy0>;
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phy-mode = "sgmii";
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/* Generic PHY, providing serdes lanes */
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phys = <&cpm_comphy0 1>;
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phys = <&cp0_comphy0 1>;
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};
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&cpm_eth2 {
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&cp0_eth2 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "rgmii-id";
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@ -46,17 +46,17 @@
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/ {
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aliases {
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gpio1 = &cpm_gpio1;
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gpio2 = &cpm_gpio2;
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spi1 = &cpm_spi0;
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spi2 = &cpm_spi1;
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gpio1 = &cp0_gpio1;
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gpio2 = &cp0_gpio2;
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spi1 = &cp0_spi0;
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spi2 = &cp0_spi1;
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};
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};
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/*
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* Instantiate the CP110
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*/
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#define CP110_NAME cpm
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#define CP110_NAME cp0
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#define CP110_BASE f2000000
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#define CP110_PCIE_IO_BASE 0xf9000000
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#define CP110_PCIE_MEM_BASE 0xf6000000
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@ -74,16 +74,16 @@
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#undef CP110_PCIE1_BASE
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#undef CP110_PCIE2_BASE
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&cpm_gpio1 {
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&cp0_gpio1 {
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status = "okay";
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};
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&cpm_gpio2 {
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&cp0_gpio2 {
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status = "okay";
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};
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&cpm_syscon0 {
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cpm_pinctrl: pinctrl {
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&cp0_syscon0 {
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cp0_pinctrl: pinctrl {
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compatible = "marvell,armada-7k-pinctrl";
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nand_pins: nand-pins {
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@ -60,6 +60,6 @@
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* oscillator so this one is let enabled.
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*/
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&cpm_rtc {
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&cp0_rtc {
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status = "disabled";
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};
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@ -61,46 +61,46 @@
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus {
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cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
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compatible = "regulator-fixed";
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regulator-name = "cpm-usb3h0-vbus";
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regulator-name = "cp0-usb3h0-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
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};
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cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus {
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cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
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compatible = "regulator-fixed";
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regulator-name = "cpm-usb3h1-vbus";
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regulator-name = "cp0-usb3h1-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
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};
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cpm_usb3_0_phy: cpm-usb3-0-phy {
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cp0_usb3_0_phy: cp0-usb3-0-phy {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&cpm_reg_usb3_0_vbus>;
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vcc-supply = <&cp0_reg_usb3_0_vbus>;
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};
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cpm_usb3_1_phy: cpm-usb3-1-phy {
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cp0_usb3_1_phy: cp0-usb3-1-phy {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&cpm_reg_usb3_1_vbus>;
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vcc-supply = <&cp0_reg_usb3_1_vbus>;
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};
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cps_reg_usb3_0_vbus: cps-usb3-0-vbus {
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cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
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compatible = "regulator-fixed";
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regulator-name = "cps-usb3h0-vbus";
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regulator-name = "cp1-usb3h0-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
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};
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cps_usb3_0_phy: cps-usb3-0-phy {
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cp1_usb3_0_phy: cp1-usb3-0-phy {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&cps_reg_usb3_0_vbus>;
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vcc-supply = <&cp1_reg_usb3_0_vbus>;
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};
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};
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@ -144,16 +144,16 @@
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};
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/* CON6 on CP0 expansion */
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&cpm_pcie0 {
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&cp0_pcie0 {
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status = "okay";
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};
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/* CON5 on CP0 expansion */
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&cpm_pcie2 {
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&cp0_pcie2 {
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status = "okay";
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};
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&cpm_i2c0 {
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&cp0_i2c0 {
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status = "okay";
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clock-frequency = <100000>;
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@ -178,23 +178,23 @@
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};
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/* CON4 on CP0 expansion */
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&cpm_sata0 {
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&cp0_sata0 {
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status = "okay";
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};
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/* CON9 on CP0 expansion */
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&cpm_usb3_0 {
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usb-phy = <&cpm_usb3_0_phy>;
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&cp0_usb3_0 {
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usb-phy = <&cp0_usb3_0_phy>;
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status = "okay";
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};
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/* CON10 on CP0 expansion */
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&cpm_usb3_1 {
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usb-phy = <&cpm_usb3_1_phy>;
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&cp0_usb3_1 {
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usb-phy = <&cp0_usb3_1_phy>;
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status = "okay";
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};
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&cpm_mdio {
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&cp0_mdio {
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status = "okay";
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phy1: ethernet-phy@1 {
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@ -202,42 +202,42 @@
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};
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};
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&cpm_ethernet {
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&cp0_ethernet {
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status = "okay";
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};
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&cpm_eth0 {
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&cp0_eth0 {
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status = "okay";
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phy-mode = "10gbase-kr";
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};
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&cpm_eth2 {
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&cp0_eth2 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "rgmii-id";
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};
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/* CON6 on CP1 expansion */
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&cps_pcie0 {
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&cp1_pcie0 {
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status = "okay";
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};
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/* CON7 on CP1 expansion */
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&cps_pcie1 {
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&cp1_pcie1 {
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status = "okay";
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};
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/* CON5 on CP1 expansion */
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&cps_pcie2 {
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&cp1_pcie2 {
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status = "okay";
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};
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&cps_i2c0 {
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&cp1_i2c0 {
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status = "okay";
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clock-frequency = <100000>;
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};
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&cps_spi1 {
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&cp1_spi1 {
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status = "okay";
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spi-flash@0 {
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@ -272,14 +272,14 @@
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* Proper NAND usage will require DPR-76 to be in position 1-2, which disables
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* MDIO signal of CP1.
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*/
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&cps_nand {
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&cp1_nand {
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num-cs = <1>;
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pinctrl-0 = <&nand_pins>, <&nand_rb>;
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pinctrl-names = "default";
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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marvell,nand-enable-arbiter;
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marvell,system-controller = <&cps_syscon0>;
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marvell,system-controller = <&cp1_syscon0>;
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nand-on-flash-bbt;
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partition@0 {
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@ -297,22 +297,22 @@
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};
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/* CON4 on CP1 expansion */
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&cps_sata0 {
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&cp1_sata0 {
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status = "okay";
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};
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/* CON9 on CP1 expansion */
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&cps_usb3_0 {
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usb-phy = <&cps_usb3_0_phy>;
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&cp1_usb3_0 {
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usb-phy = <&cp1_usb3_0_phy>;
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status = "okay";
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};
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/* CON10 on CP1 expansion */
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&cps_usb3_1 {
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&cp1_usb3_1 {
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status = "okay";
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};
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&cps_mdio {
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&cp1_mdio {
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status = "okay";
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phy0: ethernet-phy@0 {
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@ -320,16 +320,16 @@
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};
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};
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&cps_ethernet {
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&cp1_ethernet {
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status = "okay";
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};
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&cps_eth0 {
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&cp1_eth0 {
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status = "okay";
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phy-mode = "10gbase-kr";
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};
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&cps_eth1 {
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&cp1_eth1 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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@ -341,7 +341,7 @@
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non-removable;
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};
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&cpm_sdhci0 {
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&cp0_sdhci0 {
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status = "okay";
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bus-width = <8>;
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non-removable;
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@ -84,9 +84,9 @@
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v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&cpm_gpio2 15 GPIO_ACTIVE_HIGH>;
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gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&cpm_xhci_vbus_pins>;
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pinctrl-0 = <&cp0_xhci_vbus_pins>;
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regulator-name = "v_5v0_usb3_hst_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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@ -120,17 +120,17 @@
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vqmmc-supply = <&v_vddo_h>;
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};
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&cpm_i2c0 {
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&cp0_i2c0 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&cpm_i2c0_pins>;
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pinctrl-0 = <&cp0_i2c0_pins>;
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status = "okay";
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};
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&cpm_i2c1 {
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&cp0_i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&cpm_i2c1_pins>;
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pinctrl-0 = <&cp0_i2c1_pins>;
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status = "okay";
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i2c-switch@70 {
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@ -157,9 +157,9 @@
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};
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};
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&cpm_mdio {
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&cp0_mdio {
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pinctrl-names = "default";
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pinctrl-0 = <&cpm_ge_mdio_pins>;
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pinctrl-0 = <&cp0_ge_mdio_pins>;
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status = "okay";
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ge_phy: ethernet-phy@0 {
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@ -167,44 +167,44 @@
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};
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};
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&cpm_pcie0 {
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&cp0_pcie0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cpm_pcie_pins>;
|
||||
pinctrl-0 = <&cp0_pcie_pins>;
|
||||
num-lanes = <4>;
|
||||
num-viewport = <8>;
|
||||
reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>;
|
||||
reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpm_pinctrl {
|
||||
cpm_ge_mdio_pins: ge-mdio-pins {
|
||||
&cp0_pinctrl {
|
||||
cp0_ge_mdio_pins: ge-mdio-pins {
|
||||
marvell,pins = "mpp32", "mpp34";
|
||||
marvell,function = "ge";
|
||||
};
|
||||
cpm_i2c1_pins: i2c1-pins {
|
||||
cp0_i2c1_pins: i2c1-pins {
|
||||
marvell,pins = "mpp35", "mpp36";
|
||||
marvell,function = "i2c1";
|
||||
};
|
||||
cpm_i2c0_pins: i2c0-pins {
|
||||
cp0_i2c0_pins: i2c0-pins {
|
||||
marvell,pins = "mpp37", "mpp38";
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
cpm_xhci_vbus_pins: xhci0-vbus-pins {
|
||||
cp0_xhci_vbus_pins: xhci0-vbus-pins {
|
||||
marvell,pins = "mpp47";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
cpm_pcie_pins: pcie-pins {
|
||||
cp0_pcie_pins: pcie-pins {
|
||||
marvell,pins = "mpp52";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
cpm_sdhci_pins: sdhci-pins {
|
||||
cp0_sdhci_pins: sdhci-pins {
|
||||
marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
|
||||
"mpp60", "mpp61";
|
||||
marvell,function = "sdio";
|
||||
};
|
||||
};
|
||||
|
||||
&cpm_xmdio {
|
||||
&cp0_xmdio {
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
@ -218,83 +218,83 @@
|
||||
};
|
||||
};
|
||||
|
||||
&cpm_ethernet {
|
||||
&cp0_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpm_eth0 {
|
||||
&cp0_eth0 {
|
||||
status = "okay";
|
||||
/* Network PHY */
|
||||
phy = <&phy0>;
|
||||
phy-mode = "10gbase-kr";
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cpm_comphy4 0>;
|
||||
phys = <&cp0_comphy4 0>;
|
||||
};
|
||||
|
||||
&cpm_sata0 {
|
||||
&cp0_sata0 {
|
||||
/* CPM Lane 0 - U29 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpm_sdhci0 {
|
||||
&cp0_sdhci0 {
|
||||
/* U6 */
|
||||
broken-cd;
|
||||
bus-width = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cpm_sdhci_pins>;
|
||||
pinctrl-0 = <&cp0_sdhci_pins>;
|
||||
status = "okay";
|
||||
vqmmc-supply = <&v_3_3>;
|
||||
};
|
||||
|
||||
&cpm_usb3_0 {
|
||||
&cp0_usb3_0 {
|
||||
/* J38? - USB2.0 only */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpm_usb3_1 {
|
||||
&cp0_usb3_1 {
|
||||
/* J38? - USB2.0 only */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cps_ethernet {
|
||||
&cp1_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cps_eth0 {
|
||||
&cp1_eth0 {
|
||||
status = "okay";
|
||||
/* Network PHY */
|
||||
phy = <&phy8>;
|
||||
phy-mode = "10gbase-kr";
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cps_comphy4 0>;
|
||||
phys = <&cp1_comphy4 0>;
|
||||
};
|
||||
|
||||
&cps_eth1 {
|
||||
&cp1_eth1 {
|
||||
/* CPS Lane 0 - J5 (Gigabit RJ45) */
|
||||
status = "okay";
|
||||
/* Network PHY */
|
||||
phy = <&ge_phy>;
|
||||
phy-mode = "sgmii";
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cps_comphy0 1>;
|
||||
phys = <&cp1_comphy0 1>;
|
||||
};
|
||||
|
||||
&cps_pinctrl {
|
||||
cps_spi1_pins: spi1-pins {
|
||||
&cp1_pinctrl {
|
||||
cp1_spi1_pins: spi1-pins {
|
||||
marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
};
|
||||
|
||||
&cps_sata0 {
|
||||
&cp1_sata0 {
|
||||
/* CPS Lane 1 - U32 */
|
||||
/* CPS Lane 3 - U31 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cps_spi1 {
|
||||
&cp1_spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cps_spi1_pins>;
|
||||
pinctrl-0 = <&cp1_spi1_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
@ -304,7 +304,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
&cps_usb3_0 {
|
||||
&cp1_usb3_0 {
|
||||
/* CPS Lane 2 - CON7 */
|
||||
usb-phy = <&usb3h0_phy>;
|
||||
status = "okay";
|
||||
|
||||
@ -59,6 +59,6 @@
|
||||
* disable it. However, the RTC clock in CP slave is connected to the
|
||||
* oscillator so this one is let enabled.
|
||||
*/
|
||||
&cpm_rtc {
|
||||
&cp0_rtc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -46,19 +46,19 @@
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
gpio1 = &cps_gpio1;
|
||||
gpio2 = &cpm_gpio2;
|
||||
spi1 = &cpm_spi0;
|
||||
spi2 = &cpm_spi1;
|
||||
spi3 = &cps_spi0;
|
||||
spi4 = &cps_spi1;
|
||||
gpio1 = &cp1_gpio1;
|
||||
gpio2 = &cp0_gpio2;
|
||||
spi1 = &cp0_spi0;
|
||||
spi2 = &cp0_spi1;
|
||||
spi3 = &cp1_spi0;
|
||||
spi4 = &cp1_spi1;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* Instantiate the master CP110
|
||||
*/
|
||||
#define CP110_NAME cpm
|
||||
#define CP110_NAME cp0
|
||||
#define CP110_BASE f2000000
|
||||
#define CP110_PCIE_IO_BASE 0xf9000000
|
||||
#define CP110_PCIE_MEM_BASE 0xf6000000
|
||||
@ -79,7 +79,7 @@
|
||||
/*
|
||||
* Instantiate the slave CP110
|
||||
*/
|
||||
#define CP110_NAME cps
|
||||
#define CP110_NAME cp1
|
||||
#define CP110_BASE f4000000
|
||||
#define CP110_PCIE_IO_BASE 0xfd000000
|
||||
#define CP110_PCIE_MEM_BASE 0xfa000000
|
||||
@ -98,23 +98,23 @@
|
||||
#undef CP110_PCIE2_BASE
|
||||
|
||||
/* The 80x0 has two CP blocks, but uses only one block from each. */
|
||||
&cps_gpio1 {
|
||||
&cp1_gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpm_gpio2 {
|
||||
&cp0_gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpm_syscon0 {
|
||||
cpm_pinctrl: pinctrl {
|
||||
compatible = "marvell,armada-8k-cpm-pinctrl";
|
||||
&cp0_syscon0 {
|
||||
cp0_pinctrl: pinctrl {
|
||||
compatible = "marvell,armada-8k-cp0-pinctrl";
|
||||
};
|
||||
};
|
||||
|
||||
&cps_syscon0 {
|
||||
cps_pinctrl: pinctrl {
|
||||
compatible = "marvell,armada-8k-cps-pinctrl";
|
||||
&cp1_syscon0 {
|
||||
cp1_pinctrl: pinctrl {
|
||||
compatible = "marvell,armada-8k-cp1-pinctrl";
|
||||
|
||||
nand_pins: nand-pins {
|
||||
marvell,pins =
|
||||
@ -135,7 +135,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
&cps_crypto {
|
||||
&cp1_crypto {
|
||||
/*
|
||||
* The cryptographic engine found on the cp110
|
||||
* master is enabled by default at the SoC
|
||||
|
||||
Loading…
Reference in New Issue
Block a user