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ARM: 7114/1: cache-l2x0: add resume entry for l2 in secure mode
we save the l2x0 registers at the first initialization, and platform codes can get them to restore l2x0 status after wakeup. Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Barry Song
Russell King
parent
8d4e652d1b
commit
91c2ebb90b
@ -67,6 +67,13 @@
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#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
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#define L2X0_CACHE_ID_PART_L210 (1 << 6)
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#define L2X0_CACHE_ID_PART_L310 (3 << 6)
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#define L2X0_CACHE_ID_RTL_MASK 0x3f
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#define L2X0_CACHE_ID_RTL_R0P0 0x0
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#define L2X0_CACHE_ID_RTL_R1P0 0x2
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#define L2X0_CACHE_ID_RTL_R2P0 0x4
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#define L2X0_CACHE_ID_RTL_R3P0 0x5
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#define L2X0_CACHE_ID_RTL_R3P1 0x6
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#define L2X0_CACHE_ID_RTL_R3P2 0x8
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#define L2X0_AUX_CTRL_MASK 0xc0000fff
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#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0
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@ -96,6 +103,24 @@
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#ifndef __ASSEMBLY__
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extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
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extern int l2x0_of_init(__u32 aux_val, __u32 aux_mask);
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struct l2x0_regs {
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unsigned long phy_base;
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unsigned long aux_ctrl;
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/*
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* Whether the following registers need to be saved/restored
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* depends on platform
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*/
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unsigned long tag_latency;
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unsigned long data_latency;
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unsigned long filter_start;
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unsigned long filter_end;
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unsigned long prefetch_ctrl;
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unsigned long pwr_ctrl;
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};
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extern struct l2x0_regs l2x0_saved_regs;
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#endif
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#endif
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@ -34,6 +34,7 @@ struct outer_cache_fns {
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void (*sync)(void);
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#endif
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void (*set_debug)(unsigned long);
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void (*resume)(void);
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};
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#ifdef CONFIG_OUTER_CACHE
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@ -74,6 +75,12 @@ static inline void outer_disable(void)
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outer_cache.disable();
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}
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static inline void outer_resume(void)
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{
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if (outer_cache.resume)
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outer_cache.resume();
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}
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#else
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static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
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@ -20,6 +20,7 @@
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#include <asm/thread_info.h>
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#include <asm/memory.h>
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#include <asm/procinfo.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <linux/kbuild.h>
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/*
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@ -92,6 +93,17 @@ int main(void)
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DEFINE(S_OLD_R0, offsetof(struct pt_regs, ARM_ORIG_r0));
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DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs));
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BLANK();
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#ifdef CONFIG_CACHE_L2X0
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DEFINE(L2X0_R_PHY_BASE, offsetof(struct l2x0_regs, phy_base));
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DEFINE(L2X0_R_AUX_CTRL, offsetof(struct l2x0_regs, aux_ctrl));
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DEFINE(L2X0_R_TAG_LATENCY, offsetof(struct l2x0_regs, tag_latency));
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DEFINE(L2X0_R_DATA_LATENCY, offsetof(struct l2x0_regs, data_latency));
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DEFINE(L2X0_R_FILTER_START, offsetof(struct l2x0_regs, filter_start));
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DEFINE(L2X0_R_FILTER_END, offsetof(struct l2x0_regs, filter_end));
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DEFINE(L2X0_R_PREFETCH_CTRL, offsetof(struct l2x0_regs, prefetch_ctrl));
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DEFINE(L2X0_R_PWR_CTRL, offsetof(struct l2x0_regs, pwr_ctrl));
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BLANK();
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#endif
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#ifdef CONFIG_CPU_HAS_ASID
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DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id));
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BLANK();
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@ -33,6 +33,14 @@ static DEFINE_SPINLOCK(l2x0_lock);
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static uint32_t l2x0_way_mask; /* Bitmask of active ways */
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static uint32_t l2x0_size;
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struct l2x0_regs l2x0_saved_regs;
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struct l2x0_of_data {
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void (*setup)(const struct device_node *, __u32 *, __u32 *);
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void (*save)(void);
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void (*resume)(void);
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};
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static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
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{
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/* wait for cache operation by line or way to complete */
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@ -280,7 +288,7 @@ static void l2x0_disable(void)
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spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void __init l2x0_unlock(__u32 cache_id)
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static void l2x0_unlock(__u32 cache_id)
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{
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int lockregs;
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int i;
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@ -356,6 +364,8 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
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/* l2x0 controller is disabled */
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writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
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l2x0_saved_regs.aux_ctrl = aux;
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l2x0_inv_all();
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/* enable L2X0 */
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@ -445,33 +455,132 @@ static void __init pl310_of_setup(const struct device_node *np,
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}
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}
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static void __init pl310_save(void)
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{
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u32 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
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L2X0_CACHE_ID_RTL_MASK;
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l2x0_saved_regs.tag_latency = readl_relaxed(l2x0_base +
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L2X0_TAG_LATENCY_CTRL);
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l2x0_saved_regs.data_latency = readl_relaxed(l2x0_base +
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L2X0_DATA_LATENCY_CTRL);
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l2x0_saved_regs.filter_end = readl_relaxed(l2x0_base +
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L2X0_ADDR_FILTER_END);
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l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base +
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L2X0_ADDR_FILTER_START);
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if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
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/*
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* From r2p0, there is Prefetch offset/control register
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*/
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l2x0_saved_regs.prefetch_ctrl = readl_relaxed(l2x0_base +
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L2X0_PREFETCH_CTRL);
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/*
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* From r3p0, there is Power control register
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*/
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if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
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l2x0_saved_regs.pwr_ctrl = readl_relaxed(l2x0_base +
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L2X0_POWER_CTRL);
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}
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}
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static void l2x0_resume(void)
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{
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if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
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/* restore aux ctrl and enable l2 */
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l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));
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writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base +
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L2X0_AUX_CTRL);
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l2x0_inv_all();
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writel_relaxed(1, l2x0_base + L2X0_CTRL);
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}
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}
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static void pl310_resume(void)
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{
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u32 l2x0_revision;
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if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
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/* restore pl310 setup */
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writel_relaxed(l2x0_saved_regs.tag_latency,
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l2x0_base + L2X0_TAG_LATENCY_CTRL);
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writel_relaxed(l2x0_saved_regs.data_latency,
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l2x0_base + L2X0_DATA_LATENCY_CTRL);
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writel_relaxed(l2x0_saved_regs.filter_end,
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l2x0_base + L2X0_ADDR_FILTER_END);
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writel_relaxed(l2x0_saved_regs.filter_start,
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l2x0_base + L2X0_ADDR_FILTER_START);
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l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
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L2X0_CACHE_ID_RTL_MASK;
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if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
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writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
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l2x0_base + L2X0_PREFETCH_CTRL);
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if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
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writel_relaxed(l2x0_saved_regs.pwr_ctrl,
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l2x0_base + L2X0_POWER_CTRL);
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}
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}
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l2x0_resume();
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}
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static const struct l2x0_of_data pl310_data = {
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pl310_of_setup,
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pl310_save,
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pl310_resume,
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};
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static const struct l2x0_of_data l2x0_data = {
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l2x0_of_setup,
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NULL,
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l2x0_resume,
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};
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static const struct of_device_id l2x0_ids[] __initconst = {
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{ .compatible = "arm,pl310-cache", .data = pl310_of_setup },
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{ .compatible = "arm,l220-cache", .data = l2x0_of_setup },
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{ .compatible = "arm,l210-cache", .data = l2x0_of_setup },
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{ .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
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{ .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
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{ .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
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{}
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};
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int __init l2x0_of_init(__u32 aux_val, __u32 aux_mask)
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{
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struct device_node *np;
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void (*l2_setup)(const struct device_node *np,
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__u32 *aux_val, __u32 *aux_mask);
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struct l2x0_of_data *data;
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struct resource res;
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np = of_find_matching_node(NULL, l2x0_ids);
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if (!np)
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return -ENODEV;
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l2x0_base = of_iomap(np, 0);
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if (of_address_to_resource(np, 0, &res))
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return -ENODEV;
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l2x0_base = ioremap(res.start, resource_size(&res));
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if (!l2x0_base)
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return -ENOMEM;
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l2x0_saved_regs.phy_base = res.start;
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data = of_match_node(l2x0_ids, np)->data;
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/* L2 configuration can only be changed if the cache is disabled */
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if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
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l2_setup = of_match_node(l2x0_ids, np)->data;
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if (l2_setup)
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l2_setup(np, &aux_val, &aux_mask);
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if (data->setup)
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data->setup(np, &aux_val, &aux_mask);
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}
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if (data->save)
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data->save();
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l2x0_init(l2x0_base, aux_val, aux_mask);
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outer_cache.resume = data->resume;
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return 0;
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}
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#endif
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