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drm/i915/guc: Limit number of scratch registers used for H2G

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We wrongly assumed that GuC is only using last scratch register
for G2H messages, but in fact it is also using register [14] to
report sleep state status. Remove that register from our H2G
send registers pool.

v2: No message from host to GuC uses more than 8 registers and
the GuC FW itself uses an 8-element array to store the H2G message,
so we may reduce our send array to just 8 registers (Daniele)
v3: use explicit define (Daniele)
v4: and explicit comment (Daniele)

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20181019101725.14024-1-michal.wajdeczko@intel.com
This commit is contained in:
Michal Wajdeczko 2018-10-19 10:17:24 +00:00 committed by Chris Wilson
parent d364dc66e2
commit 9128b10249
2 changed files with 7 additions and 2 deletions
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3
drivers/gpu/drm/i915/intel_guc.c
View File

@ -50,7 +50,8 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
unsigned int i; unsigned int i;
guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0)); guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
guc->send_regs.count = SOFT_SCRATCH_COUNT - 1; guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
for (i = 0; i < guc->send_regs.count; i++) { for (i = 0; i < guc->send_regs.count; i++) {
fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,

6
drivers/gpu/drm/i915/intel_guc_fwif.h
View File

@ -601,7 +601,9 @@ struct guc_shared_ctx_data {
* registers, where first register holds data treated as message header, * registers, where first register holds data treated as message header,
* and other registers are used to hold message payload. * and other registers are used to hold message payload.
* *
* For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8 * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8,
* but no H2G command takes more than 8 parameters and the GuC FW
* itself uses an 8-element array to store the H2G message.
* *
* +-----------+---------+---------+---------+ * +-----------+---------+---------+---------+
* | MMIO[0] | MMIO[1] | ... | MMIO[n] | * | MMIO[0] | MMIO[1] | ... | MMIO[n] |
@ -633,6 +635,8 @@ struct guc_shared_ctx_data {
* field. * field.
*/ */
#define GUC_MAX_MMIO_MSG_LEN 8
#define INTEL_GUC_MSG_TYPE_SHIFT 28 #define INTEL_GUC_MSG_TYPE_SHIFT 28
#define INTEL_GUC_MSG_TYPE_MASK (0xF << INTEL_GUC_MSG_TYPE_SHIFT) #define INTEL_GUC_MSG_TYPE_MASK (0xF << INTEL_GUC_MSG_TYPE_SHIFT)
#define INTEL_GUC_MSG_DATA_SHIFT 16 #define INTEL_GUC_MSG_DATA_SHIFT 16