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MIPS: dts: pic32: Update dts to reflect new PIC32MZDA clk binding
- now clock nodes definition is merged with core .dtsi file - only one rootclk is now part of DT - clock clients also updated based on new binding doc Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Sandeep Sheriker <sandeepsheriker.mallikarjun@microchip.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13248/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Purna Chandra Mandal
Ralf Baechle
parent
ce6e118846
commit
9125f19bbb
@ -1,236 +0,0 @@
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/*
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* Device Tree Source for PIC32MZDA clock data
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*
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* Purna Chandra Mandal <purna.mandal@microchip.com>
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* Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
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*
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* Licensed under GPLv2 or later.
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*/
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/* all fixed rate clocks */
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/ {
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POSC:posc_clk { /* On-chip primary oscillator */
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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FRC:frc_clk { /* internal FRC oscillator */
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <8000000>;
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};
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BFRC:bfrc_clk { /* internal backup FRC oscillator */
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <8000000>;
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};
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LPRC:lprc_clk { /* internal low-power FRC oscillator */
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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};
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/* UPLL provides clock to USBCORE */
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UPLL:usb_phy_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "usbphy_clk";
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};
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TxCKI:txcki_clk { /* external clock input on TxCLKI pin */
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <4000000>;
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status = "disabled";
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};
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/* external clock input on REFCLKIx pin */
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REFIx:refix_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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status = "disabled";
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};
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/* PIC32 specific clks */
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pic32_clktree {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x1f801200 0x200>;
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compatible = "microchip,pic32mzda-clk";
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ranges = <0 0x1f801200 0x200>;
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/* secondary oscillator; external input on SOSCI pin */
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SOSC:sosc_clk@0 {
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#clock-cells = <0>;
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compatible = "microchip,pic32mzda-sosc";
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clock-frequency = <32768>;
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reg = <0x000 0x10>, /* enable reg */
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<0x1d0 0x10>; /* status reg */
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microchip,bit-mask = <0x02>; /* enable mask */
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microchip,status-bit-mask = <0x10>; /* status-mask*/
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};
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FRCDIV:frcdiv_clk {
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#clock-cells = <0>;
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compatible = "microchip,pic32mzda-frcdivclk";
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clocks = <&FRC>;
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clock-output-names = "frcdiv_clk";
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};
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/* System PLL clock */
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SYSPLL:spll_clk@020 {
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#clock-cells = <0>;
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compatible = "microchip,pic32mzda-syspll";
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reg = <0x020 0x10>, /* SPLL register */
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<0x1d0 0x10>; /* CLKSTAT register */
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clocks = <&POSC>, <&FRC>;
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clock-output-names = "sys_pll";
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microchip,status-bit-mask = <0x80>; /* SPLLRDY */
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};
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/* system clock; mux with postdiv & slew */
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SYSCLK:sys_clk@1c0 {
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#clock-cells = <0>;
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compatible = "microchip,pic32mzda-sysclk-v2";
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reg = <0x1c0 0x04>; /* SLEWCON */
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clocks = <&FRCDIV>, <&SYSPLL>, <&POSC>, <&SOSC>,
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<&LPRC>, <&FRCDIV>;
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microchip,clock-indices = <0>, <1>, <2>, <4>,
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<5>, <7>;
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clock-output-names = "sys_clk";
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};
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/* Peripheral bus1 clock */
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PBCLK1:pb1_clk@140 {
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reg = <0x140 0x10>;
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#clock-cells = <0>;
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compatible = "microchip,pic32mzda-pbclk";
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clocks = <&SYSCLK>;
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clock-output-names = "pb1_clk";
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/* used by system modules, not gateable */
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microchip,ignore-unused;
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};
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/* Peripheral bus2 clock */
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PBCLK2:pb2_clk@150 {
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reg = <0x150 0x10>;
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#clock-cells = <0>;
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compatible = "microchip,pic32mzda-pbclk";
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clocks = <&SYSCLK>;
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clock-output-names = "pb2_clk";
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/* avoid gating even if unused */
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microchip,ignore-unused;
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};
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/* Peripheral bus3 clock */
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PBCLK3:pb3_clk@160 {
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reg = <0x160 0x10>;
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#clock-cells = <0>;
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compatible = "microchip,pic32mzda-pbclk";
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clocks = <&SYSCLK>;
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clock-output-names = "pb3_clk";
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};
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/* Peripheral bus4 clock(I/O ports, GPIO) */
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PBCLK4:pb4_clk@170 {
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reg = <0x170 0x10>;
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#clock-cells = <0>;
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compatible = "microchip,pic32mzda-pbclk";
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clocks = <&SYSCLK>;
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clock-output-names = "pb4_clk";
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};
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/* Peripheral bus clock */
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PBCLK5:pb5_clk@180 {
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reg = <0x180 0x10>;
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#clock-cells = <0>;
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compatible = "microchip,pic32mzda-pbclk";
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clocks = <&SYSCLK>;
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clock-output-names = "pb5_clk";
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};
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/* Peripheral Bus6 clock; */
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PBCLK6:pb6_clk@190 {
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reg = <0x190 0x10>;
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compatible = "microchip,pic32mzda-pbclk";
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clocks = <&SYSCLK>;
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#clock-cells = <0>;
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};
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/* Peripheral bus7 clock */
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PBCLK7:pb7_clk@1a0 {
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reg = <0x1a0 0x10>;
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#clock-cells = <0>;
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compatible = "microchip,pic32mzda-pbclk";
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/* CPU is driven by this clock; so named */
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clock-output-names = "cpu_clk";
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clocks = <&SYSCLK>;
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};
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/* Reference Oscillator clock for SPI/I2S */
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REFCLKO1:refo1_clk@80 {
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reg = <0x080 0x20>;
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#clock-cells = <0>;
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compatible = "microchip,pic32mzda-refoclk";
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clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
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<&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
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microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
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<5>, <7>, <8>, <9>;
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clock-output-names = "refo1_clk";
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};
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/* Reference Oscillator clock for SQI */
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REFCLKO2:refo2_clk@a0 {
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reg = <0x0a0 0x20>;
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#clock-cells = <0>;
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compatible = "microchip,pic32mzda-refoclk";
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clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
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<&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
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microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
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<5>, <7>, <8>, <9>;
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clock-output-names = "refo2_clk";
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};
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/* Reference Oscillator clock, ADC */
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REFCLKO3:refo3_clk@c0 {
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reg = <0x0c0 0x20>;
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compatible = "microchip,pic32mzda-refoclk";
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clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
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<&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
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microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
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<5>, <7>, <8>, <9>;
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#clock-cells = <0>;
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clock-output-names = "refo3_clk";
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};
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/* Reference Oscillator clock */
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REFCLKO4:refo4_clk@e0 {
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reg = <0x0e0 0x20>;
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compatible = "microchip,pic32mzda-refoclk";
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clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
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<&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
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microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
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<5>, <7>, <8>, <9>;
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#clock-cells = <0>;
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clock-output-names = "refo4_clk";
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};
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/* Reference Oscillator clock, LCD */
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REFCLKO5:refo5_clk@100 {
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reg = <0x100 0x20>;
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compatible = "microchip,pic32mzda-refoclk";
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clocks = <&SYSCLK>,<&PBCLK1>,<&POSC>,<&FRC>,<&LPRC>,
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<&SOSC>,<&SYSPLL>,<&REFIx>,<&BFRC>;
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microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
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<5>, <7>, <8>, <9>;
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#clock-cells = <0>;
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clock-output-names = "refo5_clk";
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};
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};
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};
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@ -6,11 +6,9 @@
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* published by the Free Software Foundation.
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*
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*/
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#include <dt-bindings/clock/microchip,pic32-clock.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "pic32mzda-clk.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -50,6 +48,29 @@
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interrupts = <0 IRQ_TYPE_EDGE_RISING>;
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};
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/* external clock input on TxCLKI pin */
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txcki: txcki_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <4000000>;
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status = "disabled";
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};
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/* external input on REFCLKIx pin */
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refix: refix_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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status = "disabled";
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};
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rootclk: clock-controller@1f801200 {
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compatible = "microchip,pic32mzda-clk";
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reg = <0x1f801200 0x200>;
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#clock-cells = <1>;
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microchip,pic32mzda-sosc;
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};
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evic: interrupt-controller@1f810000 {
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compatible = "microchip,pic32mzda-evic";
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interrupt-controller;
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@ -63,7 +84,7 @@
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#size-cells = <1>;
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compatible = "microchip,pic32mzda-pinctrl";
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reg = <0x1f801400 0x400>;
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clocks = <&PBCLK1>;
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clocks = <&rootclk PB1CLK>;
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};
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/* PORTA */
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@ -75,7 +96,7 @@
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&PBCLK4>;
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clocks = <&rootclk PB4CLK>;
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microchip,gpio-bank = <0>;
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gpio-ranges = <&pic32_pinctrl 0 0 16>;
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};
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@ -89,7 +110,7 @@
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&PBCLK4>;
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clocks = <&rootclk PB4CLK>;
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microchip,gpio-bank = <1>;
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gpio-ranges = <&pic32_pinctrl 0 16 16>;
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};
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@ -103,7 +124,7 @@
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&PBCLK4>;
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clocks = <&rootclk PB4CLK>;
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microchip,gpio-bank = <2>;
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gpio-ranges = <&pic32_pinctrl 0 32 16>;
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};
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@ -117,7 +138,7 @@
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&PBCLK4>;
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clocks = <&rootclk PB4CLK>;
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microchip,gpio-bank = <3>;
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gpio-ranges = <&pic32_pinctrl 0 48 16>;
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};
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@ -131,7 +152,7 @@
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&PBCLK4>;
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clocks = <&rootclk PB4CLK>;
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microchip,gpio-bank = <4>;
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gpio-ranges = <&pic32_pinctrl 0 64 16>;
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};
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@ -145,7 +166,7 @@
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&PBCLK4>;
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clocks = <&rootclk PB4CLK>;
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microchip,gpio-bank = <5>;
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gpio-ranges = <&pic32_pinctrl 0 80 16>;
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};
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@ -159,7 +180,7 @@
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&PBCLK4>;
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clocks = <&rootclk PB4CLK>;
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microchip,gpio-bank = <6>;
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gpio-ranges = <&pic32_pinctrl 0 96 16>;
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};
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@ -173,7 +194,7 @@
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&PBCLK4>;
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clocks = <&rootclk PB4CLK>;
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microchip,gpio-bank = <7>;
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gpio-ranges = <&pic32_pinctrl 0 112 16>;
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};
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@ -189,7 +210,7 @@
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&PBCLK4>;
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clocks = <&rootclk PB4CLK>;
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microchip,gpio-bank = <8>;
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gpio-ranges = <&pic32_pinctrl 0 128 16>;
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};
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@ -203,7 +224,7 @@
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&PBCLK4>;
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clocks = <&rootclk PB4CLK>;
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microchip,gpio-bank = <9>;
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gpio-ranges = <&pic32_pinctrl 0 144 16>;
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};
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@ -212,7 +233,7 @@
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compatible = "microchip,pic32mzda-sdhci";
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reg = <0x1f8ec000 0x100>;
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interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&REFCLKO4>, <&PBCLK5>;
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clocks = <&rootclk REF4CLK>, <&rootclk PB5CLK>;
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clock-names = "base_clk", "sys_clk";
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bus-width = <4>;
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cap-sd-highspeed;
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@ -225,7 +246,7 @@
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interrupts = <112 IRQ_TYPE_LEVEL_HIGH>,
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<113 IRQ_TYPE_LEVEL_HIGH>,
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<114 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&PBCLK2>;
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clocks = <&rootclk PB2CLK>;
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status = "disabled";
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};
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@ -235,7 +256,7 @@
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interrupts = <145 IRQ_TYPE_LEVEL_HIGH>,
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<146 IRQ_TYPE_LEVEL_HIGH>,
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<147 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&PBCLK2>;
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clocks = <&rootclk PB2CLK>;
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status = "disabled";
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};
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@ -245,7 +266,7 @@
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interrupts = <157 IRQ_TYPE_LEVEL_HIGH>,
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<158 IRQ_TYPE_LEVEL_HIGH>,
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<159 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&PBCLK2>;
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clocks = <&rootclk PB2CLK>;
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status = "disabled";
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};
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@ -255,7 +276,7 @@
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interrupts = <170 IRQ_TYPE_LEVEL_HIGH>,
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<171 IRQ_TYPE_LEVEL_HIGH>,
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<172 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&PBCLK2>;
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clocks = <&rootclk PB2CLK>;
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status = "disabled";
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};
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@ -265,7 +286,7 @@
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interrupts = <179 IRQ_TYPE_LEVEL_HIGH>,
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<180 IRQ_TYPE_LEVEL_HIGH>,
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<181 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&PBCLK2>;
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clocks = <&rootclk PB2CLK>;
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status = "disabled";
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};
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@ -275,7 +296,7 @@
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interrupts = <188 IRQ_TYPE_LEVEL_HIGH>,
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<189 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&PBCLK2>;
|
||||
clocks = <&rootclk PB2CLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
@ -95,7 +95,8 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhc1>;
|
||||
status = "okay";
|
||||
assigned-clocks = <&REFCLKO2>,<&REFCLKO4>,<&REFCLKO5>;
|
||||
assigned-clocks = <&rootclk REF2CLK>, <&rootclk REF4CLK>,
|
||||
<&rootclk REF5CLK>;
|
||||
assigned-clock-rates = <50000000>, <25000000>, <40000000>;
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user