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iommu/amd: Add support for IOMMU XT mode
The AMD IOMMU XT mode enables interrupt remapping with 32-bit destination APIC ID, which is required for x2APIC. The feature is available when the XTSup bit is set in the IOMMU Extended Feature register and/or the IVHD Type 10h IOMMU Feature Reporting field. For more information, please see section "IOMMU x2APIC Support" of the AMD I/O Virtualization Technology (IOMMU) Specification. Cc: Joerg Roedel <jroedel@suse.de> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Suravee Suthikulpanit
Joerg Roedel
parent
e881dbd5d4
commit
90fcffd9cf
@ -3876,7 +3876,8 @@ static void irte_ga_prepare(void *entry,
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irte->lo.fields_remap.int_type = delivery_mode;
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irte->lo.fields_remap.dm = dest_mode;
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irte->hi.fields.vector = vector;
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irte->lo.fields_remap.destination = dest_apicid;
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irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
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irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
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irte->lo.fields_remap.valid = 1;
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}
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@ -3929,7 +3930,10 @@ static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
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if (!irte->lo.fields_remap.guest_mode) {
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irte->hi.fields.vector = vector;
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irte->lo.fields_remap.destination = dest_apicid;
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irte->lo.fields_remap.destination =
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APICID_TO_IRTE_DEST_LO(dest_apicid);
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irte->hi.fields.destination =
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APICID_TO_IRTE_DEST_HI(dest_apicid);
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modify_irte_ga(devid, index, irte, NULL);
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}
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}
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@ -4346,7 +4350,10 @@ static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
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irte->lo.val = 0;
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irte->hi.fields.vector = cfg->vector;
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irte->lo.fields_remap.guest_mode = 0;
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irte->lo.fields_remap.destination = cfg->dest_apicid;
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irte->lo.fields_remap.destination =
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APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
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irte->hi.fields.destination =
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APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
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irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
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irte->lo.fields_remap.dm = apic->irq_dest_mode;
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@ -4463,8 +4470,12 @@ int amd_iommu_update_ga(int cpu, bool is_run, void *data)
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raw_spin_lock_irqsave(&table->lock, flags);
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if (ref->lo.fields_vapic.guest_mode) {
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if (cpu >= 0)
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ref->lo.fields_vapic.destination = cpu;
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if (cpu >= 0) {
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ref->lo.fields_vapic.destination =
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APICID_TO_IRTE_DEST_LO(cpu);
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ref->hi.fields.destination =
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APICID_TO_IRTE_DEST_HI(cpu);
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}
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ref->lo.fields_vapic.is_run = is_run;
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barrier();
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}
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@ -153,6 +153,7 @@ bool amd_iommu_dump;
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bool amd_iommu_irq_remap __read_mostly;
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int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
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static int amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE;
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static bool amd_iommu_detected;
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static bool __initdata amd_iommu_disabled;
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@ -827,6 +828,19 @@ static int iommu_init_ga(struct amd_iommu *iommu)
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return ret;
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}
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static void iommu_enable_xt(struct amd_iommu *iommu)
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{
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#ifdef CONFIG_IRQ_REMAP
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/*
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* XT mode (32-bit APIC destination ID) requires
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* GA mode (128-bit IRTE support) as a prerequisite.
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*/
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if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir) &&
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amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE)
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iommu_feature_enable(iommu, CONTROL_XT_EN);
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#endif /* CONFIG_IRQ_REMAP */
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}
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static void iommu_enable_gt(struct amd_iommu *iommu)
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{
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if (!iommu_feature(iommu, FEATURE_GT))
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@ -1507,6 +1521,8 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
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iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
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if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
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amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
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if (((h->efr_attr & (0x1 << IOMMU_FEAT_XTSUP_SHIFT)) == 0))
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amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE;
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break;
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case 0x11:
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case 0x40:
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@ -1516,6 +1532,8 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
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iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
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if (((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0))
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amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
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if (((h->efr_reg & (0x1 << IOMMU_EFR_XTSUP_SHIFT)) == 0))
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amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE;
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break;
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default:
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return -EINVAL;
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@ -1832,6 +1850,8 @@ static void print_iommu_info(void)
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pr_info("AMD-Vi: Interrupt remapping enabled\n");
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if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
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pr_info("AMD-Vi: virtual APIC enabled\n");
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if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE)
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pr_info("AMD-Vi: X2APIC enabled\n");
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}
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}
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@ -2168,6 +2188,7 @@ static void early_enable_iommu(struct amd_iommu *iommu)
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iommu_enable_event_buffer(iommu);
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iommu_set_exclusion_range(iommu);
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iommu_enable_ga(iommu);
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iommu_enable_xt(iommu);
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iommu_enable(iommu);
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iommu_flush_all_caches(iommu);
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}
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@ -2212,6 +2233,7 @@ static void early_enable_iommus(void)
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iommu_enable_command_buffer(iommu);
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iommu_enable_event_buffer(iommu);
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iommu_enable_ga(iommu);
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iommu_enable_xt(iommu);
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iommu_set_device_table(iommu);
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iommu_flush_all_caches(iommu);
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}
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@ -2691,8 +2713,7 @@ int __init amd_iommu_enable(void)
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return ret;
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irq_remapping_enabled = 1;
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return 0;
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return amd_iommu_xt_mode;
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}
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void amd_iommu_disable(void)
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@ -161,6 +161,7 @@
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#define CONTROL_GAM_EN 0x19ULL
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#define CONTROL_GALOG_EN 0x1CULL
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#define CONTROL_GAINT_EN 0x1DULL
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#define CONTROL_XT_EN 0x32ULL
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#define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT)
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#define CTRL_INV_TO_NONE 0
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@ -378,9 +379,11 @@
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#define IOMMU_CAP_EFR 27
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/* IOMMU Feature Reporting Field (for IVHD type 10h */
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#define IOMMU_FEAT_XTSUP_SHIFT 0
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#define IOMMU_FEAT_GASUP_SHIFT 6
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/* IOMMU Extended Feature Register (EFR) */
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#define IOMMU_EFR_XTSUP_SHIFT 2
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#define IOMMU_EFR_GASUP_SHIFT 7
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#define MAX_DOMAIN_ID 65536
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@ -437,7 +440,6 @@ extern struct kmem_cache *amd_iommu_irq_cache;
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#define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
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#define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL)
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/*
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* This struct is used to pass information about
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* incoming PPR faults around.
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@ -810,6 +812,9 @@ union irte {
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} fields;
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};
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#define APICID_TO_IRTE_DEST_LO(x) (x & 0xffffff)
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#define APICID_TO_IRTE_DEST_HI(x) ((x >> 24) & 0xff)
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union irte_ga_lo {
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u64 val;
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@ -823,8 +828,8 @@ union irte_ga_lo {
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dm : 1,
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/* ------ */
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guest_mode : 1,
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destination : 8,
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rsvd : 48;
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destination : 24,
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ga_tag : 32;
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} fields_remap;
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/* For guest vAPIC */
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@ -837,8 +842,7 @@ union irte_ga_lo {
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is_run : 1,
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/* ------ */
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guest_mode : 1,
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destination : 8,
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rsvd2 : 16,
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destination : 24,
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ga_tag : 32;
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} fields_vapic;
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};
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@ -849,7 +853,8 @@ union irte_ga_hi {
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u64 vector : 8,
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rsvd_1 : 4,
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ga_root_ptr : 40,
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rsvd_2 : 12;
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rsvd_2 : 4,
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destination : 8;
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} fields;
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};
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