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drm/nouveau/gr/gp10b: Use gp100_grctx and gp100_gr_zbc
gp10b doesn't have all the registers that gp102_gr_zbc wants to access, which causes IBUS MMIO faults to occur. Avoid this by using the gp100 variants of grctx and gr_zbc. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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@ -238,6 +238,7 @@ void gp100_gr_init_fecs_exceptions(struct gf100_gr *);
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void gp100_gr_init_shader_exceptions(struct gf100_gr *, int, int);
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void gp100_gr_zbc_clear_color(struct gf100_gr *, int);
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void gp100_gr_zbc_clear_depth(struct gf100_gr *, int);
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extern const struct gf100_gr_func_zbc gp100_gr_zbc;
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void gp102_gr_init_swdx_pes_mask(struct gf100_gr *);
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extern const struct gf100_gr_func_zbc gp102_gr_zbc;
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@ -62,7 +62,7 @@ gp100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc)
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gr->zbc_depth[zbc].format << ((znum % 4) * 7));
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}
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static const struct gf100_gr_func_zbc
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const struct gf100_gr_func_zbc
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gp100_gr_zbc = {
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.clear_color = gp100_gr_zbc_clear_color,
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.clear_depth = gp100_gr_zbc_clear_depth,
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@ -60,8 +60,8 @@ gp10b_gr = {
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.gpc_nr = 1,
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.tpc_nr = 2,
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.ppc_nr = 1,
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.grctx = &gp102_grctx,
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.zbc = &gp102_gr_zbc,
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.grctx = &gp100_grctx,
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.zbc = &gp100_gr_zbc,
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.sclass = {
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{ -1, -1, FERMI_TWOD_A },
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{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
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