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clk: rockchip: add clock type for pll clocks and pll used on rk3066
All known Rockchip SoCs down to the RK28xx (ARM9) use a similar pattern to
handle their plls:
|--\
xin32k ----------------|mux\
xin24m -----| pll |----|pll|--- pll output
\---------------|src/
|--/
The pll output is sourced from 1 of 3 sources, the actual pll being one of
them. To change the pll frequency it is imperative to remux it to another
source beforehand. This is done by adding a clock-listener to the pll that
handles the remuxing before and after the rate change.
The output mux is implemented as a separate clock to make use of already
existing common-clock features for disabling the pll if one of the other
two sources is used.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Heiko Stübner
Mike Turquette
parent
a245fecbb8
commit
90c5902540
@ -4,3 +4,4 @@
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obj-y += clk-rockchip.o
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obj-y += clk.o
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obj-y += clk-pll.o
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431
drivers/clk/rockchip/clk-pll.c
Normal file
431
drivers/clk/rockchip/clk-pll.c
Normal file
@ -0,0 +1,431 @@
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/*
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* Copyright (c) 2014 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <asm/div64.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include "clk.h"
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#define PLL_MODE_MASK 0x3
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#define PLL_MODE_SLOW 0x0
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#define PLL_MODE_NORM 0x1
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#define PLL_MODE_DEEP 0x2
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struct rockchip_clk_pll {
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struct clk_hw hw;
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struct clk_mux pll_mux;
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const struct clk_ops *pll_mux_ops;
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struct notifier_block clk_nb;
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bool rate_change_remuxed;
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void __iomem *reg_base;
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int lock_offset;
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unsigned int lock_shift;
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enum rockchip_pll_type type;
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const struct rockchip_pll_rate_table *rate_table;
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unsigned int rate_count;
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spinlock_t *lock;
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};
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#define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw)
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#define to_rockchip_clk_pll_nb(nb) \
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container_of(nb, struct rockchip_clk_pll, clk_nb)
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static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
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struct rockchip_clk_pll *pll, unsigned long rate)
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{
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const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
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int i;
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for (i = 0; i < pll->rate_count; i++) {
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if (rate == rate_table[i].rate)
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return &rate_table[i];
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}
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return NULL;
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}
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static long rockchip_pll_round_rate(struct clk_hw *hw,
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unsigned long drate, unsigned long *prate)
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{
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struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
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const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
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int i;
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/* Assumming rate_table is in descending order */
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for (i = 0; i < pll->rate_count; i++) {
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if (drate >= rate_table[i].rate)
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return rate_table[i].rate;
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}
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/* return minimum supported value */
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return rate_table[i - 1].rate;
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}
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/*
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* Wait for the pll to reach the locked state.
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* The calling set_rate function is responsible for making sure the
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* grf regmap is available.
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*/
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static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
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{
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struct regmap *grf = rockchip_clk_get_grf();
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unsigned int val;
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int delay = 24000000, ret;
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while (delay > 0) {
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ret = regmap_read(grf, pll->lock_offset, &val);
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if (ret) {
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pr_err("%s: failed to read pll lock status: %d\n",
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__func__, ret);
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return ret;
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}
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if (val & BIT(pll->lock_shift))
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return 0;
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delay--;
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}
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pr_err("%s: timeout waiting for pll to lock\n", __func__);
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return -ETIMEDOUT;
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}
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/**
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* Set pll mux when changing the pll rate.
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* This makes sure to move the pll mux away from the actual pll before
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* changing its rate and back to the original parent after the change.
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*/
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static int rockchip_pll_notifier_cb(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct rockchip_clk_pll *pll = to_rockchip_clk_pll_nb(nb);
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struct clk_mux *pll_mux = &pll->pll_mux;
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const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
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int cur_parent;
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switch (event) {
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case PRE_RATE_CHANGE:
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cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
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if (cur_parent == PLL_MODE_NORM) {
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pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
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pll->rate_change_remuxed = 1;
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}
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break;
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case POST_RATE_CHANGE:
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if (pll->rate_change_remuxed) {
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pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
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pll->rate_change_remuxed = 0;
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}
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break;
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}
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return NOTIFY_OK;
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}
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/**
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* PLL used in RK3066, RK3188 and RK3288
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*/
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#define RK3066_PLL_RESET_DELAY(nr) ((nr * 500) / 24 + 1)
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#define RK3066_PLLCON(i) (i * 0x4)
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#define RK3066_PLLCON0_OD_MASK 0xf
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#define RK3066_PLLCON0_OD_SHIFT 0
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#define RK3066_PLLCON0_NR_MASK 0x3f
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#define RK3066_PLLCON0_NR_SHIFT 8
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#define RK3066_PLLCON1_NF_MASK 0x1fff
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#define RK3066_PLLCON1_NF_SHIFT 0
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#define RK3066_PLLCON2_BWADJ_MASK 0xfff
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#define RK3066_PLLCON2_BWADJ_SHIFT 0
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#define RK3066_PLLCON3_RESET (1 << 5)
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#define RK3066_PLLCON3_PWRDOWN (1 << 1)
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#define RK3066_PLLCON3_BYPASS (1 << 0)
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static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw,
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unsigned long prate)
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{
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struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
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u64 nf, nr, no, rate64 = prate;
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u32 pllcon;
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pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));
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if (pllcon & RK3066_PLLCON3_BYPASS) {
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pr_debug("%s: pll %s is bypassed\n", __func__,
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__clk_get_name(hw->clk));
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return prate;
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}
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pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
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nf = (pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK;
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pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
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nr = (pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK;
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no = (pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK;
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rate64 *= (nf + 1);
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do_div(rate64, nr + 1);
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do_div(rate64, no + 1);
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return (unsigned long)rate64;
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}
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static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,
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unsigned long prate)
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{
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struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
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const struct rockchip_pll_rate_table *rate;
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unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate);
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struct regmap *grf = rockchip_clk_get_grf();
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int ret;
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if (IS_ERR(grf)) {
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pr_debug("%s: grf regmap not available, aborting rate change\n",
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__func__);
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return PTR_ERR(grf);
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}
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pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
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__func__, __clk_get_name(hw->clk), old_rate, drate, prate);
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/* Get required rate settings from table */
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rate = rockchip_get_pll_settings(pll, drate);
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if (!rate) {
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pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
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drate, __clk_get_name(hw->clk));
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return -EINVAL;
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}
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pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n",
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__func__, rate->rate, rate->nr, rate->no, rate->nf);
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/* enter reset mode */
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writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0),
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pll->reg_base + RK3066_PLLCON(3));
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/* update pll values */
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writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK,
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RK3066_PLLCON0_NR_SHIFT) |
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HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK,
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RK3066_PLLCON0_OD_SHIFT),
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pll->reg_base + RK3066_PLLCON(0));
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writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK,
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RK3066_PLLCON1_NF_SHIFT),
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pll->reg_base + RK3066_PLLCON(1));
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writel_relaxed(HIWORD_UPDATE(rate->bwadj, RK3066_PLLCON2_BWADJ_MASK,
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RK3066_PLLCON2_BWADJ_SHIFT),
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pll->reg_base + RK3066_PLLCON(2));
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/* leave reset and wait the reset_delay */
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writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0),
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pll->reg_base + RK3066_PLLCON(3));
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udelay(RK3066_PLL_RESET_DELAY(rate->nr));
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/* wait for the pll to lock */
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ret = rockchip_pll_wait_lock(pll);
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if (ret) {
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pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
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__func__, old_rate);
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rockchip_rk3066_pll_set_rate(hw, old_rate, prate);
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}
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return ret;
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}
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static int rockchip_rk3066_pll_enable(struct clk_hw *hw)
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{
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struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
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writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0),
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pll->reg_base + RK3066_PLLCON(3));
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return 0;
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}
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static void rockchip_rk3066_pll_disable(struct clk_hw *hw)
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{
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struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
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writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN,
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RK3066_PLLCON3_PWRDOWN, 0),
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pll->reg_base + RK3066_PLLCON(3));
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}
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static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw)
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{
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struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
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u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));
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return !(pllcon & RK3066_PLLCON3_PWRDOWN);
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}
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static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = {
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.recalc_rate = rockchip_rk3066_pll_recalc_rate,
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.enable = rockchip_rk3066_pll_enable,
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.disable = rockchip_rk3066_pll_disable,
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.is_enabled = rockchip_rk3066_pll_is_enabled,
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};
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static const struct clk_ops rockchip_rk3066_pll_clk_ops = {
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.recalc_rate = rockchip_rk3066_pll_recalc_rate,
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.round_rate = rockchip_pll_round_rate,
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.set_rate = rockchip_rk3066_pll_set_rate,
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.enable = rockchip_rk3066_pll_enable,
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.disable = rockchip_rk3066_pll_disable,
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.is_enabled = rockchip_rk3066_pll_is_enabled,
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};
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/*
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* Common registering of pll clocks
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*/
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struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
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const char *name, const char **parent_names, u8 num_parents,
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void __iomem *base, int con_offset, int grf_lock_offset,
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int lock_shift, int mode_offset, int mode_shift,
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struct rockchip_pll_rate_table *rate_table,
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spinlock_t *lock)
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{
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const char *pll_parents[3];
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struct clk_init_data init;
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struct rockchip_clk_pll *pll;
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struct clk_mux *pll_mux;
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struct clk *pll_clk, *mux_clk;
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char pll_name[20];
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int ret;
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if (num_parents != 2) {
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pr_err("%s: needs two parent clocks\n", __func__);
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return ERR_PTR(-EINVAL);
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}
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/* name the actual pll */
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snprintf(pll_name, sizeof(pll_name), "pll_%s", name);
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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init.name = pll_name;
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/* keep all plls untouched for now */
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init.flags = CLK_IGNORE_UNUSED;
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init.parent_names = &parent_names[0];
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init.num_parents = 1;
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if (rate_table) {
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int len;
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/* find count of rates in rate_table */
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for (len = 0; rate_table[len].rate != 0; )
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len++;
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pll->rate_count = len;
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pll->rate_table = kmemdup(rate_table,
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pll->rate_count *
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sizeof(struct rockchip_pll_rate_table),
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GFP_KERNEL);
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WARN(!pll->rate_table,
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"%s: could not allocate rate table for %s\n",
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__func__, name);
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}
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switch (pll_type) {
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case pll_rk3066:
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if (!pll->rate_table)
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init.ops = &rockchip_rk3066_pll_clk_norate_ops;
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else
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init.ops = &rockchip_rk3066_pll_clk_ops;
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break;
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default:
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pr_warn("%s: Unknown pll type for pll clk %s\n",
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__func__, name);
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}
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pll->hw.init = &init;
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pll->type = pll_type;
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pll->reg_base = base + con_offset;
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pll->lock_offset = grf_lock_offset;
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pll->lock_shift = lock_shift;
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pll->lock = lock;
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pll->clk_nb.notifier_call = rockchip_pll_notifier_cb;
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pll_clk = clk_register(NULL, &pll->hw);
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if (IS_ERR(pll_clk)) {
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pr_err("%s: failed to register pll clock %s : %ld\n",
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__func__, name, PTR_ERR(pll_clk));
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mux_clk = pll_clk;
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goto err_pll;
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}
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ret = clk_notifier_register(pll_clk, &pll->clk_nb);
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if (ret) {
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pr_err("%s: failed to register clock notifier for %s : %d\n",
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__func__, name, ret);
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mux_clk = ERR_PTR(ret);
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goto err_pll_notifier;
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}
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/* create the mux on top of the real pll */
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pll->pll_mux_ops = &clk_mux_ops;
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pll_mux = &pll->pll_mux;
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/* the actual muxing is xin24m, pll-output, xin32k */
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pll_parents[0] = parent_names[0];
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pll_parents[1] = pll_name;
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pll_parents[2] = parent_names[1];
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init.name = name;
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init.flags = CLK_SET_RATE_PARENT;
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init.ops = pll->pll_mux_ops;
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init.parent_names = pll_parents;
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init.num_parents = ARRAY_SIZE(pll_parents);
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pll_mux->reg = base + mode_offset;
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pll_mux->shift = mode_shift;
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pll_mux->mask = PLL_MODE_MASK;
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pll_mux->flags = 0;
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pll_mux->lock = lock;
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pll_mux->hw.init = &init;
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if (pll_type == pll_rk3066)
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pll_mux->flags |= CLK_MUX_HIWORD_MASK;
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mux_clk = clk_register(NULL, &pll_mux->hw);
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if (IS_ERR(mux_clk))
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goto err_mux;
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return mux_clk;
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err_mux:
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ret = clk_notifier_unregister(pll_clk, &pll->clk_nb);
|
||||
if (ret) {
|
||||
pr_err("%s: could not unregister clock notifier in error path : %d\n",
|
||||
__func__, ret);
|
||||
return mux_clk;
|
||||
}
|
||||
err_pll_notifier:
|
||||
clk_unregister(pll_clk);
|
||||
err_pll:
|
||||
kfree(pll);
|
||||
return mux_clk;
|
||||
}
|
||||
@ -23,6 +23,8 @@
|
||||
#include <linux/slab.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/regmap.h>
|
||||
#include "clk.h"
|
||||
|
||||
/**
|
||||
@ -105,11 +107,15 @@ static DEFINE_SPINLOCK(clk_lock);
|
||||
static struct clk **clk_table;
|
||||
static void __iomem *reg_base;
|
||||
static struct clk_onecell_data clk_data;
|
||||
static struct device_node *cru_node;
|
||||
static struct regmap *grf;
|
||||
|
||||
void __init rockchip_clk_init(struct device_node *np, void __iomem *base,
|
||||
unsigned long nr_clks)
|
||||
{
|
||||
reg_base = base;
|
||||
cru_node = np;
|
||||
grf = ERR_PTR(-EPROBE_DEFER);
|
||||
|
||||
clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
|
||||
if (!clk_table)
|
||||
@ -120,12 +126,41 @@ void __init rockchip_clk_init(struct device_node *np, void __iomem *base,
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
}
|
||||
|
||||
struct regmap *rockchip_clk_get_grf(void)
|
||||
{
|
||||
if (IS_ERR(grf))
|
||||
grf = syscon_regmap_lookup_by_phandle(cru_node, "rockchip,grf");
|
||||
return grf;
|
||||
}
|
||||
|
||||
void rockchip_clk_add_lookup(struct clk *clk, unsigned int id)
|
||||
{
|
||||
if (clk_table && id)
|
||||
clk_table[id] = clk;
|
||||
}
|
||||
|
||||
void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list,
|
||||
unsigned int nr_pll, int grf_lock_offset)
|
||||
{
|
||||
struct clk *clk;
|
||||
int idx;
|
||||
|
||||
for (idx = 0; idx < nr_pll; idx++, list++) {
|
||||
clk = rockchip_clk_register_pll(list->type, list->name,
|
||||
list->parent_names, list->num_parents,
|
||||
reg_base, list->con_offset, grf_lock_offset,
|
||||
list->lock_shift, list->mode_offset,
|
||||
list->mode_shift, list->rate_table, &clk_lock);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register clock %s\n", __func__,
|
||||
list->name);
|
||||
continue;
|
||||
}
|
||||
|
||||
rockchip_clk_add_lookup(clk, list->id);
|
||||
}
|
||||
}
|
||||
|
||||
void __init rockchip_clk_register_branches(
|
||||
struct rockchip_clk_branch *list,
|
||||
unsigned int nr_clk)
|
||||
|
||||
@ -40,6 +40,77 @@
|
||||
#define RK2928_SOFTRST_CON(x) (x * 0x4 + 0x110)
|
||||
#define RK2928_MISC_CON 0x134
|
||||
|
||||
enum rockchip_pll_type {
|
||||
pll_rk3066,
|
||||
};
|
||||
|
||||
#define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
|
||||
{ \
|
||||
.rate = _rate##U, \
|
||||
.nr = _nr, \
|
||||
.nf = _nf, \
|
||||
.no = _no, \
|
||||
.bwadj = (_nf >> 1), \
|
||||
}
|
||||
|
||||
struct rockchip_pll_rate_table {
|
||||
unsigned long rate;
|
||||
unsigned int nr;
|
||||
unsigned int nf;
|
||||
unsigned int no;
|
||||
unsigned int bwadj;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct rockchip_pll_clock: information about pll clock
|
||||
* @id: platform specific id of the clock.
|
||||
* @name: name of this pll clock.
|
||||
* @parent_name: name of the parent clock.
|
||||
* @flags: optional flags for basic clock.
|
||||
* @con_offset: offset of the register for configuring the PLL.
|
||||
* @mode_offset: offset of the register for configuring the PLL-mode.
|
||||
* @mode_shift: offset inside the mode-register for the mode of this pll.
|
||||
* @lock_shift: offset inside the lock register for the lock status.
|
||||
* @type: Type of PLL to be registered.
|
||||
* @rate_table: Table of usable pll rates
|
||||
*/
|
||||
struct rockchip_pll_clock {
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
const char **parent_names;
|
||||
u8 num_parents;
|
||||
unsigned long flags;
|
||||
int con_offset;
|
||||
int mode_offset;
|
||||
int mode_shift;
|
||||
int lock_shift;
|
||||
enum rockchip_pll_type type;
|
||||
struct rockchip_pll_rate_table *rate_table;
|
||||
};
|
||||
|
||||
#define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
|
||||
_lshift, _rtable) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.type = _type, \
|
||||
.name = _name, \
|
||||
.parent_names = _pnames, \
|
||||
.num_parents = ARRAY_SIZE(_pnames), \
|
||||
.flags = CLK_GET_RATE_NOCACHE | _flags, \
|
||||
.con_offset = _con, \
|
||||
.mode_offset = _mode, \
|
||||
.mode_shift = _mshift, \
|
||||
.lock_shift = _lshift, \
|
||||
.rate_table = _rtable, \
|
||||
}
|
||||
|
||||
struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
|
||||
const char *name, const char **parent_names, u8 num_parents,
|
||||
void __iomem *base, int con_offset, int grf_lock_offset,
|
||||
int lock_shift, int reg_mode, int mode_shift,
|
||||
struct rockchip_pll_rate_table *rate_table,
|
||||
spinlock_t *lock);
|
||||
|
||||
#define PNAME(x) static const char *x[] __initconst
|
||||
|
||||
enum rockchip_clk_branch_type {
|
||||
@ -243,8 +314,11 @@ struct rockchip_clk_branch {
|
||||
|
||||
void rockchip_clk_init(struct device_node *np, void __iomem *base,
|
||||
unsigned long nr_clks);
|
||||
struct regmap *rockchip_clk_get_grf(void);
|
||||
void rockchip_clk_add_lookup(struct clk *clk, unsigned int id);
|
||||
void rockchip_clk_register_branches(struct rockchip_clk_branch *clk_list,
|
||||
unsigned int nr_clk);
|
||||
void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list,
|
||||
unsigned int nr_pll, int grf_lock_offset);
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user