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MIPS: pci-ar724x: use dynamically allocated PCI controller structure
The current code uses static variables to store the PCI controller specific data. This works if the system contains one PCI controller only, however it becomes impractical when multiple PCI controllers are present. Move the variables into a dynamically allocated controller specific structure, and use that instead of the static variables. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4912/ Signed-off-by: John Crispin <blogic@openwrt.org>
This commit is contained in:
Gabor Juhos
John Crispin
parent
617fed41e9
commit
908339ef25
@ -9,6 +9,7 @@
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* by the Free Software Foundation.
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*/
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#include <linux/spinlock.h>
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#include <linux/irq.h>
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#include <linux/pci.h>
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#include <linux/module.h>
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@ -28,38 +29,56 @@
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#define AR7240_BAR0_WAR_VALUE 0xffff
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static DEFINE_SPINLOCK(ar724x_pci_lock);
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static void __iomem *ar724x_pci_devcfg_base;
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static void __iomem *ar724x_pci_ctrl_base;
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struct ar724x_pci_controller {
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void __iomem *devcfg_base;
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void __iomem *ctrl_base;
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static u32 ar724x_pci_bar0_value;
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static bool ar724x_pci_bar0_is_cached;
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static bool ar724x_pci_link_up;
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int irq;
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static inline bool ar724x_pci_check_link(void)
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bool link_up;
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bool bar0_is_cached;
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u32 bar0_value;
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spinlock_t lock;
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struct pci_controller pci_controller;
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};
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static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
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{
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u32 reset;
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reset = __raw_readl(ar724x_pci_ctrl_base + AR724X_PCI_REG_RESET);
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reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET);
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return reset & AR724X_PCI_RESET_LINK_UP;
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}
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static inline struct ar724x_pci_controller *
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pci_bus_to_ar724x_controller(struct pci_bus *bus)
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{
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struct pci_controller *hose;
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hose = (struct pci_controller *) bus->sysdata;
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return container_of(hose, struct ar724x_pci_controller, pci_controller);
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}
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static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
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int size, uint32_t *value)
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{
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struct ar724x_pci_controller *apc;
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unsigned long flags;
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void __iomem *base;
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u32 data;
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if (!ar724x_pci_link_up)
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apc = pci_bus_to_ar724x_controller(bus);
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if (!apc->link_up)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (devfn)
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return PCIBIOS_DEVICE_NOT_FOUND;
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base = ar724x_pci_devcfg_base;
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base = apc->devcfg_base;
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spin_lock_irqsave(&ar724x_pci_lock, flags);
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spin_lock_irqsave(&apc->lock, flags);
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data = __raw_readl(base + (where & ~3));
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switch (size) {
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@ -78,17 +97,17 @@ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
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case 4:
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break;
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default:
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spin_unlock_irqrestore(&ar724x_pci_lock, flags);
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spin_unlock_irqrestore(&apc->lock, flags);
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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spin_unlock_irqrestore(&ar724x_pci_lock, flags);
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spin_unlock_irqrestore(&apc->lock, flags);
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if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
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ar724x_pci_bar0_is_cached) {
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apc->bar0_is_cached) {
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/* use the cached value */
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*value = ar724x_pci_bar0_value;
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*value = apc->bar0_value;
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} else {
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*value = data;
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}
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@ -99,12 +118,14 @@ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
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static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
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int size, uint32_t value)
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{
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struct ar724x_pci_controller *apc;
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unsigned long flags;
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void __iomem *base;
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u32 data;
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int s;
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if (!ar724x_pci_link_up)
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apc = pci_bus_to_ar724x_controller(bus);
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if (!apc->link_up)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (devfn)
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@ -122,18 +143,18 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
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* BAR0 register in order to make the device memory
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* accessible.
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*/
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ar724x_pci_bar0_is_cached = true;
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ar724x_pci_bar0_value = value;
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apc->bar0_is_cached = true;
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apc->bar0_value = value;
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value = AR7240_BAR0_WAR_VALUE;
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} else {
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ar724x_pci_bar0_is_cached = false;
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apc->bar0_is_cached = false;
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}
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}
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base = ar724x_pci_devcfg_base;
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base = apc->devcfg_base;
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spin_lock_irqsave(&ar724x_pci_lock, flags);
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spin_lock_irqsave(&apc->lock, flags);
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data = __raw_readl(base + (where & ~3));
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switch (size) {
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@ -151,7 +172,7 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
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data = value;
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break;
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default:
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spin_unlock_irqrestore(&ar724x_pci_lock, flags);
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spin_unlock_irqrestore(&apc->lock, flags);
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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@ -159,7 +180,7 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
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__raw_writel(data, base + (where & ~3));
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/* flush write */
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__raw_readl(base + (where & ~3));
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spin_unlock_irqrestore(&ar724x_pci_lock, flags);
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spin_unlock_irqrestore(&apc->lock, flags);
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return PCIBIOS_SUCCESSFUL;
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}
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@ -183,18 +204,14 @@ static struct resource ar724x_mem_resource = {
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.flags = IORESOURCE_MEM,
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};
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static struct pci_controller ar724x_pci_controller = {
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.pci_ops = &ar724x_pci_ops,
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.io_resource = &ar724x_io_resource,
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.mem_resource = &ar724x_mem_resource,
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};
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static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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struct ar724x_pci_controller *apc;
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void __iomem *base;
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u32 pending;
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base = ar724x_pci_ctrl_base;
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apc = irq_get_handler_data(irq);
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base = apc->ctrl_base;
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pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
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__raw_readl(base + AR724X_PCI_REG_INT_MASK);
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@ -208,10 +225,12 @@ static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
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static void ar724x_pci_irq_unmask(struct irq_data *d)
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{
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struct ar724x_pci_controller *apc;
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void __iomem *base;
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u32 t;
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base = ar724x_pci_ctrl_base;
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apc = irq_data_get_irq_chip_data(d);
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base = apc->ctrl_base;
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switch (d->irq) {
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case ATH79_PCI_IRQ(0):
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@ -225,10 +244,12 @@ static void ar724x_pci_irq_unmask(struct irq_data *d)
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static void ar724x_pci_irq_mask(struct irq_data *d)
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{
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struct ar724x_pci_controller *apc;
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void __iomem *base;
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u32 t;
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base = ar724x_pci_ctrl_base;
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apc = irq_data_get_irq_chip_data(d);
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base = apc->ctrl_base;
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switch (d->irq) {
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case ATH79_PCI_IRQ(0):
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@ -255,12 +276,12 @@ static struct irq_chip ar724x_pci_irq_chip = {
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.irq_mask_ack = ar724x_pci_irq_mask,
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};
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static void ar724x_pci_irq_init(int irq)
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static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc)
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{
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void __iomem *base;
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int i;
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base = ar724x_pci_ctrl_base;
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base = apc->ctrl_base;
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__raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
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__raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
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@ -268,45 +289,59 @@ static void ar724x_pci_irq_init(int irq)
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BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT);
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for (i = ATH79_PCI_IRQ_BASE;
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i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++)
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i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) {
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irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
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handle_level_irq);
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irq_set_chip_data(i, apc);
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}
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irq_set_chained_handler(irq, ar724x_pci_irq_handler);
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irq_set_handler_data(apc->irq, apc);
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irq_set_chained_handler(apc->irq, ar724x_pci_irq_handler);
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}
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static int ar724x_pci_probe(struct platform_device *pdev)
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{
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struct ar724x_pci_controller *apc;
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struct resource *res;
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int irq;
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apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller),
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GFP_KERNEL);
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if (!apc)
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return -ENOMEM;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base");
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if (!res)
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return -EINVAL;
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ar724x_pci_ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
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if (ar724x_pci_ctrl_base == NULL)
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apc->ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
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if (apc->ctrl_base == NULL)
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return -EBUSY;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
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if (!res)
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return -EINVAL;
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ar724x_pci_devcfg_base = devm_request_and_ioremap(&pdev->dev, res);
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if (!ar724x_pci_devcfg_base)
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apc->devcfg_base = devm_request_and_ioremap(&pdev->dev, res);
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if (!apc->devcfg_base)
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return -EBUSY;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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apc->irq = platform_get_irq(pdev, 0);
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if (apc->irq < 0)
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return -EINVAL;
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ar724x_pci_link_up = ar724x_pci_check_link();
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if (!ar724x_pci_link_up)
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spin_lock_init(&apc->lock);
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apc->pci_controller.pci_ops = &ar724x_pci_ops;
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apc->pci_controller.io_resource = &ar724x_io_resource;
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apc->pci_controller.mem_resource = &ar724x_mem_resource;
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apc->link_up = ar724x_pci_check_link(apc);
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if (!apc->link_up)
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dev_warn(&pdev->dev, "PCIe link is down\n");
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ar724x_pci_irq_init(irq);
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ar724x_pci_irq_init(apc);
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register_pci_controller(&ar724x_pci_controller);
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register_pci_controller(&apc->pci_controller);
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return 0;
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}
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