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powercap: intel_rapl: Cleanup Power Limits support
The same set of operations are shared by different Powert Limits, including Power Limit get/set, Power Limit enable/disable, clamping enable/disable, time window get/set, and max power get/set, etc. But the same operation for different Power Limit has different primitives because they use different registers/register bits. A lot of dirty/duplicate code was introduced to handle this difference. Introduce a universal way to issue Power Limit operations. Instead of using hardcoded primitive name directly, use Power Limit id + operation type, and hide all the Power Limit difference details in a central place, get_pl_prim(). Two helpers, rapl_read_pl_data() and rapl_write_pl_data(), are introduced at the same time to simplify the code for issuing Power Limit operations. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Tested-by: Wang Wendy <wendy.wang@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This commit is contained in:
Zhang Rui
Rafael J. Wysocki
parent
a38f300bb2
commit
9050a9cd5e
@ -96,9 +96,67 @@ enum unit_type {
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#define DOMAIN_STATE_POWER_LIMIT_SET BIT(1)
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#define DOMAIN_STATE_BIOS_LOCKED BIT(2)
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static const char pl1_name[] = "long_term";
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static const char pl2_name[] = "short_term";
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static const char pl4_name[] = "peak_power";
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static const char *pl_names[NR_POWER_LIMITS] = {
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[POWER_LIMIT1] = "long_term",
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[POWER_LIMIT2] = "short_term",
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[POWER_LIMIT4] = "peak_power",
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};
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enum pl_prims {
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PL_ENABLE,
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PL_CLAMP,
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PL_LIMIT,
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PL_TIME_WINDOW,
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PL_MAX_POWER,
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};
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static bool is_pl_valid(struct rapl_domain *rd, int pl)
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{
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if (pl < POWER_LIMIT1 || pl > POWER_LIMIT4)
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return false;
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return rd->rpl[pl].name ? true : false;
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}
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static int get_pl_prim(int pl, enum pl_prims prim)
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{
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switch (pl) {
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case POWER_LIMIT1:
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if (prim == PL_ENABLE)
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return PL1_ENABLE;
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if (prim == PL_CLAMP)
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return PL1_CLAMP;
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if (prim == PL_LIMIT)
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return POWER_LIMIT1;
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if (prim == PL_TIME_WINDOW)
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return TIME_WINDOW1;
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if (prim == PL_MAX_POWER)
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return THERMAL_SPEC_POWER;
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return -EINVAL;
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case POWER_LIMIT2:
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if (prim == PL_ENABLE)
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return PL2_ENABLE;
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if (prim == PL_CLAMP)
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return PL2_CLAMP;
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if (prim == PL_LIMIT)
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return POWER_LIMIT2;
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if (prim == PL_TIME_WINDOW)
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return TIME_WINDOW2;
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if (prim == PL_MAX_POWER)
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return MAX_POWER;
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return -EINVAL;
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case POWER_LIMIT4:
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if (prim == PL_LIMIT)
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return POWER_LIMIT4;
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if (prim == PL_ENABLE)
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return PL4_ENABLE;
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/* PL4 would be around two times PL2, use same prim as PL2. */
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if (prim == PL_MAX_POWER)
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return MAX_POWER;
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return -EINVAL;
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default:
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return -EINVAL;
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}
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}
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#define power_zone_to_rapl_domain(_zone) \
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container_of(_zone, struct rapl_domain, power_zone)
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@ -155,6 +213,12 @@ static int rapl_read_data_raw(struct rapl_domain *rd,
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static int rapl_write_data_raw(struct rapl_domain *rd,
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enum rapl_primitives prim,
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unsigned long long value);
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static int rapl_read_pl_data(struct rapl_domain *rd, int pl,
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enum pl_prims pl_prim,
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bool xlate, u64 *data);
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static int rapl_write_pl_data(struct rapl_domain *rd, int pl,
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enum pl_prims pl_prim,
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unsigned long long value);
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static u64 rapl_unit_xlate(struct rapl_domain *rd,
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enum unit_type type, u64 value, int to_raw);
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static void package_power_limit_irq_save(struct rapl_package *rp);
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@ -222,7 +286,7 @@ static int find_nr_power_limit(struct rapl_domain *rd)
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int i, nr_pl = 0;
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for (i = 0; i < NR_POWER_LIMITS; i++) {
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if (rd->rpl[i].name)
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if (is_pl_valid(rd, i))
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nr_pl++;
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}
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@ -233,37 +297,34 @@ static int set_domain_enable(struct powercap_zone *power_zone, bool mode)
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{
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struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
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struct rapl_defaults *defaults = get_defaults(rd->rp);
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if (rd->state & DOMAIN_STATE_BIOS_LOCKED)
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return -EACCES;
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int ret;
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cpus_read_lock();
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rapl_write_data_raw(rd, PL1_ENABLE, mode);
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if (defaults->set_floor_freq)
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ret = rapl_write_pl_data(rd, POWER_LIMIT1, PL_ENABLE, mode);
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if (!ret && defaults->set_floor_freq)
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defaults->set_floor_freq(rd, mode);
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cpus_read_unlock();
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return 0;
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return ret;
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}
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static int get_domain_enable(struct powercap_zone *power_zone, bool *mode)
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{
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struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
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u64 val;
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int ret;
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if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
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*mode = false;
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return 0;
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}
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cpus_read_lock();
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if (rapl_read_data_raw(rd, PL1_ENABLE, true, &val)) {
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cpus_read_unlock();
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return -EIO;
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}
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*mode = val;
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ret = rapl_read_pl_data(rd, POWER_LIMIT1, PL_ENABLE, true, &val);
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if (!ret)
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*mode = val;
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cpus_read_unlock();
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return 0;
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return ret;
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}
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/* per RAPL domain ops, in the order of rapl_domain_type */
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@ -319,8 +380,8 @@ static int contraint_to_pl(struct rapl_domain *rd, int cid)
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{
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int i, j;
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for (i = 0, j = 0; i < NR_POWER_LIMITS; i++) {
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if ((rd->rpl[i].name) && j++ == cid) {
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for (i = POWER_LIMIT1, j = 0; i < NR_POWER_LIMITS; i++) {
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if (is_pl_valid(rd, i) && j++ == cid) {
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pr_debug("%s: index %d\n", __func__, i);
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return i;
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}
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@ -341,36 +402,11 @@ static int set_power_limit(struct powercap_zone *power_zone, int cid,
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cpus_read_lock();
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rd = power_zone_to_rapl_domain(power_zone);
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id = contraint_to_pl(rd, cid);
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if (id < 0) {
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ret = id;
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goto set_exit;
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}
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rp = rd->rp;
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if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
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dev_warn(&power_zone->dev,
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"%s locked by BIOS, monitoring only\n", rd->name);
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ret = -EACCES;
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goto set_exit;
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}
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switch (rd->rpl[id].prim_id) {
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case PL1_ENABLE:
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rapl_write_data_raw(rd, POWER_LIMIT1, power_limit);
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break;
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case PL2_ENABLE:
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rapl_write_data_raw(rd, POWER_LIMIT2, power_limit);
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break;
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case PL4_ENABLE:
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rapl_write_data_raw(rd, POWER_LIMIT4, power_limit);
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break;
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default:
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ret = -EINVAL;
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}
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ret = rapl_write_pl_data(rd, id, PL_LIMIT, power_limit);
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if (!ret)
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package_power_limit_irq_save(rp);
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set_exit:
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cpus_read_unlock();
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return ret;
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}
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@ -380,38 +416,17 @@ static int get_current_power_limit(struct powercap_zone *power_zone, int cid,
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{
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struct rapl_domain *rd;
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u64 val;
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int prim;
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int ret = 0;
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int id;
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cpus_read_lock();
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rd = power_zone_to_rapl_domain(power_zone);
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id = contraint_to_pl(rd, cid);
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if (id < 0) {
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ret = id;
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goto get_exit;
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}
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switch (rd->rpl[id].prim_id) {
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case PL1_ENABLE:
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prim = POWER_LIMIT1;
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break;
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case PL2_ENABLE:
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prim = POWER_LIMIT2;
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break;
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case PL4_ENABLE:
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prim = POWER_LIMIT4;
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break;
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default:
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cpus_read_unlock();
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return -EINVAL;
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}
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if (rapl_read_data_raw(rd, prim, true, &val))
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ret = -EIO;
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else
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ret = rapl_read_pl_data(rd, id, PL_LIMIT, true, &val);
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if (!ret)
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*data = val;
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get_exit:
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cpus_read_unlock();
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return ret;
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@ -427,23 +442,9 @@ static int set_time_window(struct powercap_zone *power_zone, int cid,
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cpus_read_lock();
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rd = power_zone_to_rapl_domain(power_zone);
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id = contraint_to_pl(rd, cid);
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if (id < 0) {
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ret = id;
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goto set_time_exit;
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}
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switch (rd->rpl[id].prim_id) {
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case PL1_ENABLE:
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rapl_write_data_raw(rd, TIME_WINDOW1, window);
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break;
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case PL2_ENABLE:
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rapl_write_data_raw(rd, TIME_WINDOW2, window);
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break;
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default:
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ret = -EINVAL;
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}
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ret = rapl_write_pl_data(rd, id, PL_TIME_WINDOW, window);
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set_time_exit:
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cpus_read_unlock();
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return ret;
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}
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@ -459,33 +460,11 @@ static int get_time_window(struct powercap_zone *power_zone, int cid,
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cpus_read_lock();
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rd = power_zone_to_rapl_domain(power_zone);
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id = contraint_to_pl(rd, cid);
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if (id < 0) {
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ret = id;
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goto get_time_exit;
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}
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switch (rd->rpl[id].prim_id) {
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case PL1_ENABLE:
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ret = rapl_read_data_raw(rd, TIME_WINDOW1, true, &val);
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break;
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case PL2_ENABLE:
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ret = rapl_read_data_raw(rd, TIME_WINDOW2, true, &val);
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break;
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case PL4_ENABLE:
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/*
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* Time window parameter is not applicable for PL4 entry
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* so assigining '0' as default value.
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*/
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val = 0;
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break;
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default:
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cpus_read_unlock();
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return -EINVAL;
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}
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ret = rapl_read_pl_data(rd, id, PL_TIME_WINDOW, true, &val);
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if (!ret)
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*data = val;
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get_time_exit:
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cpus_read_unlock();
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return ret;
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@ -505,36 +484,23 @@ static const char *get_constraint_name(struct powercap_zone *power_zone,
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return NULL;
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}
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static int get_max_power(struct powercap_zone *power_zone, int id, u64 *data)
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static int get_max_power(struct powercap_zone *power_zone, int cid, u64 *data)
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{
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struct rapl_domain *rd;
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u64 val;
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int prim;
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int ret = 0;
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int id;
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cpus_read_lock();
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rd = power_zone_to_rapl_domain(power_zone);
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switch (rd->rpl[id].prim_id) {
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case PL1_ENABLE:
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prim = THERMAL_SPEC_POWER;
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break;
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case PL2_ENABLE:
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prim = MAX_POWER;
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break;
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case PL4_ENABLE:
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prim = MAX_POWER;
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break;
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default:
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cpus_read_unlock();
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return -EINVAL;
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}
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if (rapl_read_data_raw(rd, prim, true, &val))
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ret = -EIO;
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else
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id = contraint_to_pl(rd, cid);
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ret = rapl_read_pl_data(rd, id, PL_MAX_POWER, true, &val);
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if (!ret)
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*data = val;
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/* As a generalization rule, PL4 would be around two times PL2. */
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if (rd->rpl[id].prim_id == PL4_ENABLE)
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if (id == POWER_LIMIT4)
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*data = *data * 2;
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cpus_read_unlock();
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@ -560,6 +526,7 @@ static void rapl_init_domains(struct rapl_package *rp)
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for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
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unsigned int mask = rp->domain_map & (1 << i);
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int t;
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if (!mask)
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continue;
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@ -577,17 +544,10 @@ static void rapl_init_domains(struct rapl_package *rp)
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/* PL1 is supported by default */
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rp->priv->limits[i] |= BIT(POWER_LIMIT1);
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rd->rpl[0].prim_id = PL1_ENABLE;
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rd->rpl[0].name = pl1_name;
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if (rp->priv->limits[i] & BIT(POWER_LIMIT2)) {
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rd->rpl[1].prim_id = PL2_ENABLE;
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rd->rpl[1].name = pl2_name;
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}
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if (rp->priv->limits[i] & BIT(POWER_LIMIT4)) {
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rd->rpl[2].prim_id = PL4_ENABLE;
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rd->rpl[2].name = pl4_name;
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for (t = POWER_LIMIT1; t < NR_POWER_LIMITS; t++) {
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if (rp->priv->limits[i] & BIT(t))
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rd->rpl[t].name = pl_names[t];
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}
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for (j = 0; j < RAPL_DOMAIN_REG_MAX; j++)
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@ -818,6 +778,33 @@ static int rapl_write_data_raw(struct rapl_domain *rd,
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return ret;
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}
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static int rapl_read_pl_data(struct rapl_domain *rd, int pl,
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enum pl_prims pl_prim, bool xlate, u64 *data)
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{
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enum rapl_primitives prim = get_pl_prim(pl, pl_prim);
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if (!is_pl_valid(rd, pl))
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return -EINVAL;
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return rapl_read_data_raw(rd, prim, xlate, data);
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}
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static int rapl_write_pl_data(struct rapl_domain *rd, int pl,
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enum pl_prims pl_prim,
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unsigned long long value)
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{
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enum rapl_primitives prim = get_pl_prim(pl, pl_prim);
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if (!is_pl_valid(rd, pl))
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return -EINVAL;
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if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
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pr_warn("%s:%s:%s locked by BIOS\n", rd->rp->name, rd->name, pl_names[pl]);
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return -EACCES;
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}
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return rapl_write_data_raw(rd, prim, value);
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}
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/*
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* Raw RAPL data stored in MSRs are in certain scales. We need to
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* convert them into standard units based on the units reported in
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@ -945,17 +932,16 @@ static void package_power_limit_irq_restore(struct rapl_package *rp)
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static void set_floor_freq_default(struct rapl_domain *rd, bool mode)
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{
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int nr_powerlimit = find_nr_power_limit(rd);
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int i;
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/* always enable clamp such that p-state can go below OS requested
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* range. power capping priority over guranteed frequency.
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*/
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rapl_write_data_raw(rd, PL1_CLAMP, mode);
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rapl_write_pl_data(rd, POWER_LIMIT1, PL_CLAMP, mode);
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/* some domains have pl2 */
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if (nr_powerlimit > 1) {
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rapl_write_data_raw(rd, PL2_ENABLE, mode);
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rapl_write_data_raw(rd, PL2_CLAMP, mode);
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for (i = POWER_LIMIT2; i < NR_POWER_LIMITS; i++) {
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rapl_write_pl_data(rd, i, PL_ENABLE, mode);
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rapl_write_pl_data(rd, i, PL_CLAMP, mode);
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}
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}
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@ -1327,11 +1313,10 @@ static void rapl_detect_powerlimit(struct rapl_domain *rd)
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rd->state |= DOMAIN_STATE_BIOS_LOCKED;
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}
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}
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/* check if power limit MSR exists, otherwise domain is monitoring only */
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for (i = 0; i < NR_POWER_LIMITS; i++) {
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int prim = rd->rpl[i].prim_id;
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if (rapl_read_data_raw(rd, prim, false, &val64))
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/* check if power limit exists, otherwise domain is monitoring only */
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for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) {
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if (rapl_read_pl_data(rd, i, PL_ENABLE, false, &val64))
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rd->rpl[i].name = NULL;
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}
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}
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@ -1381,13 +1366,13 @@ void rapl_remove_package(struct rapl_package *rp)
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package_power_limit_irq_restore(rp);
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for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
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||||
rapl_write_data_raw(rd, PL1_ENABLE, 0);
|
||||
rapl_write_data_raw(rd, PL1_CLAMP, 0);
|
||||
if (find_nr_power_limit(rd) > 1) {
|
||||
rapl_write_data_raw(rd, PL2_ENABLE, 0);
|
||||
rapl_write_data_raw(rd, PL2_CLAMP, 0);
|
||||
rapl_write_data_raw(rd, PL4_ENABLE, 0);
|
||||
int i;
|
||||
|
||||
for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) {
|
||||
rapl_write_pl_data(rd, i, PL_ENABLE, 0);
|
||||
rapl_write_pl_data(rd, i, PL_CLAMP, 0);
|
||||
}
|
||||
|
||||
if (rd->id == RAPL_DOMAIN_PACKAGE) {
|
||||
rd_package = rd;
|
||||
continue;
|
||||
@ -1472,38 +1457,18 @@ static void power_limit_state_save(void)
|
||||
{
|
||||
struct rapl_package *rp;
|
||||
struct rapl_domain *rd;
|
||||
int nr_pl, ret, i;
|
||||
int ret, i;
|
||||
|
||||
cpus_read_lock();
|
||||
list_for_each_entry(rp, &rapl_packages, plist) {
|
||||
if (!rp->power_zone)
|
||||
continue;
|
||||
rd = power_zone_to_rapl_domain(rp->power_zone);
|
||||
nr_pl = find_nr_power_limit(rd);
|
||||
for (i = 0; i < nr_pl; i++) {
|
||||
switch (rd->rpl[i].prim_id) {
|
||||
case PL1_ENABLE:
|
||||
ret = rapl_read_data_raw(rd,
|
||||
POWER_LIMIT1, true,
|
||||
for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) {
|
||||
ret = rapl_read_pl_data(rd, i, PL_LIMIT, true,
|
||||
&rd->rpl[i].last_power_limit);
|
||||
if (ret)
|
||||
rd->rpl[i].last_power_limit = 0;
|
||||
break;
|
||||
case PL2_ENABLE:
|
||||
ret = rapl_read_data_raw(rd,
|
||||
POWER_LIMIT2, true,
|
||||
&rd->rpl[i].last_power_limit);
|
||||
if (ret)
|
||||
rd->rpl[i].last_power_limit = 0;
|
||||
break;
|
||||
case PL4_ENABLE:
|
||||
ret = rapl_read_data_raw(rd,
|
||||
POWER_LIMIT4, true,
|
||||
&rd->rpl[i].last_power_limit);
|
||||
if (ret)
|
||||
rd->rpl[i].last_power_limit = 0;
|
||||
break;
|
||||
}
|
||||
if (ret)
|
||||
rd->rpl[i].last_power_limit = 0;
|
||||
}
|
||||
}
|
||||
cpus_read_unlock();
|
||||
@ -1513,33 +1478,17 @@ static void power_limit_state_restore(void)
|
||||
{
|
||||
struct rapl_package *rp;
|
||||
struct rapl_domain *rd;
|
||||
int nr_pl, i;
|
||||
int i;
|
||||
|
||||
cpus_read_lock();
|
||||
list_for_each_entry(rp, &rapl_packages, plist) {
|
||||
if (!rp->power_zone)
|
||||
continue;
|
||||
rd = power_zone_to_rapl_domain(rp->power_zone);
|
||||
nr_pl = find_nr_power_limit(rd);
|
||||
for (i = 0; i < nr_pl; i++) {
|
||||
switch (rd->rpl[i].prim_id) {
|
||||
case PL1_ENABLE:
|
||||
if (rd->rpl[i].last_power_limit)
|
||||
rapl_write_data_raw(rd, POWER_LIMIT1,
|
||||
rd->rpl[i].last_power_limit);
|
||||
break;
|
||||
case PL2_ENABLE:
|
||||
if (rd->rpl[i].last_power_limit)
|
||||
rapl_write_data_raw(rd, POWER_LIMIT2,
|
||||
rd->rpl[i].last_power_limit);
|
||||
break;
|
||||
case PL4_ENABLE:
|
||||
if (rd->rpl[i].last_power_limit)
|
||||
rapl_write_data_raw(rd, POWER_LIMIT4,
|
||||
rd->rpl[i].last_power_limit);
|
||||
break;
|
||||
}
|
||||
}
|
||||
for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++)
|
||||
if (rd->rpl[i].last_power_limit)
|
||||
rapl_write_pl_data(rd, i, PL_LIMIT,
|
||||
rd->rpl[i].last_power_limit);
|
||||
}
|
||||
cpus_read_unlock();
|
||||
}
|
||||
|
||||
@ -79,7 +79,6 @@ struct rapl_domain_data {
|
||||
|
||||
struct rapl_power_limit {
|
||||
struct powercap_zone_constraint *constraint;
|
||||
int prim_id; /* primitive ID used to enable */
|
||||
struct rapl_domain *domain;
|
||||
const char *name;
|
||||
u64 last_power_limit;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user