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ARM: dts: r8a7792: add SMP support

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Add the device tree nodes for the Advanced Power Management Unit (APMU)
and the second Cortex-A15 CPU core.
Use the "enable-method" prop  to point out that the APMU should be used
for the SMP support.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Sergei Shtylyov 2016-06-21 01:31:01 +03:00 committed by Simon Horman
parent 65b133cd79
commit 8fd763c75c
1 changed files with 16 additions and 0 deletions
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16
arch/arm/boot/dts/r8a7792.dtsi
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@ -21,6 +21,7 @@
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 { cpu0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
@ -32,6 +33,15 @@
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
}; };
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1000000000>;
power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
next-level-cache = <&L2_CA15>;
};
L2_CA15: cache-controller@0 { L2_CA15: cache-controller@0 {
compatible = "cache"; compatible = "cache";
reg = <0>; reg = <0>;
@ -49,6 +59,12 @@
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
apmu@e6152000 {
compatible = "renesas,r8a7792-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1>;
};
gic: interrupt-controller@f1001000 { gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400"; compatible = "arm,gic-400";
#interrupt-cells = <3>; #interrupt-cells = <3>;