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mv643xx_eth: fix TX hang erratum workaround
The previously merged TX hang erratum workaround ("mv643xx_eth: work around TX hang hardware issue") assumes that TX_END interrupts are delivered simultaneously with or after their corresponding TX interrupts, but this is not always true in practise. In particular, it appears that TX_END interrupts are issued as soon as descriptor fetch returns an invalid descriptor, which may happen before earlier descriptors have been fully transmitted and written back to memory as being done. This hardware behavior can lead to a situation where the current driver code mistakenly assumes that the MAC has given up transmitting before noticing the packets that it is in fact still currently working on, causing the driver to re-kick the transmit queue, which will only cause the MAC to re-fetch the invalid head descriptor, and generate another TX_END interrupt, et cetera, until the packets in the pipe finally finish transmitting and have their descriptors written back to memory, which will then finally break the loop. Fix this by having the erratum workaround not check the 'number of unfinished descriptor', but instead, to compare the software's idea of what the head descriptor pointer should be to the hardware's head descriptor pointer (which is updated on the same conditions as the TX_END interupt is generated on, i.e. possibly before all previous descriptors have been transmitted and written back). Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
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@ -96,6 +96,7 @@ static char mv643xx_eth_driver_version[] = "1.1";
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#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
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#define TX_BW_BURST(p) (0x045c + ((p) << 10))
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#define INT_CAUSE(p) (0x0460 + ((p) << 10))
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#define INT_TX_END_0 0x00080000
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#define INT_TX_END 0x07f80000
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#define INT_RX 0x0007fbfc
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#define INT_EXT 0x00000002
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@ -706,6 +707,7 @@ static inline __be16 sum16_as_be(__sum16 sum)
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static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
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{
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struct mv643xx_eth_private *mp = txq_to_mp(txq);
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int nr_frags = skb_shinfo(skb)->nr_frags;
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int tx_index;
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struct tx_desc *desc;
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@ -759,6 +761,10 @@ static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
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wmb();
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desc->cmd_sts = cmd_sts;
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/* clear TX_END interrupt status */
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wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
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rdl(mp, INT_CAUSE(mp->port_num));
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/* ensure all descriptors are written before poking hardware */
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wmb();
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txq_enable(txq);
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@ -1684,7 +1690,6 @@ static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
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struct mv643xx_eth_private *mp = netdev_priv(dev);
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u32 int_cause;
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u32 int_cause_ext;
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u32 txq_active;
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int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
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(INT_TX_END | INT_RX | INT_EXT);
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@ -1743,8 +1748,6 @@ static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
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}
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#endif
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txq_active = rdl(mp, TXQ_COMMAND(mp->port_num));
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/*
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* TxBuffer or TxError set for any of the 8 queues?
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*/
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@ -1754,6 +1757,14 @@ static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
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for (i = 0; i < 8; i++)
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if (mp->txq_mask & (1 << i))
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txq_reclaim(mp->txq + i, 0);
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/*
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* Enough space again in the primary TX queue for a
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* full packet?
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*/
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spin_lock(&mp->lock);
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__txq_maybe_wake(mp->txq + mp->txq_primary);
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spin_unlock(&mp->lock);
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}
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/*
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@ -1763,19 +1774,25 @@ static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
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int i;
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wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
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spin_lock(&mp->lock);
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for (i = 0; i < 8; i++) {
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struct tx_queue *txq = mp->txq + i;
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if (txq->tx_desc_count && !((txq_active >> i) & 1))
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u32 hw_desc_ptr;
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u32 expected_ptr;
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if ((int_cause & (INT_TX_END_0 << i)) == 0)
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continue;
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hw_desc_ptr =
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rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
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expected_ptr = (u32)txq->tx_desc_dma +
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txq->tx_curr_desc * sizeof(struct tx_desc);
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if (hw_desc_ptr != expected_ptr)
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txq_enable(txq);
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}
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}
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/*
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* Enough space again in the primary TX queue for a full packet?
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*/
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if (int_cause_ext & INT_EXT_TX) {
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struct tx_queue *txq = mp->txq + mp->txq_primary;
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__txq_maybe_wake(txq);
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spin_unlock(&mp->lock);
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}
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return IRQ_HANDLED;
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