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Pin control bulk changes for the v6.11 kernel series:
Core changes: None. New drivers: - Renesas RZ/V2H(P) SoC - NXP Freescale i.MX91 SoC - Nuvoton MA35D1 SoC - Qualcomm PMC8380, SM4250, SM4250 LPI Enhancements: - A slew of scoped-based simplifications of of_node_put(). -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmacNaMACgkQQRCzN7AZ XXM2zBAApbYm8ftQ0Og6AKEapMUWWQl8eo0TMG4E81vqx9oAs0qDjFvKyHioy/Gm ZKwfmRPFqg/rxWP4eFOCE/dQwL7gELPOIiJJOlV+qF9dUcQo/cdSPze//mt06iTl xRnKL8/r+LlFU2qBcfqzdrqeCV52TZUhRrYlau+9CxGkFTF7KVNQossInMPC91gY aClovH5CDn1pl8SOziGOpPVqv9UJR0KkEDeoroWQ6IcBx3OutAan77KySpJFThcJ ZHN7cNYPgLItmJz7ERXtWumVRM4sRZ0jwQeUE9A+tMuTyhplguKHDeZjRxojoGkM HcYA7WUUrMPNzc9163+7A9qEhMzR6HINFBtysRWuQolofYq44w50/v6DL5xvdOoe 1adJzxH+JiBRWQ4fTq4Gc2QEICY59kmHamOrGLGCqeIldMRC+fQCHF+4mnqMSbru eXuvdXjzPes1KflmaHmb6s2AxJjYLmIdcfsElMAy7uz9hghzPhYUeq0157Fa3Igp M7dK1Wh9lGjudLvEXz6ZW/OV57eOo+Xc7yISVi/OnD+qiMejnzNoEcy83zSa/7sh O/BlbuHOwVv+Gysgs0Fphu9GjZuPuzjT8NyKlzouFgrUE38LojY/Dz1SF1FYJL+9 9t6TbnJnpmPwVMT3p63BmSj5f3iTUXqGd0IPqCZltTc1rPl7X/w= =79pj -----END PGP SIGNATURE----- Merge tag 'pinctrl-v6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Some new drivers is the main part, the rest is cleanups and nonurgent fixes. Nothing much special about this, no core changes this time. New drivers: - Renesas RZ/V2H(P) SoC - NXP Freescale i.MX91 SoC - Nuvoton MA35D1 SoC - Qualcomm PMC8380, SM4250, SM4250 LPI Enhancements: - A slew of scoped-based simplifications of of_node_put()" * tag 'pinctrl-v6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (110 commits) pinctrl: renesas: rzg2l: Support output enable on RZ/G2L pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions pinctrl: renesas: rzg2l: Clarify OEN read/write support dt-bindings: pinctrl: pinctrl-single: Fix pinctrl-single,gpio-range description dt-bindings: pinctrl: npcm8xx: add missing pin group and mux function dt-bindings: pinctrl: pinctrl-single: fix schmitt related properties pinctrl: freescale: Use scope based of_node_put() cleanups pinctrl: equilibrium: Use scope based of_node_put() cleanups pinctrl: ti: iodelay: Use scope based of_node_put() cleanups pinctrl: qcom: lpass-lpi: increase MAX_NR_GPIO to 32 pinctrl: cy8c95x0: Update cache modification pinctrl: cy8c95x0: Use cleanup.h pinctrl: renesas: r8a779h0: Remove unneeded separators pinctrl: renesas: r8a779g0: Add INTC-EX pins, groups, and function pinctrl: renesas: r8a779g0: Remove unneeded separators pinctrl: renesas: r8a779h0: Add AVB MII pins and groups pinctrl: renesas: r8a779g0: Fix TPU suffixes pinctrl: renesas: r8a779g0: Fix TCLK suffixes pinctrl: renesas: r8a779g0: FIX PWM suffixes pinctrl: renesas: r8a779g0: Fix IRQ suffixes ...
This commit is contained in:
Linus Torvalds
commit
8e313211f7
@ -255,7 +255,9 @@ properties:
|
||||
type: object
|
||||
allOf:
|
||||
- $ref: '#/$defs/protocol-node'
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||||
- $ref: /schemas/pinctrl/pinctrl.yaml
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||||
- anyOf:
|
||||
- $ref: /schemas/pinctrl/pinctrl.yaml
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||||
- $ref: /schemas/firmware/nxp,imx95-scmi-pinctrl.yaml
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||||
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unevaluatedProperties: false
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||||
|
||||
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||||
@ -0,0 +1,53 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright 2024 NXP
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/firmware/nxp,imx95-scmi-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: i.MX System Control and Management Interface (SCMI) Pinctrl Protocol
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maintainers:
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- Peng Fan <peng.fan@nxp.com>
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allOf:
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||||
- $ref: /schemas/pinctrl/pinctrl.yaml
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||||
|
||||
patternProperties:
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||||
'grp$':
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type: object
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||||
description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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||||
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unevaluatedProperties: false
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||||
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properties:
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fsl,pins:
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description:
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each entry consists of 6 integers and represents the mux and config
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setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
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mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
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be found in <arch/arm64/boot/dts/freescale/imx95-pinfunc.h>. The last
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integer CONFIG is the pad setting value like pull-up on this pin.
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Please refer to i.MX95 Reference Manual for detailed CONFIG settings.
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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items:
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items:
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- description: |
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||||
"mux_reg" indicates the offset of mux register.
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- description: |
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"conf_reg" indicates the offset of pad configuration register.
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- description: |
|
||||
"input_reg" indicates the offset of select input register.
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- description: |
|
||||
"mux_val" indicates the mux value to be applied.
|
||||
- description: |
|
||||
"input_val" indicates the select input value to be applied.
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||||
- description: |
|
||||
"pad_setting" indicates the pad configuration value to be applied.
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||||
|
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required:
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- fsl,pins
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||||
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additionalProperties: true
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||||
@ -35,22 +35,159 @@ additionalProperties:
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||||
|
||||
patternProperties:
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||||
"^function|groups$":
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enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
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||||
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT,
|
||||
EXTRST, FLACK, FLBUSY, FLWP, GPID, GPID0, GPID2, GPID4, GPID6, GPIE0,
|
||||
GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4,
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||||
I2C5, I2C6, I2C7, I2C8, I2C9, LPCPD, LPCPME, LPCRST, LPCSMI, MAC1LINK,
|
||||
MAC2LINK, MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2,
|
||||
NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4,
|
||||
NDTS4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, OSCCLK, PWM0,
|
||||
PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1,
|
||||
RMII2, ROM16, ROM8, ROMCS1, ROMCS2, ROMCS3, ROMCS4, RXD1, RXD2, RXD3,
|
||||
RXD4, SALT1, SALT2, SALT3, SALT4, SD1, SD2, SGPMCK, SGPMI, SGPMLD,
|
||||
SGPMO, SGPSCK, SGPSI0, SGPSI1, SGPSLD, SIOONCTRL, SIOPBI, SIOPBO,
|
||||
SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1DEBUG, SPI1PASSTHRU,
|
||||
SPICS1, TIMER3, TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2,
|
||||
TXD3, TXD4, UART6, USB11D1, USB11H2, USB2D1, USB2H1, USBCKI, VGABIOS_ROM,
|
||||
VGAHS, VGAVS, VPI18, VPI24, VPI30, VPO12, VPO24, WDTRST1, WDTRST2]
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||||
enum:
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||||
- ACPI
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- ADC0
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- ADC1
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- ADC10
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- ADC11
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- ADC12
|
||||
- ADC13
|
||||
- ADC14
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||||
- ADC15
|
||||
- ADC2
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||||
- ADC3
|
||||
- ADC4
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||||
- ADC5
|
||||
- ADC6
|
||||
- ADC7
|
||||
- ADC8
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||||
- ADC9
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||||
- BMCINT
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- DDCCLK
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||||
- DDCDAT
|
||||
- EXTRST
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||||
- FLACK
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- FLBUSY
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- FLWP
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- GPID
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- GPID0
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||||
- GPID2
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- GPID4
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- GPID6
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- GPIE0
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- GPIE2
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- GPIE4
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- GPIE6
|
||||
- I2C10
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||||
- I2C11
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- I2C12
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- I2C13
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- I2C14
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||||
- I2C3
|
||||
- I2C4
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||||
- I2C5
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||||
- I2C6
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- I2C7
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- I2C8
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- I2C9
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- LPCPD
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- LPCPME
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- LPCRST
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- LPCSMI
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- MAC1LINK
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- MAC2LINK
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- MDIO1
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- MDIO2
|
||||
- NCTS1
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- NCTS2
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- NCTS3
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- NCTS4
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||||
- NDCD1
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||||
- NDCD2
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||||
- NDCD3
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||||
- NDCD4
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- NDSR1
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- NDSR2
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- NDSR3
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- NDSR4
|
||||
- NDTR1
|
||||
- NDTR2
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||||
- NDTR3
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- NDTR4
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||||
- NDTS4
|
||||
- NRI1
|
||||
- NRI2
|
||||
- NRI3
|
||||
- NRI4
|
||||
- NRTS1
|
||||
- NRTS2
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||||
- NRTS3
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||||
- OSCCLK
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||||
- PWM0
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||||
- PWM1
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||||
- PWM2
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- PWM3
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- PWM4
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||||
- PWM5
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||||
- PWM6
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- PWM7
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||||
- RGMII1
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- RGMII2
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- RMII1
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||||
- RMII2
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||||
- ROM16
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||||
- ROM8
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||||
- ROMCS1
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||||
- ROMCS2
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||||
- ROMCS3
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||||
- ROMCS4
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||||
- RXD1
|
||||
- RXD2
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||||
- RXD3
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||||
- RXD4
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||||
- SALT1
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||||
- SALT2
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||||
- SALT3
|
||||
- SALT4
|
||||
- SD1
|
||||
- SD2
|
||||
- SGPMCK
|
||||
- SGPMI
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||||
- SGPMLD
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||||
- SGPMO
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||||
- SGPSCK
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||||
- SGPSI0
|
||||
- SGPSI1
|
||||
- SGPSLD
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||||
- SIOONCTRL
|
||||
- SIOPBI
|
||||
- SIOPBO
|
||||
- SIOPWREQ
|
||||
- SIOPWRGD
|
||||
- SIOS3
|
||||
- SIOS5
|
||||
- SIOSCI
|
||||
- SPI1
|
||||
- SPI1DEBUG
|
||||
- SPI1PASSTHRU
|
||||
- SPICS1
|
||||
- TIMER3
|
||||
- TIMER4
|
||||
- TIMER5
|
||||
- TIMER6
|
||||
- TIMER7
|
||||
- TIMER8
|
||||
- TXD1
|
||||
- TXD2
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||||
- TXD3
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||||
- TXD4
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||||
- UART6
|
||||
- USB11D1
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||||
- USB11H2
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||||
- USB2D1
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||||
- USB2H1
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||||
- USBCKI
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||||
- VGABIOS_ROM
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||||
- VGAHS
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||||
- VGAVS
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||||
- VPI18
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||||
- VPI24
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||||
- VPI30
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||||
- VPO12
|
||||
- VPO24
|
||||
- WDTRST1
|
||||
- WDTRST2
|
||||
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allOf:
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||||
- $ref: pinctrl.yaml#
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||||
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||||
@ -35,7 +35,7 @@ properties:
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||||
description: |
|
||||
A cell of phandles to external controller nodes:
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0: compatible with "aspeed,ast2500-gfx", "syscon"
|
||||
1: compatible with "aspeed,ast2500-lhc", "syscon"
|
||||
1: compatible with "aspeed,ast2500-lpc", "syscon"
|
||||
|
||||
additionalProperties:
|
||||
$ref: pinmux-node.yaml#
|
||||
@ -47,24 +47,174 @@ additionalProperties:
|
||||
|
||||
patternProperties:
|
||||
"^function|groups$":
|
||||
enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
|
||||
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT,
|
||||
ESPI, FWSPICS1, FWSPICS2, GPID0, GPID2, GPID4, GPID6, GPIE0, GPIE2,
|
||||
GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4, I2C5,
|
||||
I2C6, I2C7, I2C8, I2C9, LAD0, LAD1, LAD2, LAD3, LCLK, LFRAME, LPCHC,
|
||||
LPCPD, LPCPLUS, LPCPME, LPCRST, LPCSMI, LSIRQ, MAC1LINK, MAC2LINK,
|
||||
MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4,
|
||||
NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2,
|
||||
NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PNOR, PWM0,
|
||||
PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1,
|
||||
RMII2, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13,
|
||||
SALT14, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9, SCL1,
|
||||
SCL2, SD1, SD2, SDA1, SDA2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO,
|
||||
SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1CS1, SPI1DEBUG,
|
||||
SPI1PASSTHRU, SPI2CK, SPI2CS0, SPI2CS1, SPI2MISO, SPI2MOSI, TIMER3,
|
||||
TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2, TXD3, TXD4, UART6,
|
||||
USB11BHID, USB2AD, USB2AH, USB2BD, USB2BH, USBCKI, VGABIOSROM, VGAHS,
|
||||
VGAVS, VPI24, VPO, WDTRST1, WDTRST2]
|
||||
enum:
|
||||
- ACPI
|
||||
- ADC0
|
||||
- ADC1
|
||||
- ADC10
|
||||
- ADC11
|
||||
- ADC12
|
||||
- ADC13
|
||||
- ADC14
|
||||
- ADC15
|
||||
- ADC2
|
||||
- ADC3
|
||||
- ADC4
|
||||
- ADC5
|
||||
- ADC6
|
||||
- ADC7
|
||||
- ADC8
|
||||
- ADC9
|
||||
- BMCINT
|
||||
- DDCCLK
|
||||
- DDCDAT
|
||||
- ESPI
|
||||
- FWSPICS1
|
||||
- FWSPICS2
|
||||
- GPID0
|
||||
- GPID2
|
||||
- GPID4
|
||||
- GPID6
|
||||
- GPIE0
|
||||
- GPIE2
|
||||
- GPIE4
|
||||
- GPIE6
|
||||
- I2C10
|
||||
- I2C11
|
||||
- I2C12
|
||||
- I2C13
|
||||
- I2C14
|
||||
- I2C3
|
||||
- I2C4
|
||||
- I2C5
|
||||
- I2C6
|
||||
- I2C7
|
||||
- I2C8
|
||||
- I2C9
|
||||
- LAD0
|
||||
- LAD1
|
||||
- LAD2
|
||||
- LAD3
|
||||
- LCLK
|
||||
- LFRAME
|
||||
- LPCHC
|
||||
- LPCPD
|
||||
- LPCPLUS
|
||||
- LPCPME
|
||||
- LPCRST
|
||||
- LPCSMI
|
||||
- LSIRQ
|
||||
- MAC1LINK
|
||||
- MAC2LINK
|
||||
- MDIO1
|
||||
- MDIO2
|
||||
- NCTS1
|
||||
- NCTS2
|
||||
- NCTS3
|
||||
- NCTS4
|
||||
- NDCD1
|
||||
- NDCD2
|
||||
- NDCD3
|
||||
- NDCD4
|
||||
- NDSR1
|
||||
- NDSR2
|
||||
- NDSR3
|
||||
- NDSR4
|
||||
- NDTR1
|
||||
- NDTR2
|
||||
- NDTR3
|
||||
- NDTR4
|
||||
- NRI1
|
||||
- NRI2
|
||||
- NRI3
|
||||
- NRI4
|
||||
- NRTS1
|
||||
- NRTS2
|
||||
- NRTS3
|
||||
- NRTS4
|
||||
- OSCCLK
|
||||
- PEWAKE
|
||||
- PNOR
|
||||
- PWM0
|
||||
- PWM1
|
||||
- PWM2
|
||||
- PWM3
|
||||
- PWM4
|
||||
- PWM5
|
||||
- PWM6
|
||||
- PWM7
|
||||
- RGMII1
|
||||
- RGMII2
|
||||
- RMII1
|
||||
- RMII2
|
||||
- RXD1
|
||||
- RXD2
|
||||
- RXD3
|
||||
- RXD4
|
||||
- SALT1
|
||||
- SALT10
|
||||
- SALT11
|
||||
- SALT12
|
||||
- SALT13
|
||||
- SALT14
|
||||
- SALT2
|
||||
- SALT3
|
||||
- SALT4
|
||||
- SALT5
|
||||
- SALT6
|
||||
- SALT7
|
||||
- SALT8
|
||||
- SALT9
|
||||
- SCL1
|
||||
- SCL2
|
||||
- SD1
|
||||
- SD2
|
||||
- SDA1
|
||||
- SDA2
|
||||
- SGPM
|
||||
- SGPS1
|
||||
- SGPS2
|
||||
- SIOONCTRL
|
||||
- SIOPBI
|
||||
- SIOPBO
|
||||
- SIOPWREQ
|
||||
- SIOPWRGD
|
||||
- SIOS3
|
||||
- SIOS5
|
||||
- SIOSCI
|
||||
- SPI1
|
||||
- SPI1CS1
|
||||
- SPI1DEBUG
|
||||
- SPI1PASSTHRU
|
||||
- SPI2CK
|
||||
- SPI2CS0
|
||||
- SPI2CS1
|
||||
- SPI2MISO
|
||||
- SPI2MOSI
|
||||
- TIMER3
|
||||
- TIMER4
|
||||
- TIMER5
|
||||
- TIMER6
|
||||
- TIMER7
|
||||
- TIMER8
|
||||
- TXD1
|
||||
- TXD2
|
||||
- TXD3
|
||||
- TXD4
|
||||
- UART6
|
||||
- USB11BHID
|
||||
- USB2AD
|
||||
- USB2AH
|
||||
- USB2BD
|
||||
- USB2BH
|
||||
- USBCKI
|
||||
- VGABIOSROM
|
||||
- VGAHS
|
||||
- VGAVS
|
||||
- VPI24
|
||||
- VPO
|
||||
- WDTRST1
|
||||
- WDTRST2
|
||||
|
||||
allOf:
|
||||
- $ref: pinctrl.yaml#
|
||||
|
||||
@ -19,6 +19,11 @@ description: |+
|
||||
Refer to the bindings described in
|
||||
Documentation/devicetree/bindings/mfd/syscon.yaml
|
||||
|
||||
Note: According to the NCSI specification, the reference clock output pin
|
||||
(RMIIXRCLKO) is not required on the management controller side. To optimize
|
||||
pin usage, add "NCSI" pin groups that are equivalent to the RMII pin groups,
|
||||
but without the RMIIXRCLKO pin.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: aspeed,ast2600-pinctrl
|
||||
@ -29,56 +34,469 @@ additionalProperties:
|
||||
|
||||
properties:
|
||||
function:
|
||||
enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
|
||||
ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC, ESPI, ESPIALT,
|
||||
FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3,
|
||||
GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5,
|
||||
GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16,
|
||||
I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5,
|
||||
I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ,
|
||||
MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4,
|
||||
NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2,
|
||||
NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4,
|
||||
NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PWM0, PWM1, PWM10, PWM11,
|
||||
PWM12, PWM13, PWM14, PWM15, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8,
|
||||
PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4,
|
||||
RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, SALT14,
|
||||
SALT15, SALT16, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8,
|
||||
SALT9, SD1, SD2, SGPM1, SGPM2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO,
|
||||
SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2,
|
||||
SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13, TACH14,
|
||||
TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0,
|
||||
THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12,
|
||||
UART13, UART6, UART7, UART8, UART9, USBAD, USBADP, USB2AH, USB2AHP,
|
||||
USB2BD, USB2BH, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4 ]
|
||||
enum:
|
||||
- ADC0
|
||||
- ADC1
|
||||
- ADC10
|
||||
- ADC11
|
||||
- ADC12
|
||||
- ADC13
|
||||
- ADC14
|
||||
- ADC15
|
||||
- ADC2
|
||||
- ADC3
|
||||
- ADC4
|
||||
- ADC5
|
||||
- ADC6
|
||||
- ADC7
|
||||
- ADC8
|
||||
- ADC9
|
||||
- BMCINT
|
||||
- EMMC
|
||||
- ESPI
|
||||
- ESPIALT
|
||||
- FSI1
|
||||
- FSI2
|
||||
- FWQSPI
|
||||
- FWSPIABR
|
||||
- FWSPID
|
||||
- FWSPIWP
|
||||
- GPIT0
|
||||
- GPIT1
|
||||
- GPIT2
|
||||
- GPIT3
|
||||
- GPIT4
|
||||
- GPIT5
|
||||
- GPIT6
|
||||
- GPIT7
|
||||
- GPIU0
|
||||
- GPIU1
|
||||
- GPIU2
|
||||
- GPIU3
|
||||
- GPIU4
|
||||
- GPIU5
|
||||
- GPIU6
|
||||
- GPIU7
|
||||
- I2C1
|
||||
- I2C10
|
||||
- I2C11
|
||||
- I2C12
|
||||
- I2C13
|
||||
- I2C14
|
||||
- I2C15
|
||||
- I2C16
|
||||
- I2C2
|
||||
- I2C3
|
||||
- I2C4
|
||||
- I2C5
|
||||
- I2C6
|
||||
- I2C7
|
||||
- I2C8
|
||||
- I2C9
|
||||
- I3C1
|
||||
- I3C2
|
||||
- I3C3
|
||||
- I3C4
|
||||
- I3C5
|
||||
- I3C6
|
||||
- JTAGM
|
||||
- LHPD
|
||||
- LHSIRQ
|
||||
- LPC
|
||||
- LPCHC
|
||||
- LPCPD
|
||||
- LPCPME
|
||||
- LPCSMI
|
||||
- LSIRQ
|
||||
- MACLINK1
|
||||
- MACLINK2
|
||||
- MACLINK3
|
||||
- MACLINK4
|
||||
- MDIO1
|
||||
- MDIO2
|
||||
- MDIO3
|
||||
- MDIO4
|
||||
- NCTS1
|
||||
- NCTS2
|
||||
- NCTS3
|
||||
- NCTS4
|
||||
- NDCD1
|
||||
- NDCD2
|
||||
- NDCD3
|
||||
- NDCD4
|
||||
- NDSR1
|
||||
- NDSR2
|
||||
- NDSR3
|
||||
- NDSR4
|
||||
- NDTR1
|
||||
- NDTR2
|
||||
- NDTR3
|
||||
- NDTR4
|
||||
- NRI1
|
||||
- NRI2
|
||||
- NRI3
|
||||
- NRI4
|
||||
- NRTS1
|
||||
- NRTS2
|
||||
- NRTS3
|
||||
- NRTS4
|
||||
- OSCCLK
|
||||
- PEWAKE
|
||||
- PWM0
|
||||
- PWM1
|
||||
- PWM10
|
||||
- PWM11
|
||||
- PWM12
|
||||
- PWM13
|
||||
- PWM14
|
||||
- PWM15
|
||||
- PWM2
|
||||
- PWM3
|
||||
- PWM4
|
||||
- PWM5
|
||||
- PWM6
|
||||
- PWM7
|
||||
- PWM8
|
||||
- PWM9
|
||||
- RGMII1
|
||||
- RGMII2
|
||||
- RGMII3
|
||||
- RGMII4
|
||||
- RMII1
|
||||
- RMII2
|
||||
- RMII3
|
||||
- RMII4
|
||||
- RXD1
|
||||
- RXD2
|
||||
- RXD3
|
||||
- RXD4
|
||||
- SALT1
|
||||
- SALT10
|
||||
- SALT11
|
||||
- SALT12
|
||||
- SALT13
|
||||
- SALT14
|
||||
- SALT15
|
||||
- SALT16
|
||||
- SALT2
|
||||
- SALT3
|
||||
- SALT4
|
||||
- SALT5
|
||||
- SALT6
|
||||
- SALT7
|
||||
- SALT8
|
||||
- SALT9
|
||||
- SD1
|
||||
- SD2
|
||||
- SGPM1
|
||||
- SGPM2
|
||||
- SGPS1
|
||||
- SGPS2
|
||||
- SIOONCTRL
|
||||
- SIOPBI
|
||||
- SIOPBO
|
||||
- SIOPWREQ
|
||||
- SIOPWRGD
|
||||
- SIOS3
|
||||
- SIOS5
|
||||
- SIOSCI
|
||||
- SPI1
|
||||
- SPI1ABR
|
||||
- SPI1CS1
|
||||
- SPI1WP
|
||||
- SPI2
|
||||
- SPI2CS1
|
||||
- SPI2CS2
|
||||
- TACH0
|
||||
- TACH1
|
||||
- TACH10
|
||||
- TACH11
|
||||
- TACH12
|
||||
- TACH13
|
||||
- TACH14
|
||||
- TACH15
|
||||
- TACH2
|
||||
- TACH3
|
||||
- TACH4
|
||||
- TACH5
|
||||
- TACH6
|
||||
- TACH7
|
||||
- TACH8
|
||||
- TACH9
|
||||
- THRU0
|
||||
- THRU1
|
||||
- THRU2
|
||||
- THRU3
|
||||
- TXD1
|
||||
- TXD2
|
||||
- TXD3
|
||||
- TXD4
|
||||
- UART10
|
||||
- UART11
|
||||
- UART12
|
||||
- UART13
|
||||
- UART6
|
||||
- UART7
|
||||
- UART8
|
||||
- UART9
|
||||
- USB11BHID
|
||||
- USB2AD
|
||||
- USB2AH
|
||||
- USB2AHP
|
||||
- USB2BD
|
||||
- USB2BH
|
||||
- USBAD
|
||||
- USBADP
|
||||
- VB
|
||||
- VGAHS
|
||||
- VGAVS
|
||||
- WDTRST1
|
||||
- WDTRST2
|
||||
- WDTRST3
|
||||
- WDTRST4
|
||||
|
||||
groups:
|
||||
enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
|
||||
ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1, EMMCG4,
|
||||
EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP,
|
||||
GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
|
||||
GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1, I2C10,
|
||||
I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5,
|
||||
I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ,
|
||||
LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3,
|
||||
MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, NCTS3, NCTS4,
|
||||
NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2,
|
||||
NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4,
|
||||
OSCCLK, PEWAKE, PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, PWM12G0,
|
||||
PWM12G1, PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, PWM15G1, PWM2,
|
||||
PWM3, PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, PWM9G0, PWM9G1, QSPI1,
|
||||
QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4,
|
||||
RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1, SALT11G0, SALT11G1,
|
||||
SALT12G0, SALT12G1, SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0,
|
||||
SALT15G1, SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6,
|
||||
SALT7, SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPM2, SGPS1, SGPS2,
|
||||
SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1,
|
||||
SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11,
|
||||
TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6,
|
||||
TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3,
|
||||
TXD4, UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6,
|
||||
UART7, UART8, UART9, USBA, USBB, VB, VGAHS, VGAVS, WDTRST1, WDTRST2,
|
||||
WDTRST3, WDTRST4]
|
||||
enum:
|
||||
- ADC0
|
||||
- ADC1
|
||||
- ADC10
|
||||
- ADC11
|
||||
- ADC12
|
||||
- ADC13
|
||||
- ADC14
|
||||
- ADC15
|
||||
- ADC2
|
||||
- ADC3
|
||||
- ADC4
|
||||
- ADC5
|
||||
- ADC6
|
||||
- ADC7
|
||||
- ADC8
|
||||
- ADC9
|
||||
- BMCINT
|
||||
- EMMCG1
|
||||
- EMMCG4
|
||||
- EMMCG8
|
||||
- ESPI
|
||||
- ESPIALT
|
||||
- FSI1
|
||||
- FSI2
|
||||
- FWQSPI
|
||||
- FWSPIABR
|
||||
- FWSPID
|
||||
- FWSPIWP
|
||||
- GPIT0
|
||||
- GPIT1
|
||||
- GPIT2
|
||||
- GPIT3
|
||||
- GPIT4
|
||||
- GPIT5
|
||||
- GPIT6
|
||||
- GPIT7
|
||||
- GPIU0
|
||||
- GPIU1
|
||||
- GPIU2
|
||||
- GPIU3
|
||||
- GPIU4
|
||||
- GPIU5
|
||||
- GPIU6
|
||||
- GPIU7
|
||||
- HVI3C3
|
||||
- HVI3C4
|
||||
- I2C1
|
||||
- I2C10
|
||||
- I2C11
|
||||
- I2C12
|
||||
- I2C13
|
||||
- I2C14
|
||||
- I2C15
|
||||
- I2C16
|
||||
- I2C2
|
||||
- I2C3
|
||||
- I2C4
|
||||
- I2C5
|
||||
- I2C6
|
||||
- I2C7
|
||||
- I2C8
|
||||
- I2C9
|
||||
- I3C1
|
||||
- I3C2
|
||||
- I3C3
|
||||
- I3C4
|
||||
- I3C5
|
||||
- I3C6
|
||||
- JTAGM
|
||||
- LHPD
|
||||
- LHSIRQ
|
||||
- LPC
|
||||
- LPCHC
|
||||
- LPCPD
|
||||
- LPCPME
|
||||
- LPCSMI
|
||||
- LSIRQ
|
||||
- MACLINK1
|
||||
- MACLINK2
|
||||
- MACLINK3
|
||||
- MACLINK4
|
||||
- MDIO1
|
||||
- MDIO2
|
||||
- MDIO3
|
||||
- MDIO4
|
||||
- NCSI3
|
||||
- NCSI4
|
||||
- NCTS1
|
||||
- NCTS2
|
||||
- NCTS3
|
||||
- NCTS4
|
||||
- NDCD1
|
||||
- NDCD2
|
||||
- NDCD3
|
||||
- NDCD4
|
||||
- NDSR1
|
||||
- NDSR2
|
||||
- NDSR3
|
||||
- NDSR4
|
||||
- NDTR1
|
||||
- NDTR2
|
||||
- NDTR3
|
||||
- NDTR4
|
||||
- NRI1
|
||||
- NRI2
|
||||
- NRI3
|
||||
- NRI4
|
||||
- NRTS1
|
||||
- NRTS2
|
||||
- NRTS3
|
||||
- NRTS4
|
||||
- OSCCLK
|
||||
- PEWAKE
|
||||
- PWM0
|
||||
- PWM1
|
||||
- PWM10G0
|
||||
- PWM10G1
|
||||
- PWM11G0
|
||||
- PWM11G1
|
||||
- PWM12G0
|
||||
- PWM12G1
|
||||
- PWM13G0
|
||||
- PWM13G1
|
||||
- PWM14G0
|
||||
- PWM14G1
|
||||
- PWM15G0
|
||||
- PWM15G1
|
||||
- PWM2
|
||||
- PWM3
|
||||
- PWM4
|
||||
- PWM5
|
||||
- PWM6
|
||||
- PWM7
|
||||
- PWM8G0
|
||||
- PWM8G1
|
||||
- PWM9G0
|
||||
- PWM9G1
|
||||
- QSPI1
|
||||
- QSPI2
|
||||
- RGMII1
|
||||
- RGMII2
|
||||
- RGMII3
|
||||
- RGMII4
|
||||
- RMII1
|
||||
- RMII2
|
||||
- RMII3
|
||||
- RMII4
|
||||
- RXD1
|
||||
- RXD2
|
||||
- RXD3
|
||||
- RXD4
|
||||
- SALT1
|
||||
- SALT10G0
|
||||
- SALT10G1
|
||||
- SALT11G0
|
||||
- SALT11G1
|
||||
- SALT12G0
|
||||
- SALT12G1
|
||||
- SALT13G0
|
||||
- SALT13G1
|
||||
- SALT14G0
|
||||
- SALT14G1
|
||||
- SALT15G0
|
||||
- SALT15G1
|
||||
- SALT16G0
|
||||
- SALT16G1
|
||||
- SALT2
|
||||
- SALT3
|
||||
- SALT4
|
||||
- SALT5
|
||||
- SALT6
|
||||
- SALT7
|
||||
- SALT8
|
||||
- SALT9G0
|
||||
- SALT9G1
|
||||
- SD1
|
||||
- SD2
|
||||
- SD3
|
||||
- SGPM1
|
||||
- SGPM2
|
||||
- SGPS1
|
||||
- SGPS2
|
||||
- SIOONCTRL
|
||||
- SIOPBI
|
||||
- SIOPBO
|
||||
- SIOPWREQ
|
||||
- SIOPWRGD
|
||||
- SIOS3
|
||||
- SIOS5
|
||||
- SIOSCI
|
||||
- SPI1
|
||||
- SPI1ABR
|
||||
- SPI1CS1
|
||||
- SPI1WP
|
||||
- SPI2
|
||||
- SPI2CS1
|
||||
- SPI2CS2
|
||||
- TACH0
|
||||
- TACH1
|
||||
- TACH10
|
||||
- TACH11
|
||||
- TACH12
|
||||
- TACH13
|
||||
- TACH14
|
||||
- TACH15
|
||||
- TACH2
|
||||
- TACH3
|
||||
- TACH4
|
||||
- TACH5
|
||||
- TACH6
|
||||
- TACH7
|
||||
- TACH8
|
||||
- TACH9
|
||||
- THRU0
|
||||
- THRU1
|
||||
- THRU2
|
||||
- THRU3
|
||||
- TXD1
|
||||
- TXD2
|
||||
- TXD3
|
||||
- TXD4
|
||||
- UART10
|
||||
- UART11
|
||||
- UART12G0
|
||||
- UART12G1
|
||||
- UART13G0
|
||||
- UART13G1
|
||||
- UART6
|
||||
- UART7
|
||||
- UART8
|
||||
- UART9
|
||||
- USBA
|
||||
- USBB
|
||||
- VB
|
||||
- VGAHS
|
||||
- VGAVS
|
||||
- WDTRST1
|
||||
- WDTRST2
|
||||
- WDTRST3
|
||||
- WDTRST4
|
||||
|
||||
pins: true
|
||||
bias-disable: true
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/fsl,imx93-pinctrl.yaml#
|
||||
$id: http://devicetree.org/schemas/pinctrl/fsl,imx9-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale IMX93 IOMUX Controller
|
||||
title: Freescale IMX9 IOMUX Controller
|
||||
|
||||
maintainers:
|
||||
- Peng Fan <peng.fan@nxp.com>
|
||||
@ -18,7 +18,9 @@ allOf:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx93-iomuxc
|
||||
enum:
|
||||
- fsl,imx91-iomuxc
|
||||
- fsl,imx93-iomuxc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -0,0 +1,178 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/nuvoton,ma35d1-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Nuvoton MA35D1 pin control and GPIO
|
||||
|
||||
maintainers:
|
||||
- Shan-Chun Hung <schung@nuvoton.com>
|
||||
- Jacky Huang <ychuang3@nuvoton.com>
|
||||
|
||||
allOf:
|
||||
- $ref: pinctrl.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nuvoton,ma35d1-pinctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 1
|
||||
|
||||
nuvoton,sys:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
phandle of the system-management node.
|
||||
|
||||
ranges: true
|
||||
|
||||
patternProperties:
|
||||
"^gpio@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
const: 2
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 2
|
||||
|
||||
interrupts:
|
||||
description:
|
||||
The interrupt outputs to sysirq.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- reg
|
||||
- clocks
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
"-grp$":
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
patternProperties:
|
||||
"-pins$":
|
||||
type: object
|
||||
description:
|
||||
A pinctrl node should contain at least one subnodes representing the
|
||||
pinctrl groups available on the machine. Each subnode will list the
|
||||
pins it needs, and how they should be configured, with regard to muxer
|
||||
configuration, pullups, drive strength, input enable/disable and input
|
||||
schmitt.
|
||||
$ref: /schemas/pinctrl/pincfg-node.yaml
|
||||
|
||||
properties:
|
||||
nuvoton,pins:
|
||||
description:
|
||||
Each entry consists of 4 parameters and represents the mux and config
|
||||
setting for one pin.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
minItems: 1
|
||||
items:
|
||||
items:
|
||||
- minimum: 0
|
||||
maximum: 13
|
||||
description:
|
||||
Pin bank.
|
||||
- minimum: 0
|
||||
maximum: 15
|
||||
description:
|
||||
Pin bank index.
|
||||
- minimum: 0
|
||||
maximum: 15
|
||||
description:
|
||||
Mux 0 means GPIO and mux 1 to 15 means the specific device function.
|
||||
|
||||
power-source:
|
||||
description: |
|
||||
Valid arguments are described as below:
|
||||
0: power supply of 1.8V
|
||||
1: power supply of 3.3V
|
||||
enum: [0, 1]
|
||||
|
||||
drive-strength-microamp:
|
||||
oneOf:
|
||||
- enum: [ 2900, 4400, 5800, 7300, 8600, 10100, 11500, 13000 ]
|
||||
description: 1.8V I/O driving strength
|
||||
- enum: [ 17100, 25600, 34100, 42800, 48000, 56000, 77000, 82000 ]
|
||||
description: 3.3V I/O driving strength
|
||||
|
||||
bias-disable: true
|
||||
|
||||
bias-pull-up: true
|
||||
|
||||
bias-pull-down: true
|
||||
|
||||
input-schmitt-disable: true
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- nuvoton,sys
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
|
||||
|
||||
pinctrl@40040000 {
|
||||
compatible = "nuvoton,ma35d1-pinctrl";
|
||||
reg = <0x40040000 0xc00>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
nuvoton,sys = <&sys>;
|
||||
ranges = <0x0 0x40040000 0x400>;
|
||||
|
||||
gpio@0 {
|
||||
reg = <0x0 0x40>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk GPA_GATE>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
uart-grp {
|
||||
uart11-pins {
|
||||
nuvoton,pins = <11 0 2>,
|
||||
<11 1 2>,
|
||||
<11 2 2>,
|
||||
<11 3 2>;
|
||||
power-source = <1>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -85,11 +85,12 @@ patternProperties:
|
||||
smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
|
||||
sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
|
||||
mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk,
|
||||
scipme, smi, smb6, smb7, spi1, faninx, r1, spi3, spi3cs1,
|
||||
spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c, smb0den,
|
||||
smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13, spix,
|
||||
spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4,
|
||||
hgpio5, hgpio6, hgpio7 ]
|
||||
scipme, smi, smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c,
|
||||
smb7d, spi1, faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2,
|
||||
spi3cs3, nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio,
|
||||
wdog1, wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0,
|
||||
hgpio1, hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4,
|
||||
bu4b, bu5, bu5b, bu6, gpo187 ]
|
||||
|
||||
function:
|
||||
description:
|
||||
@ -109,11 +110,12 @@ patternProperties:
|
||||
smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
|
||||
sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
|
||||
mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk,
|
||||
scipme, smi, smb6, smb7, spi1, faninx, r1, spi3, spi3cs1,
|
||||
spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c, smb0den,
|
||||
smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13, spix,
|
||||
spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4,
|
||||
hgpio5, hgpio6, hgpio7 ]
|
||||
scipme, smi, smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c,
|
||||
smb7d, spi1, faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2,
|
||||
spi3cs3, nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio,
|
||||
wdog1, wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0,
|
||||
hgpio1, hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4,
|
||||
bu4b, bu5, bu5b, bu6, gpo187 ]
|
||||
|
||||
dependencies:
|
||||
groups: [ function ]
|
||||
|
||||
@ -75,11 +75,11 @@ properties:
|
||||
description: Optional list of pin base, nr pins & gpio function
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
- items:
|
||||
- description: phandle of a gpio-range node
|
||||
- description: pin base
|
||||
- description: number of pins
|
||||
- description: gpio function
|
||||
items:
|
||||
- description: phandle of a gpio-range node
|
||||
- description: pin base
|
||||
- description: number of pins
|
||||
- description: gpio function
|
||||
|
||||
'#gpio-range-cells':
|
||||
description: No longer needed, may exist in older files for gpio-ranges
|
||||
@ -144,6 +144,13 @@ patternProperties:
|
||||
- description: drive strength mask
|
||||
|
||||
pinctrl-single,input-schmitt:
|
||||
description: Optional schmitt strength configuration
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- description: schmitt strength current
|
||||
- description: schmitt strength mask
|
||||
|
||||
pinctrl-single,input-schmitt-enable:
|
||||
description: Optional input schmitt configuration
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
|
||||
@ -56,6 +56,7 @@ properties:
|
||||
- qcom,pma8084-gpio
|
||||
- qcom,pmc8180-gpio
|
||||
- qcom,pmc8180c-gpio
|
||||
- qcom,pmc8380-gpio
|
||||
- qcom,pmd8028-gpio
|
||||
- qcom,pmi632-gpio
|
||||
- qcom,pmi8950-gpio
|
||||
@ -223,6 +224,7 @@ allOf:
|
||||
- qcom,pm8150-gpio
|
||||
- qcom,pm8350-gpio
|
||||
- qcom,pmc8180-gpio
|
||||
- qcom,pmc8380-gpio
|
||||
- qcom,pmi8994-gpio
|
||||
- qcom,pmm8155au-gpio
|
||||
then:
|
||||
|
||||
@ -0,0 +1,118 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM4250 SoC LPASS LPI TLMM
|
||||
|
||||
maintainers:
|
||||
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
|
||||
(LPASS) Low Power Island (LPI) of Qualcomm SM4250 SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm4250-lpass-lpi-pinctrl
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: LPASS LPI TLMM Control and Status registers
|
||||
- description: LPASS LPI MCC registers
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: LPASS Audio voting clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: audio
|
||||
|
||||
patternProperties:
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sm4250-lpass-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-sm4250-lpass-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-sm4250-lpass-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
pattern: "^gpio([0-9]|1[0-9]|2[0-6])$"
|
||||
|
||||
function:
|
||||
enum: [ gpio, dmic01_clk, dmic01_data, dmic23_clk, dmic23_data,
|
||||
dmic4_clk, dmic4_data, ext_mclk0_a, ext_mclk0_b, ext_mclk1_a,
|
||||
ext_mclk1_b, ext_mclk1_c, i2s1_clk, i2s1_data, i2s1_ws,
|
||||
i2s2_clk, i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws,
|
||||
qua_mi2s_data, qua_mi2s_sclk, qua_mi2s_ws, slim_clk, slim_data,
|
||||
swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data, swr_wsa_clk,
|
||||
swr_wsa_data ]
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins.
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,lpass-lpi-common.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/sound/qcom,q6afe.h>
|
||||
lpi_tlmm: pinctrl@a7c0000 {
|
||||
compatible = "qcom,sm4250-lpass-lpi-pinctrl";
|
||||
reg = <0xa7c0000 0x20000>,
|
||||
<0xa950000 0x10000>;
|
||||
clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
|
||||
clock-names = "audio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&lpi_tlmm 0 0 19>;
|
||||
|
||||
i2s2-active-state {
|
||||
clk-pins {
|
||||
pins = "gpio10";
|
||||
function = "i2s2_clk";
|
||||
drive-strength = <2>;
|
||||
slew-rate = <1>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
data-pins {
|
||||
pins = "gpio12";
|
||||
function = "i2s2_data";
|
||||
drive-strength = <2>;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
i2s2-sleep-clk-state {
|
||||
pins = "gpio10";
|
||||
function = "i2s2_clk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
@ -26,6 +26,7 @@ properties:
|
||||
- renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
|
||||
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
|
||||
- renesas,r9a08g045-pinctrl # RZ/G3S
|
||||
- renesas,r9a09g057-pinctrl # RZ/V2H(P)
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
@ -66,10 +67,14 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: GPIO_RSTN signal
|
||||
- description: GPIO_PORT_RESETN signal
|
||||
- description: GPIO_SPARE_RESETN signal
|
||||
oneOf:
|
||||
- items:
|
||||
- description: GPIO_RSTN signal
|
||||
- description: GPIO_PORT_RESETN signal
|
||||
- description: GPIO_SPARE_RESETN signal
|
||||
- items:
|
||||
- description: PFC main reset
|
||||
- description: Reset for the control register related to WDTUDFCA and WDTUDFFCM pins
|
||||
|
||||
additionalProperties:
|
||||
anyOf:
|
||||
@ -79,21 +84,6 @@ additionalProperties:
|
||||
- $ref: pincfg-node.yaml#
|
||||
- $ref: pinmux-node.yaml#
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,r9a08g045-pinctrl
|
||||
then:
|
||||
properties:
|
||||
drive-strength: false
|
||||
output-impedance-ohms: false
|
||||
slew-rate: false
|
||||
else:
|
||||
properties:
|
||||
drive-strength-microamp: false
|
||||
|
||||
description:
|
||||
Pin controller client devices use pin configuration subnodes (children
|
||||
and grandchildren) for desired pin configuration.
|
||||
@ -126,6 +116,16 @@ additionalProperties:
|
||||
output-high: true
|
||||
output-low: true
|
||||
line-name: true
|
||||
bias-disable: true
|
||||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
renesas,output-impedance:
|
||||
description:
|
||||
Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this
|
||||
property corresponds to register bit values that can be set in the PFC_IOLH_mn
|
||||
register, which adjusts the drive strength value and is pin-dependent.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
|
||||
- type: object
|
||||
additionalProperties:
|
||||
@ -134,6 +134,20 @@ additionalProperties:
|
||||
allOf:
|
||||
- $ref: pinctrl.yaml#
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,r9a09g057-pinctrl
|
||||
then:
|
||||
properties:
|
||||
resets:
|
||||
maxItems: 2
|
||||
else:
|
||||
properties:
|
||||
resets:
|
||||
minItems: 3
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@ -42,179 +42,187 @@ patternProperties:
|
||||
$ref: pinmux-node.yaml#
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of pins to select (either this or "groups" must be specified)
|
||||
items:
|
||||
pattern: '^MIO([0-9]|[1-6][0-9]|7[0-7])$'
|
||||
|
||||
groups:
|
||||
description:
|
||||
List of groups to select (either this or "pins" must be
|
||||
specified), available groups for this subnode.
|
||||
items:
|
||||
enum: [ethernet0_0_grp, ethernet1_0_grp, ethernet2_0_grp,
|
||||
ethernet3_0_grp, gemtsu0_0_grp, gemtsu0_1_grp,
|
||||
gemtsu0_2_grp, mdio0_0_grp, mdio1_0_grp,
|
||||
mdio1_1_grp, mdio2_0_grp, mdio3_0_grp,
|
||||
qspi0_0_grp, qspi_ss_0_grp, qspi_fbclk_0_grp,
|
||||
spi0_0_grp, spi0_ss_0_grp, spi0_ss_1_grp,
|
||||
spi0_ss_2_grp, spi0_1_grp, spi0_ss_3_grp,
|
||||
spi0_ss_4_grp, spi0_ss_5_grp, spi0_2_grp,
|
||||
spi0_ss_6_grp, spi0_ss_7_grp, spi0_ss_8_grp,
|
||||
spi0_3_grp, spi0_ss_9_grp, spi0_ss_10_grp,
|
||||
spi0_ss_11_grp, spi0_4_grp, spi0_ss_12_grp,
|
||||
spi0_ss_13_grp, spi0_ss_14_grp, spi0_5_grp,
|
||||
spi0_ss_15_grp, spi0_ss_16_grp, spi0_ss_17_grp,
|
||||
spi1_0_grp, spi1_ss_0_grp, spi1_ss_1_grp,
|
||||
spi1_ss_2_grp, spi1_1_grp, spi1_ss_3_grp,
|
||||
spi1_ss_4_grp, spi1_ss_5_grp, spi1_2_grp,
|
||||
spi1_ss_6_grp, spi1_ss_7_grp, spi1_ss_8_grp,
|
||||
spi1_3_grp, spi1_ss_9_grp, spi1_ss_10_grp,
|
||||
spi1_ss_11_grp, spi1_4_grp, spi1_ss_12_grp,
|
||||
spi1_ss_13_grp, spi1_ss_14_grp, spi1_5_grp,
|
||||
spi1_ss_15_grp, spi1_ss_16_grp, spi1_ss_17_grp,
|
||||
sdio0_0_grp, sdio0_1_grp, sdio0_2_grp,
|
||||
sdio0_3_grp, sdio0_4_grp, sdio0_5_grp,
|
||||
sdio0_6_grp, sdio0_7_grp, sdio0_8_grp,
|
||||
sdio0_9_grp, sdio0_10_grp, sdio0_11_grp,
|
||||
sdio0_12_grp, sdio0_13_grp, sdio0_14_grp,
|
||||
sdio0_15_grp, sdio0_16_grp, sdio0_17_grp,
|
||||
sdio0_18_grp, sdio0_19_grp, sdio0_20_grp,
|
||||
sdio0_21_grp, sdio0_22_grp, sdio0_23_grp,
|
||||
sdio0_24_grp, sdio0_25_grp, sdio0_26_grp,
|
||||
sdio0_27_grp, sdio0_28_grp, sdio0_29_grp,
|
||||
sdio0_30_grp, sdio0_31_grp, sdio0_32_grp,
|
||||
sdio0_pc_0_grp, sdio0_cd_0_grp, sdio0_wp_0_grp,
|
||||
sdio0_pc_1_grp, sdio0_cd_1_grp, sdio0_wp_1_grp,
|
||||
sdio0_pc_2_grp, sdio0_cd_2_grp, sdio0_wp_2_grp,
|
||||
sdio1_0_grp, sdio1_1_grp, sdio1_2_grp,
|
||||
sdio1_3_grp, sdio1_4_grp, sdio1_5_grp,
|
||||
sdio1_6_grp, sdio1_7_grp, sdio1_8_grp,
|
||||
sdio1_9_grp, sdio1_10_grp, sdio1_11_grp,
|
||||
sdio1_12_grp, sdio1_13_grp, sdio1_14_grp,
|
||||
sdio1_15_grp, sdio1_pc_0_grp, sdio1_cd_0_grp,
|
||||
sdio1_wp_0_grp, sdio1_pc_1_grp, sdio1_cd_1_grp,
|
||||
sdio1_wp_1_grp, nand0_0_grp, nand0_ce_0_grp,
|
||||
nand0_rb_0_grp, nand0_dqs_0_grp, nand0_ce_1_grp,
|
||||
nand0_rb_1_grp, nand0_dqs_1_grp, can0_0_grp,
|
||||
can0_1_grp, can0_2_grp, can0_3_grp,
|
||||
can0_4_grp, can0_5_grp, can0_6_grp,
|
||||
can0_7_grp, can0_8_grp, can0_9_grp,
|
||||
can0_10_grp, can0_11_grp, can0_12_grp,
|
||||
can0_13_grp, can0_14_grp, can0_15_grp,
|
||||
can0_16_grp, can0_17_grp, can0_18_grp,
|
||||
can1_0_grp, can1_1_grp, can1_2_grp,
|
||||
can1_3_grp, can1_4_grp, can1_5_grp,
|
||||
can1_6_grp, can1_7_grp, can1_8_grp,
|
||||
can1_9_grp, can1_10_grp, can1_11_grp,
|
||||
can1_12_grp, can1_13_grp, can1_14_grp,
|
||||
can1_15_grp, can1_16_grp, can1_17_grp,
|
||||
can1_18_grp, can1_19_grp, uart0_0_grp,
|
||||
uart0_1_grp, uart0_2_grp, uart0_3_grp,
|
||||
uart0_4_grp, uart0_5_grp, uart0_6_grp,
|
||||
uart0_7_grp, uart0_8_grp, uart0_9_grp,
|
||||
uart0_10_grp, uart0_11_grp, uart0_12_grp,
|
||||
uart0_13_grp, uart0_14_grp, uart0_15_grp,
|
||||
uart0_16_grp, uart0_17_grp, uart0_18_grp,
|
||||
uart1_0_grp, uart1_1_grp, uart1_2_grp,
|
||||
uart1_3_grp, uart1_4_grp, uart1_5_grp,
|
||||
uart1_6_grp, uart1_7_grp, uart1_8_grp,
|
||||
uart1_9_grp, uart1_10_grp, uart1_11_grp,
|
||||
uart1_12_grp, uart1_13_grp, uart1_14_grp,
|
||||
uart1_15_grp, uart1_16_grp, uart1_17_grp,
|
||||
uart1_18_grp, i2c0_0_grp, i2c0_1_grp,
|
||||
i2c0_2_grp, i2c0_3_grp, i2c0_4_grp,
|
||||
i2c0_5_grp, i2c0_6_grp, i2c0_7_grp,
|
||||
i2c0_8_grp, i2c0_9_grp, i2c0_10_grp,
|
||||
i2c0_11_grp, i2c0_12_grp, i2c0_13_grp,
|
||||
i2c0_14_grp, i2c0_15_grp, i2c0_16_grp,
|
||||
i2c0_17_grp, i2c0_18_grp, i2c1_0_grp,
|
||||
i2c1_1_grp, i2c1_2_grp, i2c1_3_grp,
|
||||
i2c1_4_grp, i2c1_5_grp, i2c1_6_grp,
|
||||
i2c1_7_grp, i2c1_8_grp, i2c1_9_grp,
|
||||
i2c1_10_grp, i2c1_11_grp, i2c1_12_grp,
|
||||
i2c1_13_grp, i2c1_14_grp, i2c1_15_grp,
|
||||
i2c1_16_grp, i2c1_17_grp, i2c1_18_grp,
|
||||
i2c1_19_grp, ttc0_clk_0_grp, ttc0_wav_0_grp,
|
||||
ttc0_clk_1_grp, ttc0_wav_1_grp, ttc0_clk_2_grp,
|
||||
ttc0_wav_2_grp, ttc0_clk_3_grp, ttc0_wav_3_grp,
|
||||
ttc0_clk_4_grp, ttc0_wav_4_grp, ttc0_clk_5_grp,
|
||||
ttc0_wav_5_grp, ttc0_clk_6_grp, ttc0_wav_6_grp,
|
||||
ttc0_clk_7_grp, ttc0_wav_7_grp, ttc0_clk_8_grp,
|
||||
ttc0_wav_8_grp, ttc1_clk_0_grp, ttc1_wav_0_grp,
|
||||
ttc1_clk_1_grp, ttc1_wav_1_grp, ttc1_clk_2_grp,
|
||||
ttc1_wav_2_grp, ttc1_clk_3_grp, ttc1_wav_3_grp,
|
||||
ttc1_clk_4_grp, ttc1_wav_4_grp, ttc1_clk_5_grp,
|
||||
ttc1_wav_5_grp, ttc1_clk_6_grp, ttc1_wav_6_grp,
|
||||
ttc1_clk_7_grp, ttc1_wav_7_grp, ttc1_clk_8_grp,
|
||||
ttc1_wav_8_grp, ttc2_clk_0_grp, ttc2_wav_0_grp,
|
||||
ttc2_clk_1_grp, ttc2_wav_1_grp, ttc2_clk_2_grp,
|
||||
ttc2_wav_2_grp, ttc2_clk_3_grp, ttc2_wav_3_grp,
|
||||
ttc2_clk_4_grp, ttc2_wav_4_grp, ttc2_clk_5_grp,
|
||||
ttc2_wav_5_grp, ttc2_clk_6_grp, ttc2_wav_6_grp,
|
||||
ttc2_clk_7_grp, ttc2_wav_7_grp, ttc2_clk_8_grp,
|
||||
ttc2_wav_8_grp, ttc3_clk_0_grp, ttc3_wav_0_grp,
|
||||
ttc3_clk_1_grp, ttc3_wav_1_grp, ttc3_clk_2_grp,
|
||||
ttc3_wav_2_grp, ttc3_clk_3_grp, ttc3_wav_3_grp,
|
||||
ttc3_clk_4_grp, ttc3_wav_4_grp, ttc3_clk_5_grp,
|
||||
ttc3_wav_5_grp, ttc3_clk_6_grp, ttc3_wav_6_grp,
|
||||
ttc3_clk_7_grp, ttc3_wav_7_grp, ttc3_clk_8_grp,
|
||||
ttc3_wav_8_grp, swdt0_clk_0_grp, swdt0_rst_0_grp,
|
||||
swdt0_clk_1_grp, swdt0_rst_1_grp, swdt0_clk_2_grp,
|
||||
swdt0_rst_2_grp, swdt0_clk_3_grp, swdt0_rst_3_grp,
|
||||
swdt0_clk_4_grp, swdt0_rst_4_grp, swdt0_clk_5_grp,
|
||||
swdt0_rst_5_grp, swdt0_clk_6_grp, swdt0_rst_6_grp,
|
||||
swdt0_clk_7_grp, swdt0_rst_7_grp, swdt0_clk_8_grp,
|
||||
swdt0_rst_8_grp, swdt0_clk_9_grp, swdt0_rst_9_grp,
|
||||
swdt0_clk_10_grp, swdt0_rst_10_grp, swdt0_clk_11_grp,
|
||||
swdt0_rst_11_grp, swdt0_clk_12_grp, swdt0_rst_12_grp,
|
||||
swdt1_clk_0_grp, swdt1_rst_0_grp, swdt1_clk_1_grp,
|
||||
swdt1_rst_1_grp, swdt1_clk_2_grp, swdt1_rst_2_grp,
|
||||
swdt1_clk_3_grp, swdt1_rst_3_grp, swdt1_clk_4_grp,
|
||||
swdt1_rst_4_grp, swdt1_clk_5_grp, swdt1_rst_5_grp,
|
||||
swdt1_clk_6_grp, swdt1_rst_6_grp, swdt1_clk_7_grp,
|
||||
swdt1_rst_7_grp, swdt1_clk_8_grp, swdt1_rst_8_grp,
|
||||
swdt1_clk_9_grp, swdt1_rst_9_grp, swdt1_clk_10_grp,
|
||||
swdt1_rst_10_grp, swdt1_clk_11_grp, swdt1_rst_11_grp,
|
||||
swdt1_clk_12_grp, swdt1_rst_12_grp, gpio0_0_grp,
|
||||
gpio0_1_grp, gpio0_2_grp, gpio0_3_grp,
|
||||
gpio0_4_grp, gpio0_5_grp, gpio0_6_grp,
|
||||
gpio0_7_grp, gpio0_8_grp, gpio0_9_grp,
|
||||
gpio0_10_grp, gpio0_11_grp, gpio0_12_grp,
|
||||
gpio0_13_grp, gpio0_14_grp, gpio0_15_grp,
|
||||
gpio0_16_grp, gpio0_17_grp, gpio0_18_grp,
|
||||
gpio0_19_grp, gpio0_20_grp, gpio0_21_grp,
|
||||
gpio0_22_grp, gpio0_23_grp, gpio0_24_grp,
|
||||
gpio0_25_grp, gpio0_26_grp, gpio0_27_grp,
|
||||
gpio0_28_grp, gpio0_29_grp, gpio0_30_grp,
|
||||
gpio0_31_grp, gpio0_32_grp, gpio0_33_grp,
|
||||
gpio0_34_grp, gpio0_35_grp, gpio0_36_grp,
|
||||
gpio0_37_grp, gpio0_38_grp, gpio0_39_grp,
|
||||
gpio0_40_grp, gpio0_41_grp, gpio0_42_grp,
|
||||
gpio0_43_grp, gpio0_44_grp, gpio0_45_grp,
|
||||
gpio0_46_grp, gpio0_47_grp, gpio0_48_grp,
|
||||
gpio0_49_grp, gpio0_50_grp, gpio0_51_grp,
|
||||
gpio0_52_grp, gpio0_53_grp, gpio0_54_grp,
|
||||
gpio0_55_grp, gpio0_56_grp, gpio0_57_grp,
|
||||
gpio0_58_grp, gpio0_59_grp, gpio0_60_grp,
|
||||
gpio0_61_grp, gpio0_62_grp, gpio0_63_grp,
|
||||
gpio0_64_grp, gpio0_65_grp, gpio0_66_grp,
|
||||
gpio0_67_grp, gpio0_68_grp, gpio0_69_grp,
|
||||
gpio0_70_grp, gpio0_71_grp, gpio0_72_grp,
|
||||
gpio0_73_grp, gpio0_74_grp, gpio0_75_grp,
|
||||
gpio0_76_grp, gpio0_77_grp, usb0_0_grp,
|
||||
usb1_0_grp, pmu0_0_grp, pmu0_1_grp,
|
||||
pmu0_2_grp, pmu0_3_grp, pmu0_4_grp,
|
||||
pmu0_5_grp, pmu0_6_grp, pmu0_7_grp,
|
||||
pmu0_8_grp, pmu0_9_grp, pmu0_10_grp,
|
||||
pmu0_11_grp, pcie0_0_grp, pcie0_1_grp,
|
||||
pcie0_2_grp, pcie0_3_grp, pcie0_4_grp,
|
||||
pcie0_5_grp, pcie0_6_grp, pcie0_7_grp,
|
||||
csu0_0_grp, csu0_1_grp, csu0_2_grp,
|
||||
csu0_3_grp, csu0_4_grp, csu0_5_grp,
|
||||
csu0_6_grp, csu0_7_grp, csu0_8_grp,
|
||||
csu0_9_grp, csu0_10_grp, csu0_11_grp,
|
||||
dpaux0_0_grp, dpaux0_1_grp, dpaux0_2_grp,
|
||||
dpaux0_3_grp, pjtag0_0_grp, pjtag0_1_grp,
|
||||
pjtag0_2_grp, pjtag0_3_grp, pjtag0_4_grp,
|
||||
pjtag0_5_grp, trace0_0_grp, trace0_clk_0_grp,
|
||||
trace0_1_grp, trace0_clk_1_grp, trace0_2_grp,
|
||||
trace0_clk_2_grp, testscan0_0_grp]
|
||||
anyOf:
|
||||
- pattern: '^MIO([0-9]|[1-6][0-9]|7[0-7])$'
|
||||
- enum: [ethernet0_0_grp, ethernet1_0_grp, ethernet2_0_grp,
|
||||
ethernet3_0_grp, gemtsu0_0_grp, gemtsu0_1_grp,
|
||||
gemtsu0_2_grp, mdio0_0_grp, mdio1_0_grp,
|
||||
mdio1_1_grp, mdio2_0_grp, mdio3_0_grp,
|
||||
qspi0_0_grp, qspi_ss_0_grp, qspi_fbclk_0_grp,
|
||||
spi0_0_grp, spi0_ss_0_grp, spi0_ss_1_grp,
|
||||
spi0_ss_2_grp, spi0_1_grp, spi0_ss_3_grp,
|
||||
spi0_ss_4_grp, spi0_ss_5_grp, spi0_2_grp,
|
||||
spi0_ss_6_grp, spi0_ss_7_grp, spi0_ss_8_grp,
|
||||
spi0_3_grp, spi0_ss_9_grp, spi0_ss_10_grp,
|
||||
spi0_ss_11_grp, spi0_4_grp, spi0_ss_12_grp,
|
||||
spi0_ss_13_grp, spi0_ss_14_grp, spi0_5_grp,
|
||||
spi0_ss_15_grp, spi0_ss_16_grp, spi0_ss_17_grp,
|
||||
spi1_0_grp, spi1_ss_0_grp, spi1_ss_1_grp,
|
||||
spi1_ss_2_grp, spi1_1_grp, spi1_ss_3_grp,
|
||||
spi1_ss_4_grp, spi1_ss_5_grp, spi1_2_grp,
|
||||
spi1_ss_6_grp, spi1_ss_7_grp, spi1_ss_8_grp,
|
||||
spi1_3_grp, spi1_ss_9_grp, spi1_ss_10_grp,
|
||||
spi1_ss_11_grp, spi1_4_grp, spi1_ss_12_grp,
|
||||
spi1_ss_13_grp, spi1_ss_14_grp, spi1_5_grp,
|
||||
spi1_ss_15_grp, spi1_ss_16_grp, spi1_ss_17_grp,
|
||||
sdio0_0_grp, sdio0_1_grp, sdio0_2_grp,
|
||||
sdio0_3_grp, sdio0_4_grp, sdio0_5_grp,
|
||||
sdio0_6_grp, sdio0_7_grp, sdio0_8_grp,
|
||||
sdio0_9_grp, sdio0_10_grp, sdio0_11_grp,
|
||||
sdio0_12_grp, sdio0_13_grp, sdio0_14_grp,
|
||||
sdio0_15_grp, sdio0_16_grp, sdio0_17_grp,
|
||||
sdio0_18_grp, sdio0_19_grp, sdio0_20_grp,
|
||||
sdio0_21_grp, sdio0_22_grp, sdio0_23_grp,
|
||||
sdio0_24_grp, sdio0_25_grp, sdio0_26_grp,
|
||||
sdio0_27_grp, sdio0_28_grp, sdio0_29_grp,
|
||||
sdio0_30_grp, sdio0_31_grp, sdio0_32_grp,
|
||||
sdio0_pc_0_grp, sdio0_cd_0_grp, sdio0_wp_0_grp,
|
||||
sdio0_pc_1_grp, sdio0_cd_1_grp, sdio0_wp_1_grp,
|
||||
sdio0_pc_2_grp, sdio0_cd_2_grp, sdio0_wp_2_grp,
|
||||
sdio1_0_grp, sdio1_1_grp, sdio1_2_grp,
|
||||
sdio1_3_grp, sdio1_4_grp, sdio1_5_grp,
|
||||
sdio1_6_grp, sdio1_7_grp, sdio1_8_grp,
|
||||
sdio1_9_grp, sdio1_10_grp, sdio1_11_grp,
|
||||
sdio1_12_grp, sdio1_13_grp, sdio1_14_grp,
|
||||
sdio1_15_grp, sdio1_pc_0_grp, sdio1_cd_0_grp,
|
||||
sdio1_wp_0_grp, sdio1_pc_1_grp, sdio1_cd_1_grp,
|
||||
sdio1_wp_1_grp, nand0_0_grp, nand0_ce_0_grp,
|
||||
nand0_rb_0_grp, nand0_dqs_0_grp, nand0_ce_1_grp,
|
||||
nand0_rb_1_grp, nand0_dqs_1_grp, can0_0_grp,
|
||||
can0_1_grp, can0_2_grp, can0_3_grp,
|
||||
can0_4_grp, can0_5_grp, can0_6_grp,
|
||||
can0_7_grp, can0_8_grp, can0_9_grp,
|
||||
can0_10_grp, can0_11_grp, can0_12_grp,
|
||||
can0_13_grp, can0_14_grp, can0_15_grp,
|
||||
can0_16_grp, can0_17_grp, can0_18_grp,
|
||||
can1_0_grp, can1_1_grp, can1_2_grp,
|
||||
can1_3_grp, can1_4_grp, can1_5_grp,
|
||||
can1_6_grp, can1_7_grp, can1_8_grp,
|
||||
can1_9_grp, can1_10_grp, can1_11_grp,
|
||||
can1_12_grp, can1_13_grp, can1_14_grp,
|
||||
can1_15_grp, can1_16_grp, can1_17_grp,
|
||||
can1_18_grp, can1_19_grp, uart0_0_grp,
|
||||
uart0_1_grp, uart0_2_grp, uart0_3_grp,
|
||||
uart0_4_grp, uart0_5_grp, uart0_6_grp,
|
||||
uart0_7_grp, uart0_8_grp, uart0_9_grp,
|
||||
uart0_10_grp, uart0_11_grp, uart0_12_grp,
|
||||
uart0_13_grp, uart0_14_grp, uart0_15_grp,
|
||||
uart0_16_grp, uart0_17_grp, uart0_18_grp,
|
||||
uart1_0_grp, uart1_1_grp, uart1_2_grp,
|
||||
uart1_3_grp, uart1_4_grp, uart1_5_grp,
|
||||
uart1_6_grp, uart1_7_grp, uart1_8_grp,
|
||||
uart1_9_grp, uart1_10_grp, uart1_11_grp,
|
||||
uart1_12_grp, uart1_13_grp, uart1_14_grp,
|
||||
uart1_15_grp, uart1_16_grp, uart1_17_grp,
|
||||
uart1_18_grp, i2c0_0_grp, i2c0_1_grp,
|
||||
i2c0_2_grp, i2c0_3_grp, i2c0_4_grp,
|
||||
i2c0_5_grp, i2c0_6_grp, i2c0_7_grp,
|
||||
i2c0_8_grp, i2c0_9_grp, i2c0_10_grp,
|
||||
i2c0_11_grp, i2c0_12_grp, i2c0_13_grp,
|
||||
i2c0_14_grp, i2c0_15_grp, i2c0_16_grp,
|
||||
i2c0_17_grp, i2c0_18_grp, i2c1_0_grp,
|
||||
i2c1_1_grp, i2c1_2_grp, i2c1_3_grp,
|
||||
i2c1_4_grp, i2c1_5_grp, i2c1_6_grp,
|
||||
i2c1_7_grp, i2c1_8_grp, i2c1_9_grp,
|
||||
i2c1_10_grp, i2c1_11_grp, i2c1_12_grp,
|
||||
i2c1_13_grp, i2c1_14_grp, i2c1_15_grp,
|
||||
i2c1_16_grp, i2c1_17_grp, i2c1_18_grp,
|
||||
i2c1_19_grp, ttc0_clk_0_grp, ttc0_wav_0_grp,
|
||||
ttc0_clk_1_grp, ttc0_wav_1_grp, ttc0_clk_2_grp,
|
||||
ttc0_wav_2_grp, ttc0_clk_3_grp, ttc0_wav_3_grp,
|
||||
ttc0_clk_4_grp, ttc0_wav_4_grp, ttc0_clk_5_grp,
|
||||
ttc0_wav_5_grp, ttc0_clk_6_grp, ttc0_wav_6_grp,
|
||||
ttc0_clk_7_grp, ttc0_wav_7_grp, ttc0_clk_8_grp,
|
||||
ttc0_wav_8_grp, ttc1_clk_0_grp, ttc1_wav_0_grp,
|
||||
ttc1_clk_1_grp, ttc1_wav_1_grp, ttc1_clk_2_grp,
|
||||
ttc1_wav_2_grp, ttc1_clk_3_grp, ttc1_wav_3_grp,
|
||||
ttc1_clk_4_grp, ttc1_wav_4_grp, ttc1_clk_5_grp,
|
||||
ttc1_wav_5_grp, ttc1_clk_6_grp, ttc1_wav_6_grp,
|
||||
ttc1_clk_7_grp, ttc1_wav_7_grp, ttc1_clk_8_grp,
|
||||
ttc1_wav_8_grp, ttc2_clk_0_grp, ttc2_wav_0_grp,
|
||||
ttc2_clk_1_grp, ttc2_wav_1_grp, ttc2_clk_2_grp,
|
||||
ttc2_wav_2_grp, ttc2_clk_3_grp, ttc2_wav_3_grp,
|
||||
ttc2_clk_4_grp, ttc2_wav_4_grp, ttc2_clk_5_grp,
|
||||
ttc2_wav_5_grp, ttc2_clk_6_grp, ttc2_wav_6_grp,
|
||||
ttc2_clk_7_grp, ttc2_wav_7_grp, ttc2_clk_8_grp,
|
||||
ttc2_wav_8_grp, ttc3_clk_0_grp, ttc3_wav_0_grp,
|
||||
ttc3_clk_1_grp, ttc3_wav_1_grp, ttc3_clk_2_grp,
|
||||
ttc3_wav_2_grp, ttc3_clk_3_grp, ttc3_wav_3_grp,
|
||||
ttc3_clk_4_grp, ttc3_wav_4_grp, ttc3_clk_5_grp,
|
||||
ttc3_wav_5_grp, ttc3_clk_6_grp, ttc3_wav_6_grp,
|
||||
ttc3_clk_7_grp, ttc3_wav_7_grp, ttc3_clk_8_grp,
|
||||
ttc3_wav_8_grp, swdt0_clk_0_grp, swdt0_rst_0_grp,
|
||||
swdt0_clk_1_grp, swdt0_rst_1_grp, swdt0_clk_2_grp,
|
||||
swdt0_rst_2_grp, swdt0_clk_3_grp, swdt0_rst_3_grp,
|
||||
swdt0_clk_4_grp, swdt0_rst_4_grp, swdt0_clk_5_grp,
|
||||
swdt0_rst_5_grp, swdt0_clk_6_grp, swdt0_rst_6_grp,
|
||||
swdt0_clk_7_grp, swdt0_rst_7_grp, swdt0_clk_8_grp,
|
||||
swdt0_rst_8_grp, swdt0_clk_9_grp, swdt0_rst_9_grp,
|
||||
swdt0_clk_10_grp, swdt0_rst_10_grp, swdt0_clk_11_grp,
|
||||
swdt0_rst_11_grp, swdt0_clk_12_grp, swdt0_rst_12_grp,
|
||||
swdt1_clk_0_grp, swdt1_rst_0_grp, swdt1_clk_1_grp,
|
||||
swdt1_rst_1_grp, swdt1_clk_2_grp, swdt1_rst_2_grp,
|
||||
swdt1_clk_3_grp, swdt1_rst_3_grp, swdt1_clk_4_grp,
|
||||
swdt1_rst_4_grp, swdt1_clk_5_grp, swdt1_rst_5_grp,
|
||||
swdt1_clk_6_grp, swdt1_rst_6_grp, swdt1_clk_7_grp,
|
||||
swdt1_rst_7_grp, swdt1_clk_8_grp, swdt1_rst_8_grp,
|
||||
swdt1_clk_9_grp, swdt1_rst_9_grp, swdt1_clk_10_grp,
|
||||
swdt1_rst_10_grp, swdt1_clk_11_grp, swdt1_rst_11_grp,
|
||||
swdt1_clk_12_grp, swdt1_rst_12_grp, gpio0_0_grp,
|
||||
gpio0_1_grp, gpio0_2_grp, gpio0_3_grp,
|
||||
gpio0_4_grp, gpio0_5_grp, gpio0_6_grp,
|
||||
gpio0_7_grp, gpio0_8_grp, gpio0_9_grp,
|
||||
gpio0_10_grp, gpio0_11_grp, gpio0_12_grp,
|
||||
gpio0_13_grp, gpio0_14_grp, gpio0_15_grp,
|
||||
gpio0_16_grp, gpio0_17_grp, gpio0_18_grp,
|
||||
gpio0_19_grp, gpio0_20_grp, gpio0_21_grp,
|
||||
gpio0_22_grp, gpio0_23_grp, gpio0_24_grp,
|
||||
gpio0_25_grp, gpio0_26_grp, gpio0_27_grp,
|
||||
gpio0_28_grp, gpio0_29_grp, gpio0_30_grp,
|
||||
gpio0_31_grp, gpio0_32_grp, gpio0_33_grp,
|
||||
gpio0_34_grp, gpio0_35_grp, gpio0_36_grp,
|
||||
gpio0_37_grp, gpio0_38_grp, gpio0_39_grp,
|
||||
gpio0_40_grp, gpio0_41_grp, gpio0_42_grp,
|
||||
gpio0_43_grp, gpio0_44_grp, gpio0_45_grp,
|
||||
gpio0_46_grp, gpio0_47_grp, gpio0_48_grp,
|
||||
gpio0_49_grp, gpio0_50_grp, gpio0_51_grp,
|
||||
gpio0_52_grp, gpio0_53_grp, gpio0_54_grp,
|
||||
gpio0_55_grp, gpio0_56_grp, gpio0_57_grp,
|
||||
gpio0_58_grp, gpio0_59_grp, gpio0_60_grp,
|
||||
gpio0_61_grp, gpio0_62_grp, gpio0_63_grp,
|
||||
gpio0_64_grp, gpio0_65_grp, gpio0_66_grp,
|
||||
gpio0_67_grp, gpio0_68_grp, gpio0_69_grp,
|
||||
gpio0_70_grp, gpio0_71_grp, gpio0_72_grp,
|
||||
gpio0_73_grp, gpio0_74_grp, gpio0_75_grp,
|
||||
gpio0_76_grp, gpio0_77_grp, usb0_0_grp,
|
||||
usb1_0_grp, pmu0_0_grp, pmu0_1_grp,
|
||||
pmu0_2_grp, pmu0_3_grp, pmu0_4_grp,
|
||||
pmu0_5_grp, pmu0_6_grp, pmu0_7_grp,
|
||||
pmu0_8_grp, pmu0_9_grp, pmu0_10_grp,
|
||||
pmu0_11_grp, pcie0_0_grp, pcie0_1_grp,
|
||||
pcie0_2_grp, pcie0_3_grp, pcie0_4_grp,
|
||||
pcie0_5_grp, pcie0_6_grp, pcie0_7_grp,
|
||||
csu0_0_grp, csu0_1_grp, csu0_2_grp,
|
||||
csu0_3_grp, csu0_4_grp, csu0_5_grp,
|
||||
csu0_6_grp, csu0_7_grp, csu0_8_grp,
|
||||
csu0_9_grp, csu0_10_grp, csu0_11_grp,
|
||||
dpaux0_0_grp, dpaux0_1_grp, dpaux0_2_grp,
|
||||
dpaux0_3_grp, pjtag0_0_grp, pjtag0_1_grp,
|
||||
pjtag0_2_grp, pjtag0_3_grp, pjtag0_4_grp,
|
||||
pjtag0_5_grp, trace0_0_grp, trace0_clk_0_grp,
|
||||
trace0_1_grp, trace0_clk_1_grp, trace0_2_grp,
|
||||
trace0_clk_2_grp, testscan0_0_grp]
|
||||
maxItems: 78
|
||||
|
||||
function:
|
||||
@ -230,9 +238,12 @@ patternProperties:
|
||||
pcie0, csu0, dpaux0, pjtag0, trace0, trace0_clk, testscan0]
|
||||
|
||||
required:
|
||||
- groups
|
||||
- function
|
||||
|
||||
oneOf:
|
||||
- required: [ groups ]
|
||||
- required: [ pins ]
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
'^conf':
|
||||
|
||||
@ -18,6 +18,7 @@ properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: nuvoton,ma35d1-reset
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -37,7 +38,7 @@ examples:
|
||||
- |
|
||||
|
||||
system-management@40460000 {
|
||||
compatible = "nuvoton,ma35d1-reset";
|
||||
compatible = "nuvoton,ma35d1-reset", "syscon";
|
||||
reg = <0x40460000 0x200>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
@ -249,7 +249,9 @@ PIN_DECL_2(E26, GPIOD3, RGMII3RXD3, RMII3RXER);
|
||||
|
||||
FUNC_GROUP_DECL(RGMII3, H24, J22, H22, H23, G22, F22, G23, G24, F23, F26, F25,
|
||||
E26);
|
||||
FUNC_GROUP_DECL(RMII3, H24, J22, H22, H23, G23, F23, F26, F25, E26);
|
||||
GROUP_DECL(RMII3, H24, J22, H22, H23, G23, F23, F26, F25, E26);
|
||||
GROUP_DECL(NCSI3, J22, H22, H23, G23, F23, F26, F25, E26);
|
||||
FUNC_DECL_2(RMII3, RMII3, NCSI3);
|
||||
|
||||
#define F24 28
|
||||
SIG_EXPR_LIST_DECL_SESG(F24, NCTS3, NCTS3, SIG_DESC_SET(SCU410, 28));
|
||||
@ -355,7 +357,9 @@ FUNC_GROUP_DECL(NRTS4, B24);
|
||||
|
||||
FUNC_GROUP_DECL(RGMII4, F24, E23, E24, E25, D26, D24, C25, C26, C24, B26, B25,
|
||||
B24);
|
||||
FUNC_GROUP_DECL(RMII4, F24, E23, E24, E25, C25, C24, B26, B25, B24);
|
||||
GROUP_DECL(RMII4, F24, E23, E24, E25, C25, C24, B26, B25, B24);
|
||||
GROUP_DECL(NCSI4, E23, E24, E25, C25, C24, B26, B25, B24);
|
||||
FUNC_DECL_2(RMII4, RMII4, NCSI4);
|
||||
|
||||
#define D22 40
|
||||
SIG_EXPR_LIST_DECL_SESG(D22, SD1CLK, SD1, SIG_DESC_SET(SCU414, 8));
|
||||
@ -1977,6 +1981,8 @@ static const struct aspeed_pin_group aspeed_g6_groups[] = {
|
||||
ASPEED_PINCTRL_GROUP(MDIO2),
|
||||
ASPEED_PINCTRL_GROUP(MDIO3),
|
||||
ASPEED_PINCTRL_GROUP(MDIO4),
|
||||
ASPEED_PINCTRL_GROUP(NCSI3),
|
||||
ASPEED_PINCTRL_GROUP(NCSI4),
|
||||
ASPEED_PINCTRL_GROUP(NCTS1),
|
||||
ASPEED_PINCTRL_GROUP(NCTS2),
|
||||
ASPEED_PINCTRL_GROUP(NCTS3),
|
||||
|
||||
@ -34,6 +34,7 @@
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/string_choices.h>
|
||||
#include <linux/types.h>
|
||||
#include <dt-bindings/pinctrl/bcm2835.h>
|
||||
|
||||
@ -752,7 +753,7 @@ static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
|
||||
int irq = irq_find_mapping(chip->irq.domain, offset);
|
||||
|
||||
seq_printf(s, "function %s in %s; irq %d (%s)",
|
||||
fname, value ? "hi" : "lo",
|
||||
fname, str_hi_lo(value),
|
||||
irq, irq_type_names[pc->irq_type[offset]]);
|
||||
}
|
||||
|
||||
@ -1428,7 +1429,7 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
dev_info(dev, "GPIO_OUT persistence: %s\n",
|
||||
persist_gpio_outputs ? "yes" : "no");
|
||||
str_yes_no(persist_gpio_outputs));
|
||||
|
||||
return 0;
|
||||
|
||||
|
||||
@ -559,5 +559,6 @@ static struct platform_driver bcm4908_pinctrl_driver = {
|
||||
module_platform_driver(bcm4908_pinctrl_driver);
|
||||
|
||||
MODULE_AUTHOR("Rafał Miłecki");
|
||||
MODULE_DESCRIPTION("Broadcom BCM4908 pinmux driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DEVICE_TABLE(of, bcm4908_pinctrl_of_match_table);
|
||||
|
||||
@ -67,7 +67,6 @@ int bcm63xx_pinctrl_probe(struct platform_device *pdev,
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct bcm63xx_pinctrl *pc;
|
||||
struct device_node *node;
|
||||
int err;
|
||||
|
||||
pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
|
||||
@ -94,12 +93,11 @@ int bcm63xx_pinctrl_probe(struct platform_device *pdev,
|
||||
if (IS_ERR(pc->pctl_dev))
|
||||
return PTR_ERR(pc->pctl_dev);
|
||||
|
||||
for_each_child_of_node(dev->parent->of_node, node) {
|
||||
for_each_child_of_node_scoped(dev->parent->of_node, node) {
|
||||
if (of_match_node(bcm63xx_gpio_of_match, node)) {
|
||||
err = bcm63xx_gpio_probe(dev, node, soc, pc);
|
||||
if (err) {
|
||||
dev_err(dev, "could not add GPIO chip\n");
|
||||
of_node_put(node);
|
||||
return err;
|
||||
}
|
||||
}
|
||||
|
||||
@ -27,7 +27,7 @@ struct berlin_pinctrl {
|
||||
struct regmap *regmap;
|
||||
struct device *dev;
|
||||
const struct berlin_pinctrl_desc *desc;
|
||||
struct berlin_pinctrl_function *functions;
|
||||
struct pinfunction *functions;
|
||||
unsigned nfunctions;
|
||||
struct pinctrl_dev *pctrl_dev;
|
||||
};
|
||||
@ -120,12 +120,12 @@ static const char *berlin_pinmux_get_function_name(struct pinctrl_dev *pctrl_dev
|
||||
static int berlin_pinmux_get_function_groups(struct pinctrl_dev *pctrl_dev,
|
||||
unsigned function,
|
||||
const char * const **groups,
|
||||
unsigned * const num_groups)
|
||||
unsigned * const ngroups)
|
||||
{
|
||||
struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
|
||||
|
||||
*groups = pctrl->functions[function].groups;
|
||||
*num_groups = pctrl->functions[function].ngroups;
|
||||
*ngroups = pctrl->functions[function].ngroups;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -153,7 +153,7 @@ static int berlin_pinmux_set(struct pinctrl_dev *pctrl_dev,
|
||||
{
|
||||
struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
|
||||
const struct berlin_desc_group *group_desc = pctrl->desc->groups + group;
|
||||
struct berlin_pinctrl_function *func = pctrl->functions + function;
|
||||
struct pinfunction *func = pctrl->functions + function;
|
||||
struct berlin_desc_function *function_desc =
|
||||
berlin_pinctrl_find_function_by_name(pctrl, group_desc,
|
||||
func->name);
|
||||
@ -180,7 +180,7 @@ static const struct pinmux_ops berlin_pinmux_ops = {
|
||||
static int berlin_pinctrl_add_function(struct berlin_pinctrl *pctrl,
|
||||
const char *name)
|
||||
{
|
||||
struct berlin_pinctrl_function *function = pctrl->functions;
|
||||
struct pinfunction *function = pctrl->functions;
|
||||
|
||||
while (function->name) {
|
||||
if (!strcmp(function->name, name)) {
|
||||
@ -214,8 +214,7 @@ static int berlin_pinctrl_build_state(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
/* we will reallocate later */
|
||||
pctrl->functions = kcalloc(max_functions,
|
||||
sizeof(*pctrl->functions), GFP_KERNEL);
|
||||
pctrl->functions = kcalloc(max_functions, sizeof(*pctrl->functions), GFP_KERNEL);
|
||||
if (!pctrl->functions)
|
||||
return -ENOMEM;
|
||||
|
||||
@ -242,8 +241,7 @@ static int berlin_pinctrl_build_state(struct platform_device *pdev)
|
||||
desc_function = desc_group->functions;
|
||||
|
||||
while (desc_function->name) {
|
||||
struct berlin_pinctrl_function
|
||||
*function = pctrl->functions;
|
||||
struct pinfunction *function = pctrl->functions;
|
||||
const char **groups;
|
||||
bool found = false;
|
||||
|
||||
@ -264,16 +262,15 @@ static int berlin_pinctrl_build_state(struct platform_device *pdev)
|
||||
function->groups =
|
||||
devm_kcalloc(&pdev->dev,
|
||||
function->ngroups,
|
||||
sizeof(char *),
|
||||
sizeof(*function->groups),
|
||||
GFP_KERNEL);
|
||||
|
||||
if (!function->groups) {
|
||||
kfree(pctrl->functions);
|
||||
return -ENOMEM;
|
||||
}
|
||||
}
|
||||
|
||||
groups = function->groups;
|
||||
groups = (const char **)function->groups;
|
||||
while (*groups)
|
||||
groups++;
|
||||
|
||||
|
||||
@ -28,12 +28,6 @@ struct berlin_pinctrl_desc {
|
||||
unsigned ngroups;
|
||||
};
|
||||
|
||||
struct berlin_pinctrl_function {
|
||||
const char *name;
|
||||
const char **groups;
|
||||
unsigned ngroups;
|
||||
};
|
||||
|
||||
#define BERLIN_PINCTRL_GROUP(_name, _offset, _width, _lsb, ...) \
|
||||
{ \
|
||||
.name = _name, \
|
||||
|
||||
@ -1670,13 +1670,23 @@ static int pinctrl_pins_show(struct seq_file *s, void *what)
|
||||
seq_printf(s, "pin %d (%s) ", pin, desc->name);
|
||||
|
||||
#ifdef CONFIG_GPIOLIB
|
||||
gdev = NULL;
|
||||
gpio_num = -1;
|
||||
list_for_each_entry(range, &pctldev->gpio_ranges, node) {
|
||||
if ((pin >= range->pin_base) &&
|
||||
(pin < (range->pin_base + range->npins))) {
|
||||
gpio_num = range->base + (pin - range->pin_base);
|
||||
break;
|
||||
if (range->pins != NULL) {
|
||||
for (int i = 0; i < range->npins; ++i) {
|
||||
if (range->pins[i] == pin) {
|
||||
gpio_num = range->base + i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
} else if ((pin >= range->pin_base) &&
|
||||
(pin < (range->pin_base + range->npins))) {
|
||||
gpio_num =
|
||||
range->base + (pin - range->pin_base);
|
||||
}
|
||||
if (gpio_num != -1)
|
||||
break;
|
||||
}
|
||||
if (gpio_num >= 0)
|
||||
/*
|
||||
@ -2080,6 +2090,14 @@ out_err:
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
static void pinctrl_uninit_controller(struct pinctrl_dev *pctldev, struct pinctrl_desc *pctldesc)
|
||||
{
|
||||
pinctrl_free_pindescs(pctldev, pctldesc->pins,
|
||||
pctldesc->npins);
|
||||
mutex_destroy(&pctldev->mutex);
|
||||
kfree(pctldev);
|
||||
}
|
||||
|
||||
static int pinctrl_claim_hogs(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
pctldev->p = create_pinctrl(pctldev->dev, pctldev);
|
||||
@ -2160,8 +2178,10 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
|
||||
return pctldev;
|
||||
|
||||
error = pinctrl_enable(pctldev);
|
||||
if (error)
|
||||
if (error) {
|
||||
pinctrl_uninit_controller(pctldev, pctldesc);
|
||||
return ERR_PTR(error);
|
||||
}
|
||||
|
||||
return pctldev;
|
||||
}
|
||||
|
||||
@ -206,7 +206,7 @@ struct group_desc {
|
||||
void *data;
|
||||
};
|
||||
|
||||
/* Convenience macro to define a generic pin group descriptor */
|
||||
/* Convenient macro to define a generic pin group descriptor */
|
||||
#define PINCTRL_GROUP_DESC(_name, _pins, _num_pins, _data) \
|
||||
(struct group_desc) { \
|
||||
.grp = PINCTRL_PINGROUP(_name, _pins, _num_pins), \
|
||||
|
||||
@ -7,6 +7,17 @@ config PINCTRL_IMX
|
||||
select PINCONF
|
||||
select REGMAP
|
||||
|
||||
config PINCTRL_IMX_SCMI
|
||||
tristate "i.MX95 pinctrl driver using SCMI protocol interface"
|
||||
depends on ARM_SCMI_PROTOCOL && OF || COMPILE_TEST
|
||||
select PINMUX
|
||||
select GENERIC_PINCONF
|
||||
select GENERIC_PINCTRL_GROUPS
|
||||
select GENERIC_PINMUX_FUNCTIONS
|
||||
help
|
||||
i.MX95 SCMI firmware provides pinctrl protocol. This driver
|
||||
utilizes the SCMI interface to do pinctrl configuration.
|
||||
|
||||
config PINCTRL_IMX_SCU
|
||||
tristate
|
||||
depends on IMX_SCU
|
||||
@ -184,6 +195,13 @@ config PINCTRL_IMXRT1050
|
||||
help
|
||||
Say Y here to enable the imxrt1050 pinctrl driver
|
||||
|
||||
config PINCTRL_IMX91
|
||||
tristate "IMX91 pinctrl driver"
|
||||
depends on ARCH_MXC
|
||||
select PINCTRL_IMX
|
||||
help
|
||||
Say Y here to enable the imx91 pinctrl driver
|
||||
|
||||
config PINCTRL_IMX93
|
||||
tristate "IMX93 pinctrl driver"
|
||||
depends on ARCH_MXC
|
||||
|
||||
@ -2,6 +2,7 @@
|
||||
# Freescale pin control drivers
|
||||
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
|
||||
obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o
|
||||
obj-$(CONFIG_PINCTRL_IMX_SCMI) += pinctrl-imx-scmi.o
|
||||
obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
|
||||
obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o
|
||||
obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
|
||||
@ -25,6 +26,7 @@ obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o
|
||||
obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
|
||||
obj-$(CONFIG_PINCTRL_IMX8DXL) += pinctrl-imx8dxl.o
|
||||
obj-$(CONFIG_PINCTRL_IMX8ULP) += pinctrl-imx8ulp.o
|
||||
obj-$(CONFIG_PINCTRL_IMX91) += pinctrl-imx91.o
|
||||
obj-$(CONFIG_PINCTRL_IMX93) += pinctrl-imx93.o
|
||||
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
|
||||
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
|
||||
|
||||
357
drivers/pinctrl/freescale/pinctrl-imx-scmi.c
Normal file
357
drivers/pinctrl/freescale/pinctrl-imx-scmi.c
Normal file
@ -0,0 +1,357 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* System Control and Power Interface (SCMI) Protocol based i.MX pinctrl driver
|
||||
*
|
||||
* Copyright 2024 NXP
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/scmi_protocol.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/pinctrl/pinconf.h>
|
||||
#include <linux/pinctrl/pinconf-generic.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/pinctrl/pinmux.h>
|
||||
|
||||
#include "../pinctrl-utils.h"
|
||||
#include "../core.h"
|
||||
#include "../pinconf.h"
|
||||
#include "../pinmux.h"
|
||||
|
||||
#define DRV_NAME "scmi-pinctrl-imx"
|
||||
|
||||
struct scmi_pinctrl_imx {
|
||||
struct device *dev;
|
||||
struct scmi_protocol_handle *ph;
|
||||
struct pinctrl_dev *pctldev;
|
||||
struct pinctrl_desc pctl_desc;
|
||||
const struct scmi_pinctrl_proto_ops *ops;
|
||||
};
|
||||
|
||||
/* SCMI pin control types, aligned with SCMI firmware */
|
||||
#define IMX_SCMI_NUM_CFG 4
|
||||
#define IMX_SCMI_PIN_MUX 192
|
||||
#define IMX_SCMI_PIN_CONFIG 193
|
||||
#define IMX_SCMI_PIN_DAISY_ID 194
|
||||
#define IMX_SCMI_PIN_DAISY_CFG 195
|
||||
|
||||
#define IMX_SCMI_NO_PAD_CTL BIT(31)
|
||||
#define IMX_SCMI_PAD_SION BIT(30)
|
||||
#define IMX_SCMI_IOMUXC_CONFIG_SION BIT(4)
|
||||
|
||||
#define IMX_SCMI_PIN_SIZE 24
|
||||
|
||||
#define IMX95_DAISY_OFF 0x408
|
||||
|
||||
static int pinctrl_scmi_imx_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
struct device_node *np,
|
||||
struct pinctrl_map **map,
|
||||
unsigned int *num_maps)
|
||||
{
|
||||
struct pinctrl_map *new_map;
|
||||
const __be32 *list;
|
||||
unsigned long *configs = NULL;
|
||||
unsigned long cfg[IMX_SCMI_NUM_CFG];
|
||||
int map_num, size, pin_size, pin_id, num_pins;
|
||||
int mux_reg, conf_reg, input_reg, mux_val, conf_val, input_val;
|
||||
int i, j;
|
||||
uint32_t ncfg;
|
||||
static uint32_t daisy_off;
|
||||
|
||||
if (!daisy_off) {
|
||||
if (of_machine_is_compatible("fsl,imx95")) {
|
||||
daisy_off = IMX95_DAISY_OFF;
|
||||
} else {
|
||||
dev_err(pctldev->dev, "platform not support scmi pinctrl\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
list = of_get_property(np, "fsl,pins", &size);
|
||||
if (!list) {
|
||||
dev_err(pctldev->dev, "no fsl,pins property in node %pOF\n", np);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pin_size = IMX_SCMI_PIN_SIZE;
|
||||
|
||||
if (!size || size % pin_size) {
|
||||
dev_err(pctldev->dev, "Invalid fsl,pins or pins property in node %pOF\n", np);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
num_pins = size / pin_size;
|
||||
map_num = num_pins;
|
||||
|
||||
new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map),
|
||||
GFP_KERNEL);
|
||||
if (!new_map)
|
||||
return -ENOMEM;
|
||||
|
||||
*map = new_map;
|
||||
*num_maps = map_num;
|
||||
|
||||
/* create config map */
|
||||
for (i = 0; i < num_pins; i++) {
|
||||
j = 0;
|
||||
ncfg = IMX_SCMI_NUM_CFG;
|
||||
mux_reg = be32_to_cpu(*list++);
|
||||
conf_reg = be32_to_cpu(*list++);
|
||||
input_reg = be32_to_cpu(*list++);
|
||||
mux_val = be32_to_cpu(*list++);
|
||||
input_val = be32_to_cpu(*list++);
|
||||
conf_val = be32_to_cpu(*list++);
|
||||
if (conf_val & IMX_SCMI_PAD_SION)
|
||||
mux_val |= IMX_SCMI_IOMUXC_CONFIG_SION;
|
||||
|
||||
pin_id = mux_reg / 4;
|
||||
|
||||
cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_MUX, mux_val);
|
||||
|
||||
if (!conf_reg || (conf_val & IMX_SCMI_NO_PAD_CTL))
|
||||
ncfg--;
|
||||
else
|
||||
cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_CONFIG, conf_val);
|
||||
|
||||
if (!input_reg) {
|
||||
ncfg -= 2;
|
||||
} else {
|
||||
cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_DAISY_ID,
|
||||
(input_reg - daisy_off) / 4);
|
||||
cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_DAISY_CFG, input_val);
|
||||
}
|
||||
|
||||
configs = kmemdup(cfg, ncfg * sizeof(unsigned long), GFP_KERNEL);
|
||||
|
||||
new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
|
||||
new_map[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_id);
|
||||
new_map[i].data.configs.configs = configs;
|
||||
new_map[i].data.configs.num_configs = ncfg;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void pinctrl_scmi_imx_dt_free_map(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_map *map, unsigned int num_maps)
|
||||
{
|
||||
kfree(map);
|
||||
}
|
||||
|
||||
static const struct pinctrl_ops pinctrl_scmi_imx_pinctrl_ops = {
|
||||
.get_groups_count = pinctrl_generic_get_group_count,
|
||||
.get_group_name = pinctrl_generic_get_group_name,
|
||||
.get_group_pins = pinctrl_generic_get_group_pins,
|
||||
.dt_node_to_map = pinctrl_scmi_imx_dt_node_to_map,
|
||||
.dt_free_map = pinctrl_scmi_imx_dt_free_map,
|
||||
};
|
||||
|
||||
static int pinctrl_scmi_imx_func_set_mux(struct pinctrl_dev *pctldev,
|
||||
unsigned int selector, unsigned int group)
|
||||
{
|
||||
/*
|
||||
* For i.MX SCMI PINCTRL , postpone the mux setting
|
||||
* until config is set as they can be set together
|
||||
* in one IPC call
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct pinmux_ops pinctrl_scmi_imx_pinmux_ops = {
|
||||
.get_functions_count = pinmux_generic_get_function_count,
|
||||
.get_function_name = pinmux_generic_get_function_name,
|
||||
.get_function_groups = pinmux_generic_get_function_groups,
|
||||
.set_mux = pinctrl_scmi_imx_func_set_mux,
|
||||
};
|
||||
|
||||
static int pinctrl_scmi_imx_pinconf_get(struct pinctrl_dev *pctldev,
|
||||
unsigned int pin, unsigned long *config)
|
||||
{
|
||||
int ret;
|
||||
struct scmi_pinctrl_imx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
u32 config_type, val;
|
||||
|
||||
if (!config)
|
||||
return -EINVAL;
|
||||
|
||||
config_type = pinconf_to_config_param(*config);
|
||||
|
||||
ret = pmx->ops->settings_get_one(pmx->ph, pin, PIN_TYPE, config_type, &val);
|
||||
/* Convert SCMI error code to PINCTRL expected error code */
|
||||
if (ret == -EOPNOTSUPP)
|
||||
return -ENOTSUPP;
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
*config = pinconf_to_config_packed(config_type, val);
|
||||
|
||||
dev_dbg(pmx->dev, "pin:%s, conf:0x%x", pin_get_name(pctldev, pin), val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pinctrl_scmi_imx_pinconf_set(struct pinctrl_dev *pctldev,
|
||||
unsigned int pin,
|
||||
unsigned long *configs,
|
||||
unsigned int num_configs)
|
||||
{
|
||||
struct scmi_pinctrl_imx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
enum scmi_pinctrl_conf_type config_type[IMX_SCMI_NUM_CFG];
|
||||
u32 config_value[IMX_SCMI_NUM_CFG];
|
||||
enum scmi_pinctrl_conf_type *p_config_type = config_type;
|
||||
u32 *p_config_value = config_value;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
if (!configs || !num_configs)
|
||||
return -EINVAL;
|
||||
|
||||
if (num_configs > IMX_SCMI_NUM_CFG) {
|
||||
dev_err(pmx->dev, "num_configs(%d) too large\n", num_configs);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for (i = 0; i < num_configs; i++) {
|
||||
/* cast to avoid build warning */
|
||||
p_config_type[i] =
|
||||
(enum scmi_pinctrl_conf_type)pinconf_to_config_param(configs[i]);
|
||||
p_config_value[i] = pinconf_to_config_argument(configs[i]);
|
||||
|
||||
dev_dbg(pmx->dev, "pin: %u, type: %u, val: 0x%x\n",
|
||||
pin, p_config_type[i], p_config_value[i]);
|
||||
}
|
||||
|
||||
ret = pmx->ops->settings_conf(pmx->ph, pin, PIN_TYPE, num_configs,
|
||||
p_config_type, p_config_value);
|
||||
if (ret)
|
||||
dev_err(pmx->dev, "Error set config %d\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void pinctrl_scmi_imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
|
||||
struct seq_file *s, unsigned int pin_id)
|
||||
{
|
||||
unsigned long config = pinconf_to_config_packed(IMX_SCMI_PIN_CONFIG, 0);
|
||||
int ret;
|
||||
|
||||
ret = pinctrl_scmi_imx_pinconf_get(pctldev, pin_id, &config);
|
||||
if (ret)
|
||||
config = 0;
|
||||
else
|
||||
config = pinconf_to_config_argument(config);
|
||||
|
||||
seq_printf(s, "0x%lx", config);
|
||||
}
|
||||
|
||||
static const struct pinconf_ops pinctrl_scmi_imx_pinconf_ops = {
|
||||
.pin_config_get = pinctrl_scmi_imx_pinconf_get,
|
||||
.pin_config_set = pinctrl_scmi_imx_pinconf_set,
|
||||
.pin_config_dbg_show = pinctrl_scmi_imx_pinconf_dbg_show,
|
||||
};
|
||||
|
||||
static int
|
||||
scmi_pinctrl_imx_get_pins(struct scmi_pinctrl_imx *pmx, struct pinctrl_desc *desc)
|
||||
{
|
||||
struct pinctrl_pin_desc *pins;
|
||||
unsigned int npins;
|
||||
int ret, i;
|
||||
|
||||
npins = pmx->ops->count_get(pmx->ph, PIN_TYPE);
|
||||
pins = devm_kmalloc_array(pmx->dev, npins, sizeof(*pins), GFP_KERNEL);
|
||||
if (!pins)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < npins; i++) {
|
||||
pins[i].number = i;
|
||||
/* no need free name, firmware driver handles it */
|
||||
ret = pmx->ops->name_get(pmx->ph, i, PIN_TYPE, &pins[i].name);
|
||||
if (ret)
|
||||
return dev_err_probe(pmx->dev, ret,
|
||||
"Can't get name for pin %d", i);
|
||||
}
|
||||
|
||||
desc->npins = npins;
|
||||
desc->pins = pins;
|
||||
dev_dbg(pmx->dev, "got pins %u", npins);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char * const scmi_pinctrl_imx_allowlist[] = {
|
||||
"fsl,imx95",
|
||||
NULL
|
||||
};
|
||||
|
||||
static int scmi_pinctrl_imx_probe(struct scmi_device *sdev)
|
||||
{
|
||||
struct device *dev = &sdev->dev;
|
||||
const struct scmi_handle *handle = sdev->handle;
|
||||
struct scmi_pinctrl_imx *pmx;
|
||||
struct scmi_protocol_handle *ph;
|
||||
const struct scmi_pinctrl_proto_ops *pinctrl_ops;
|
||||
int ret;
|
||||
|
||||
if (!handle)
|
||||
return -EINVAL;
|
||||
|
||||
if (!of_machine_compatible_match(scmi_pinctrl_imx_allowlist))
|
||||
return -ENODEV;
|
||||
|
||||
pinctrl_ops = handle->devm_protocol_get(sdev, SCMI_PROTOCOL_PINCTRL, &ph);
|
||||
if (IS_ERR(pinctrl_ops))
|
||||
return PTR_ERR(pinctrl_ops);
|
||||
|
||||
pmx = devm_kzalloc(dev, sizeof(*pmx), GFP_KERNEL);
|
||||
if (!pmx)
|
||||
return -ENOMEM;
|
||||
|
||||
pmx->ph = ph;
|
||||
pmx->ops = pinctrl_ops;
|
||||
|
||||
pmx->dev = dev;
|
||||
pmx->pctl_desc.name = DRV_NAME;
|
||||
pmx->pctl_desc.owner = THIS_MODULE;
|
||||
pmx->pctl_desc.pctlops = &pinctrl_scmi_imx_pinctrl_ops;
|
||||
pmx->pctl_desc.pmxops = &pinctrl_scmi_imx_pinmux_ops;
|
||||
pmx->pctl_desc.confops = &pinctrl_scmi_imx_pinconf_ops;
|
||||
|
||||
ret = scmi_pinctrl_imx_get_pins(pmx, &pmx->pctl_desc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pmx->dev = &sdev->dev;
|
||||
|
||||
ret = devm_pinctrl_register_and_init(dev, &pmx->pctl_desc, pmx,
|
||||
&pmx->pctldev);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "Failed to register pinctrl\n");
|
||||
|
||||
return pinctrl_enable(pmx->pctldev);
|
||||
}
|
||||
|
||||
static const struct scmi_device_id scmi_id_table[] = {
|
||||
{ SCMI_PROTOCOL_PINCTRL, "pinctrl-imx" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(scmi, scmi_id_table);
|
||||
|
||||
static struct scmi_driver scmi_pinctrl_imx_driver = {
|
||||
.name = DRV_NAME,
|
||||
.probe = scmi_pinctrl_imx_probe,
|
||||
.id_table = scmi_id_table,
|
||||
};
|
||||
module_scmi_driver(scmi_pinctrl_imx_driver);
|
||||
|
||||
MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
|
||||
MODULE_DESCRIPTION("i.MX SCMI pin controller driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
@ -266,7 +266,7 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
|
||||
npins = grp->grp.npins;
|
||||
|
||||
dev_dbg(ipctl->dev, "enable function %s group %s\n",
|
||||
func->name, grp->grp.name);
|
||||
func->func.name, grp->grp.name);
|
||||
|
||||
for (i = 0; i < npins; i++) {
|
||||
/*
|
||||
@ -580,7 +580,6 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
|
||||
u32 index)
|
||||
{
|
||||
struct pinctrl_dev *pctl = ipctl->pctl;
|
||||
struct device_node *child;
|
||||
struct function_desc *func;
|
||||
struct group_desc *grp;
|
||||
const char **group_names;
|
||||
@ -593,29 +592,27 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
|
||||
return -EINVAL;
|
||||
|
||||
/* Initialise function */
|
||||
func->name = np->name;
|
||||
func->num_group_names = of_get_child_count(np);
|
||||
if (func->num_group_names == 0) {
|
||||
func->func.name = np->name;
|
||||
func->func.ngroups = of_get_child_count(np);
|
||||
if (func->func.ngroups == 0) {
|
||||
dev_info(ipctl->dev, "no groups defined in %pOF\n", np);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
group_names = devm_kcalloc(ipctl->dev, func->num_group_names,
|
||||
sizeof(char *), GFP_KERNEL);
|
||||
group_names = devm_kcalloc(ipctl->dev, func->func.ngroups,
|
||||
sizeof(*func->func.groups), GFP_KERNEL);
|
||||
if (!group_names)
|
||||
return -ENOMEM;
|
||||
i = 0;
|
||||
for_each_child_of_node(np, child)
|
||||
for_each_child_of_node_scoped(np, child)
|
||||
group_names[i++] = child->name;
|
||||
func->group_names = group_names;
|
||||
func->func.groups = group_names;
|
||||
|
||||
i = 0;
|
||||
for_each_child_of_node(np, child) {
|
||||
for_each_child_of_node_scoped(np, child) {
|
||||
grp = devm_kzalloc(ipctl->dev, sizeof(*grp), GFP_KERNEL);
|
||||
if (!grp) {
|
||||
of_node_put(child);
|
||||
if (!grp)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
mutex_lock(&ipctl->mutex);
|
||||
radix_tree_insert(&pctl->pin_group_tree,
|
||||
@ -635,21 +632,13 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
|
||||
*/
|
||||
static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np)
|
||||
{
|
||||
struct device_node *function_np;
|
||||
struct device_node *pinctrl_np;
|
||||
|
||||
for_each_child_of_node(np, function_np) {
|
||||
if (of_property_read_bool(function_np, "fsl,pins")) {
|
||||
of_node_put(function_np);
|
||||
for_each_child_of_node_scoped(np, function_np) {
|
||||
if (of_property_read_bool(function_np, "fsl,pins"))
|
||||
return true;
|
||||
}
|
||||
|
||||
for_each_child_of_node(function_np, pinctrl_np) {
|
||||
if (of_property_read_bool(pinctrl_np, "fsl,pins")) {
|
||||
of_node_put(pinctrl_np);
|
||||
of_node_put(function_np);
|
||||
for_each_child_of_node_scoped(function_np, pinctrl_np) {
|
||||
if (of_property_read_bool(pinctrl_np, "fsl,pins"))
|
||||
return false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -508,7 +508,6 @@ static int imx1_pinctrl_parse_functions(struct device_node *np,
|
||||
struct imx1_pinctrl_soc_info *info,
|
||||
u32 index)
|
||||
{
|
||||
struct device_node *child;
|
||||
struct imx1_pmx_func *func;
|
||||
struct imx1_pin_group *grp;
|
||||
int ret;
|
||||
@ -531,14 +530,12 @@ static int imx1_pinctrl_parse_functions(struct device_node *np,
|
||||
if (!func->groups)
|
||||
return -ENOMEM;
|
||||
|
||||
for_each_child_of_node(np, child) {
|
||||
for_each_child_of_node_scoped(np, child) {
|
||||
func->groups[i] = child->name;
|
||||
grp = &info->groups[grp_index++];
|
||||
ret = imx1_pinctrl_parse_groups(child, grp, info, i++);
|
||||
if (ret == -ENOMEM) {
|
||||
of_node_put(child);
|
||||
if (ret == -ENOMEM)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
@ -548,7 +545,6 @@ static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
|
||||
struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct device_node *child;
|
||||
int ret;
|
||||
u32 nfuncs = 0;
|
||||
u32 ngroups = 0;
|
||||
@ -557,7 +553,7 @@ static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
|
||||
if (!np)
|
||||
return -ENODEV;
|
||||
|
||||
for_each_child_of_node(np, child) {
|
||||
for_each_child_of_node_scoped(np, child) {
|
||||
++nfuncs;
|
||||
ngroups += of_get_child_count(child);
|
||||
}
|
||||
@ -579,12 +575,10 @@ static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
|
||||
if (!info->functions || !info->groups)
|
||||
return -ENOMEM;
|
||||
|
||||
for_each_child_of_node(np, child) {
|
||||
for_each_child_of_node_scoped(np, child) {
|
||||
ret = imx1_pinctrl_parse_functions(child, info, ifunc++);
|
||||
if (ret == -ENOMEM) {
|
||||
of_node_put(child);
|
||||
if (ret == -ENOMEM)
|
||||
return -ENOMEM;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
271
drivers/pinctrl/freescale/pinctrl-imx91.c
Normal file
271
drivers/pinctrl/freescale/pinctrl-imx91.c
Normal file
@ -0,0 +1,271 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright 2024 NXP
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "pinctrl-imx.h"
|
||||
|
||||
enum imx91_pads {
|
||||
IMX91_PAD_DAP_TDI = 0,
|
||||
IMX91_PAD_DAP_TMS_SWDIO = 1,
|
||||
IMX91_PAD_DAP_TCLK_SWCLK = 2,
|
||||
IMX91_PAD_DAP_TDO_TRACESWO = 3,
|
||||
IMX91_PAD_GPIO_IO00 = 4,
|
||||
IMX91_PAD_GPIO_IO01 = 5,
|
||||
IMX91_PAD_GPIO_IO02 = 6,
|
||||
IMX91_PAD_GPIO_IO03 = 7,
|
||||
IMX91_PAD_GPIO_IO04 = 8,
|
||||
IMX91_PAD_GPIO_IO05 = 9,
|
||||
IMX91_PAD_GPIO_IO06 = 10,
|
||||
IMX91_PAD_GPIO_IO07 = 11,
|
||||
IMX91_PAD_GPIO_IO08 = 12,
|
||||
IMX91_PAD_GPIO_IO09 = 13,
|
||||
IMX91_PAD_GPIO_IO10 = 14,
|
||||
IMX91_PAD_GPIO_IO11 = 15,
|
||||
IMX91_PAD_GPIO_IO12 = 16,
|
||||
IMX91_PAD_GPIO_IO13 = 17,
|
||||
IMX91_PAD_GPIO_IO14 = 18,
|
||||
IMX91_PAD_GPIO_IO15 = 19,
|
||||
IMX91_PAD_GPIO_IO16 = 20,
|
||||
IMX91_PAD_GPIO_IO17 = 21,
|
||||
IMX91_PAD_GPIO_IO18 = 22,
|
||||
IMX91_PAD_GPIO_IO19 = 23,
|
||||
IMX91_PAD_GPIO_IO20 = 24,
|
||||
IMX91_PAD_GPIO_IO21 = 25,
|
||||
IMX91_PAD_GPIO_IO22 = 26,
|
||||
IMX91_PAD_GPIO_IO23 = 27,
|
||||
IMX91_PAD_GPIO_IO24 = 28,
|
||||
IMX91_PAD_GPIO_IO25 = 29,
|
||||
IMX91_PAD_GPIO_IO26 = 30,
|
||||
IMX91_PAD_GPIO_IO27 = 31,
|
||||
IMX91_PAD_GPIO_IO28 = 32,
|
||||
IMX91_PAD_GPIO_IO29 = 33,
|
||||
IMX91_PAD_CCM_CLKO1 = 34,
|
||||
IMX91_PAD_CCM_CLKO2 = 35,
|
||||
IMX91_PAD_CCM_CLKO3 = 36,
|
||||
IMX91_PAD_CCM_CLKO4 = 37,
|
||||
IMX91_PAD_ENET1_MDC = 38,
|
||||
IMX91_PAD_ENET1_MDIO = 39,
|
||||
IMX91_PAD_ENET1_TD3 = 40,
|
||||
IMX91_PAD_ENET1_TD2 = 41,
|
||||
IMX91_PAD_ENET1_TD1 = 42,
|
||||
IMX91_PAD_ENET1_TD0 = 43,
|
||||
IMX91_PAD_ENET1_TX_CTL = 44,
|
||||
IMX91_PAD_ENET1_TXC = 45,
|
||||
IMX91_PAD_ENET1_RX_CTL = 46,
|
||||
IMX91_PAD_ENET1_RXC = 47,
|
||||
IMX91_PAD_ENET1_RD0 = 48,
|
||||
IMX91_PAD_ENET1_RD1 = 49,
|
||||
IMX91_PAD_ENET1_RD2 = 50,
|
||||
IMX91_PAD_ENET1_RD3 = 51,
|
||||
IMX91_PAD_ENET2_MDC = 52,
|
||||
IMX91_PAD_ENET2_MDIO = 53,
|
||||
IMX91_PAD_ENET2_TD3 = 54,
|
||||
IMX91_PAD_ENET2_TD2 = 55,
|
||||
IMX91_PAD_ENET2_TD1 = 56,
|
||||
IMX91_PAD_ENET2_TD0 = 57,
|
||||
IMX91_PAD_ENET2_TX_CTL = 58,
|
||||
IMX91_PAD_ENET2_TXC = 59,
|
||||
IMX91_PAD_ENET2_RX_CTL = 60,
|
||||
IMX91_PAD_ENET2_RXC = 61,
|
||||
IMX91_PAD_ENET2_RD0 = 62,
|
||||
IMX91_PAD_ENET2_RD1 = 63,
|
||||
IMX91_PAD_ENET2_RD2 = 64,
|
||||
IMX91_PAD_ENET2_RD3 = 65,
|
||||
IMX91_PAD_SD1_CLK = 66,
|
||||
IMX91_PAD_SD1_CMD = 67,
|
||||
IMX91_PAD_SD1_DATA0 = 68,
|
||||
IMX91_PAD_SD1_DATA1 = 69,
|
||||
IMX91_PAD_SD1_DATA2 = 70,
|
||||
IMX91_PAD_SD1_DATA3 = 71,
|
||||
IMX91_PAD_SD1_DATA4 = 72,
|
||||
IMX91_PAD_SD1_DATA5 = 73,
|
||||
IMX91_PAD_SD1_DATA6 = 74,
|
||||
IMX91_PAD_SD1_DATA7 = 75,
|
||||
IMX91_PAD_SD1_STROBE = 76,
|
||||
IMX91_PAD_SD2_VSELECT = 77,
|
||||
IMX91_PAD_SD3_CLK = 78,
|
||||
IMX91_PAD_SD3_CMD = 79,
|
||||
IMX91_PAD_SD3_DATA0 = 80,
|
||||
IMX91_PAD_SD3_DATA1 = 81,
|
||||
IMX91_PAD_SD3_DATA2 = 82,
|
||||
IMX91_PAD_SD3_DATA3 = 83,
|
||||
IMX91_PAD_SD2_CD_B = 84,
|
||||
IMX91_PAD_SD2_CLK = 85,
|
||||
IMX91_PAD_SD2_CMD = 86,
|
||||
IMX91_PAD_SD2_DATA0 = 87,
|
||||
IMX91_PAD_SD2_DATA1 = 88,
|
||||
IMX91_PAD_SD2_DATA2 = 89,
|
||||
IMX91_PAD_SD2_DATA3 = 90,
|
||||
IMX91_PAD_SD2_RESET_B = 91,
|
||||
IMX91_PAD_I2C1_SCL = 92,
|
||||
IMX91_PAD_I2C1_SDA = 93,
|
||||
IMX91_PAD_I2C2_SCL = 94,
|
||||
IMX91_PAD_I2C2_SDA = 95,
|
||||
IMX91_PAD_UART1_RXD = 96,
|
||||
IMX91_PAD_UART1_TXD = 97,
|
||||
IMX91_PAD_UART2_RXD = 98,
|
||||
IMX91_PAD_UART2_TXD = 99,
|
||||
IMX91_PAD_PDM_CLK = 100,
|
||||
IMX91_PAD_PDM_BIT_STREAM0 = 101,
|
||||
IMX91_PAD_PDM_BIT_STREAM1 = 102,
|
||||
IMX91_PAD_SAI1_TXFS = 103,
|
||||
IMX91_PAD_SAI1_TXC = 104,
|
||||
IMX91_PAD_SAI1_TXD0 = 105,
|
||||
IMX91_PAD_SAI1_RXD0 = 106,
|
||||
IMX91_PAD_WDOG_ANY = 107,
|
||||
};
|
||||
|
||||
/* Pad names for the pinmux subsystem */
|
||||
static const struct pinctrl_pin_desc imx91_pinctrl_pads[] = {
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_DAP_TDI),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_DAP_TMS_SWDIO),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_DAP_TCLK_SWCLK),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_DAP_TDO_TRACESWO),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO00),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO01),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO02),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO03),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO04),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO05),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO06),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO07),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO08),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO09),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO10),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO11),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO12),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO13),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO14),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO15),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO16),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO17),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO18),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO19),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO20),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO21),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO22),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO23),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO24),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO25),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO26),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO27),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO28),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO29),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_CCM_CLKO1),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_CCM_CLKO2),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_CCM_CLKO3),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_CCM_CLKO4),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_MDC),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_MDIO),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TD3),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TD2),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TD1),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TD0),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TX_CTL),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TXC),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RX_CTL),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RXC),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RD0),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RD1),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RD2),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RD3),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_MDC),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_MDIO),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TD3),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TD2),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TD1),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TD0),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TX_CTL),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TXC),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RX_CTL),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RXC),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RD0),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RD1),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RD2),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RD3),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD1_CLK),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD1_CMD),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA0),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA1),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA2),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA3),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA4),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA5),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA6),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA7),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD1_STROBE),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD2_VSELECT),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD3_CLK),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD3_CMD),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD3_DATA0),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD3_DATA1),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD3_DATA2),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD3_DATA3),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD2_CD_B),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD2_CLK),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD2_CMD),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD2_DATA0),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD2_DATA1),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD2_DATA2),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD2_DATA3),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SD2_RESET_B),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_I2C1_SCL),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_I2C1_SDA),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_I2C2_SCL),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_I2C2_SDA),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_UART1_RXD),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_UART1_TXD),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_UART2_RXD),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_UART2_TXD),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_PDM_CLK),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_PDM_BIT_STREAM0),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_PDM_BIT_STREAM1),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SAI1_TXFS),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SAI1_TXC),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SAI1_TXD0),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_SAI1_RXD0),
|
||||
IMX_PINCTRL_PIN(IMX91_PAD_WDOG_ANY),
|
||||
};
|
||||
|
||||
static const struct imx_pinctrl_soc_info imx91_pinctrl_info = {
|
||||
.pins = imx91_pinctrl_pads,
|
||||
.npins = ARRAY_SIZE(imx91_pinctrl_pads),
|
||||
.flags = ZERO_OFFSET_VALID,
|
||||
};
|
||||
|
||||
static int imx91_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return imx_pinctrl_probe(pdev, &imx91_pinctrl_info);
|
||||
}
|
||||
|
||||
static const struct of_device_id imx91_pinctrl_of_match[] = {
|
||||
{ .compatible = "fsl,imx91-iomuxc", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, imx91_pinctrl_of_match);
|
||||
|
||||
static struct platform_driver imx91_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "imx91-pinctrl",
|
||||
.of_match_table = imx91_pinctrl_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.probe = imx91_pinctrl_probe,
|
||||
};
|
||||
|
||||
static int __init imx91_pinctrl_init(void)
|
||||
{
|
||||
return platform_driver_register(&imx91_pinctrl_driver);
|
||||
}
|
||||
arch_initcall(imx91_pinctrl_init);
|
||||
|
||||
MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
|
||||
MODULE_DESCRIPTION("NXP i.MX91 pinctrl driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
@ -413,8 +413,8 @@ static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
child = of_get_next_child(np, NULL);
|
||||
if (!child) {
|
||||
val = of_get_child_count(np);
|
||||
if (val == 0) {
|
||||
dev_err(&pdev->dev, "no group is defined\n");
|
||||
return -ENOENT;
|
||||
}
|
||||
@ -490,16 +490,14 @@ static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
|
||||
/* Get groups for each function */
|
||||
idxf = 0;
|
||||
fn = fnull;
|
||||
for_each_child_of_node(np, child) {
|
||||
for_each_child_of_node_scoped(np, child) {
|
||||
if (is_mxs_gpio(child))
|
||||
continue;
|
||||
if (of_property_read_u32(child, "reg", &val)) {
|
||||
ret = mxs_pinctrl_parse_group(pdev, child,
|
||||
idxg++, NULL);
|
||||
if (ret) {
|
||||
of_node_put(child);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
continue;
|
||||
}
|
||||
|
||||
@ -509,19 +507,15 @@ static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
|
||||
f->ngroups,
|
||||
sizeof(*f->groups),
|
||||
GFP_KERNEL);
|
||||
if (!f->groups) {
|
||||
of_node_put(child);
|
||||
if (!f->groups)
|
||||
return -ENOMEM;
|
||||
}
|
||||
fn = child->name;
|
||||
i = 0;
|
||||
}
|
||||
ret = mxs_pinctrl_parse_group(pdev, child, idxg++,
|
||||
&f->groups[i++]);
|
||||
if (ret) {
|
||||
of_node_put(child);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
@ -56,7 +56,7 @@ static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev,
|
||||
return -EINVAL;
|
||||
|
||||
dev_dbg(pctldev->dev, "enable function %s group %s\n",
|
||||
func->name, grp->grp.name);
|
||||
func->func.name, grp->grp.name);
|
||||
|
||||
for (i = 0; i < grp->grp.npins; i++) {
|
||||
const struct mtk_pin_desc *desc;
|
||||
@ -620,12 +620,12 @@ static int mtk_build_functions(struct mtk_pinctrl *hw)
|
||||
int i, err;
|
||||
|
||||
for (i = 0; i < hw->soc->nfuncs ; i++) {
|
||||
const struct function_desc *func = hw->soc->funcs + i;
|
||||
const struct function_desc *function = hw->soc->funcs + i;
|
||||
const struct pinfunction *func = &function->func;
|
||||
|
||||
err = pinmux_generic_add_function(hw->pctrl, func->name,
|
||||
func->group_names,
|
||||
func->num_group_names,
|
||||
func->data);
|
||||
func->groups, func->ngroups,
|
||||
function->data);
|
||||
if (err < 0) {
|
||||
dev_err(hw->dev, "Failed to register function %s\n",
|
||||
func->name);
|
||||
|
||||
@ -43,6 +43,12 @@
|
||||
.data = id##_funcs, \
|
||||
}
|
||||
|
||||
#define PINCTRL_PIN_FUNCTION(_name_, id) \
|
||||
{ \
|
||||
.func = PINCTRL_PINFUNCTION(_name_, id##_groups, ARRAY_SIZE(id##_groups)), \
|
||||
.data = NULL, \
|
||||
}
|
||||
|
||||
int mtk_moore_pinctrl_probe(struct platform_device *pdev,
|
||||
const struct mtk_pin_soc *soc);
|
||||
|
||||
|
||||
@ -823,22 +823,22 @@ static const char *mt7622_uart_groups[] = { "uart0_0_tx_rx",
|
||||
static const char *mt7622_wdt_groups[] = { "watchdog", };
|
||||
|
||||
static const struct function_desc mt7622_functions[] = {
|
||||
{"antsel", mt7622_antsel_groups, ARRAY_SIZE(mt7622_antsel_groups)},
|
||||
{"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)},
|
||||
{"eth", mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)},
|
||||
{"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)},
|
||||
{"i2s", mt7622_i2s_groups, ARRAY_SIZE(mt7622_i2s_groups)},
|
||||
{"ir", mt7622_ir_groups, ARRAY_SIZE(mt7622_ir_groups)},
|
||||
{"led", mt7622_led_groups, ARRAY_SIZE(mt7622_led_groups)},
|
||||
{"flash", mt7622_flash_groups, ARRAY_SIZE(mt7622_flash_groups)},
|
||||
{"pcie", mt7622_pcie_groups, ARRAY_SIZE(mt7622_pcie_groups)},
|
||||
{"pmic", mt7622_pmic_bus_groups, ARRAY_SIZE(mt7622_pmic_bus_groups)},
|
||||
{"pwm", mt7622_pwm_groups, ARRAY_SIZE(mt7622_pwm_groups)},
|
||||
{"sd", mt7622_sd_groups, ARRAY_SIZE(mt7622_sd_groups)},
|
||||
{"spi", mt7622_spic_groups, ARRAY_SIZE(mt7622_spic_groups)},
|
||||
{"tdm", mt7622_tdm_groups, ARRAY_SIZE(mt7622_tdm_groups)},
|
||||
{"uart", mt7622_uart_groups, ARRAY_SIZE(mt7622_uart_groups)},
|
||||
{"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)},
|
||||
PINCTRL_PIN_FUNCTION("antsel", mt7622_antsel),
|
||||
PINCTRL_PIN_FUNCTION("emmc", mt7622_emmc),
|
||||
PINCTRL_PIN_FUNCTION("eth", mt7622_ethernet),
|
||||
PINCTRL_PIN_FUNCTION("i2c", mt7622_i2c),
|
||||
PINCTRL_PIN_FUNCTION("i2s", mt7622_i2s),
|
||||
PINCTRL_PIN_FUNCTION("ir", mt7622_ir),
|
||||
PINCTRL_PIN_FUNCTION("led", mt7622_led),
|
||||
PINCTRL_PIN_FUNCTION("flash", mt7622_flash),
|
||||
PINCTRL_PIN_FUNCTION("pcie", mt7622_pcie),
|
||||
PINCTRL_PIN_FUNCTION("pmic", mt7622_pmic_bus),
|
||||
PINCTRL_PIN_FUNCTION("pwm", mt7622_pwm),
|
||||
PINCTRL_PIN_FUNCTION("sd", mt7622_sd),
|
||||
PINCTRL_PIN_FUNCTION("spi", mt7622_spic),
|
||||
PINCTRL_PIN_FUNCTION("tdm", mt7622_tdm),
|
||||
PINCTRL_PIN_FUNCTION("uart", mt7622_uart),
|
||||
PINCTRL_PIN_FUNCTION("watchdog", mt7622_wdt),
|
||||
};
|
||||
|
||||
static const struct mtk_eint_hw mt7622_eint_hw = {
|
||||
|
||||
@ -1341,27 +1341,27 @@ static const char *mt7623_uart_groups[] = { "uart0_0_txd_rxd",
|
||||
static const char *mt7623_wdt_groups[] = { "watchdog_0", "watchdog_1", };
|
||||
|
||||
static const struct function_desc mt7623_functions[] = {
|
||||
{"audck", mt7623_aud_clk_groups, ARRAY_SIZE(mt7623_aud_clk_groups)},
|
||||
{"disp", mt7623_disp_pwm_groups, ARRAY_SIZE(mt7623_disp_pwm_groups)},
|
||||
{"eth", mt7623_ethernet_groups, ARRAY_SIZE(mt7623_ethernet_groups)},
|
||||
{"sdio", mt7623_ext_sdio_groups, ARRAY_SIZE(mt7623_ext_sdio_groups)},
|
||||
{"hdmi", mt7623_hdmi_groups, ARRAY_SIZE(mt7623_hdmi_groups)},
|
||||
{"i2c", mt7623_i2c_groups, ARRAY_SIZE(mt7623_i2c_groups)},
|
||||
{"i2s", mt7623_i2s_groups, ARRAY_SIZE(mt7623_i2s_groups)},
|
||||
{"ir", mt7623_ir_groups, ARRAY_SIZE(mt7623_ir_groups)},
|
||||
{"lcd", mt7623_lcd_groups, ARRAY_SIZE(mt7623_lcd_groups)},
|
||||
{"msdc", mt7623_msdc_groups, ARRAY_SIZE(mt7623_msdc_groups)},
|
||||
{"nand", mt7623_nandc_groups, ARRAY_SIZE(mt7623_nandc_groups)},
|
||||
{"otg", mt7623_otg_groups, ARRAY_SIZE(mt7623_otg_groups)},
|
||||
{"pcie", mt7623_pcie_groups, ARRAY_SIZE(mt7623_pcie_groups)},
|
||||
{"pcm", mt7623_pcm_groups, ARRAY_SIZE(mt7623_pcm_groups)},
|
||||
{"pwm", mt7623_pwm_groups, ARRAY_SIZE(mt7623_pwm_groups)},
|
||||
{"pwrap", mt7623_pwrap_groups, ARRAY_SIZE(mt7623_pwrap_groups)},
|
||||
{"rtc", mt7623_rtc_groups, ARRAY_SIZE(mt7623_rtc_groups)},
|
||||
{"spi", mt7623_spi_groups, ARRAY_SIZE(mt7623_spi_groups)},
|
||||
{"spdif", mt7623_spdif_groups, ARRAY_SIZE(mt7623_spdif_groups)},
|
||||
{"uart", mt7623_uart_groups, ARRAY_SIZE(mt7623_uart_groups)},
|
||||
{"watchdog", mt7623_wdt_groups, ARRAY_SIZE(mt7623_wdt_groups)},
|
||||
PINCTRL_PIN_FUNCTION("audck", mt7623_aud_clk),
|
||||
PINCTRL_PIN_FUNCTION("disp", mt7623_disp_pwm),
|
||||
PINCTRL_PIN_FUNCTION("eth", mt7623_ethernet),
|
||||
PINCTRL_PIN_FUNCTION("sdio", mt7623_ext_sdio),
|
||||
PINCTRL_PIN_FUNCTION("hdmi", mt7623_hdmi),
|
||||
PINCTRL_PIN_FUNCTION("i2c", mt7623_i2c),
|
||||
PINCTRL_PIN_FUNCTION("i2s", mt7623_i2s),
|
||||
PINCTRL_PIN_FUNCTION("ir", mt7623_ir),
|
||||
PINCTRL_PIN_FUNCTION("lcd", mt7623_lcd),
|
||||
PINCTRL_PIN_FUNCTION("msdc", mt7623_msdc),
|
||||
PINCTRL_PIN_FUNCTION("nand", mt7623_nandc),
|
||||
PINCTRL_PIN_FUNCTION("otg", mt7623_otg),
|
||||
PINCTRL_PIN_FUNCTION("pcie", mt7623_pcie),
|
||||
PINCTRL_PIN_FUNCTION("pcm", mt7623_pcm),
|
||||
PINCTRL_PIN_FUNCTION("pwm", mt7623_pwm),
|
||||
PINCTRL_PIN_FUNCTION("pwrap", mt7623_pwrap),
|
||||
PINCTRL_PIN_FUNCTION("rtc", mt7623_rtc),
|
||||
PINCTRL_PIN_FUNCTION("spi", mt7623_spi),
|
||||
PINCTRL_PIN_FUNCTION("spdif", mt7623_spdif),
|
||||
PINCTRL_PIN_FUNCTION("uart", mt7623_uart),
|
||||
PINCTRL_PIN_FUNCTION("watchdog", mt7623_wdt),
|
||||
};
|
||||
|
||||
static const struct mtk_eint_hw mt7623_eint_hw = {
|
||||
|
||||
@ -385,16 +385,16 @@ static const char *mt7629_wifi_groups[] = { "wf0_5g", "wf0_2g", };
|
||||
static const char *mt7629_flash_groups[] = { "snfi", "spi_nor" };
|
||||
|
||||
static const struct function_desc mt7629_functions[] = {
|
||||
{"eth", mt7629_ethernet_groups, ARRAY_SIZE(mt7629_ethernet_groups)},
|
||||
{"i2c", mt7629_i2c_groups, ARRAY_SIZE(mt7629_i2c_groups)},
|
||||
{"led", mt7629_led_groups, ARRAY_SIZE(mt7629_led_groups)},
|
||||
{"pcie", mt7629_pcie_groups, ARRAY_SIZE(mt7629_pcie_groups)},
|
||||
{"pwm", mt7629_pwm_groups, ARRAY_SIZE(mt7629_pwm_groups)},
|
||||
{"spi", mt7629_spi_groups, ARRAY_SIZE(mt7629_spi_groups)},
|
||||
{"uart", mt7629_uart_groups, ARRAY_SIZE(mt7629_uart_groups)},
|
||||
{"watchdog", mt7629_wdt_groups, ARRAY_SIZE(mt7629_wdt_groups)},
|
||||
{"wifi", mt7629_wifi_groups, ARRAY_SIZE(mt7629_wifi_groups)},
|
||||
{"flash", mt7629_flash_groups, ARRAY_SIZE(mt7629_flash_groups)},
|
||||
PINCTRL_PIN_FUNCTION("eth", mt7629_ethernet),
|
||||
PINCTRL_PIN_FUNCTION("i2c", mt7629_i2c),
|
||||
PINCTRL_PIN_FUNCTION("led", mt7629_led),
|
||||
PINCTRL_PIN_FUNCTION("pcie", mt7629_pcie),
|
||||
PINCTRL_PIN_FUNCTION("pwm", mt7629_pwm),
|
||||
PINCTRL_PIN_FUNCTION("spi", mt7629_spi),
|
||||
PINCTRL_PIN_FUNCTION("uart", mt7629_uart),
|
||||
PINCTRL_PIN_FUNCTION("watchdog", mt7629_wdt),
|
||||
PINCTRL_PIN_FUNCTION("wifi", mt7629_wifi),
|
||||
PINCTRL_PIN_FUNCTION("flash", mt7629_flash),
|
||||
};
|
||||
|
||||
static const struct mtk_eint_hw mt7629_eint_hw = {
|
||||
|
||||
@ -37,36 +37,30 @@
|
||||
|
||||
static struct mtmips_pmx_func pwm1_grp[] = {
|
||||
FUNC("sdxc d6", 3, 19, 1),
|
||||
FUNC("utif", 2, 19, 1),
|
||||
FUNC("gpio", 1, 19, 1),
|
||||
FUNC("pwm1 utif", 2, 19, 1),
|
||||
FUNC("pwm1", 0, 19, 1),
|
||||
};
|
||||
|
||||
static struct mtmips_pmx_func pwm0_grp[] = {
|
||||
FUNC("sdxc d7", 3, 18, 1),
|
||||
FUNC("utif", 2, 18, 1),
|
||||
FUNC("gpio", 1, 18, 1),
|
||||
FUNC("pwm0 utif", 2, 18, 1),
|
||||
FUNC("pwm0", 0, 18, 1),
|
||||
};
|
||||
|
||||
static struct mtmips_pmx_func uart2_grp[] = {
|
||||
FUNC("sdxc d5 d4", 3, 20, 2),
|
||||
FUNC("pwm", 2, 20, 2),
|
||||
FUNC("gpio", 1, 20, 2),
|
||||
FUNC("uart2 pwm", 2, 20, 2),
|
||||
FUNC("uart2", 0, 20, 2),
|
||||
};
|
||||
|
||||
static struct mtmips_pmx_func uart1_grp[] = {
|
||||
FUNC("sw_r", 3, 45, 2),
|
||||
FUNC("pwm", 2, 45, 2),
|
||||
FUNC("gpio", 1, 45, 2),
|
||||
FUNC("uart1 pwm", 2, 45, 2),
|
||||
FUNC("uart1", 0, 45, 2),
|
||||
};
|
||||
|
||||
static struct mtmips_pmx_func i2c_grp[] = {
|
||||
FUNC("-", 3, 4, 2),
|
||||
FUNC("debug", 2, 4, 2),
|
||||
FUNC("gpio", 1, 4, 2),
|
||||
FUNC("i2c", 0, 4, 2),
|
||||
};
|
||||
|
||||
@ -76,128 +70,100 @@ static struct mtmips_pmx_func wdt_grp[] = { FUNC("wdt", 0, 38, 1) };
|
||||
static struct mtmips_pmx_func spi_grp[] = { FUNC("spi", 0, 7, 4) };
|
||||
|
||||
static struct mtmips_pmx_func sd_mode_grp[] = {
|
||||
FUNC("jtag", 3, 22, 8),
|
||||
FUNC("utif", 2, 22, 8),
|
||||
FUNC("gpio", 1, 22, 8),
|
||||
FUNC("sdxc jtag", 3, 22, 8),
|
||||
FUNC("sdxc utif", 2, 22, 8),
|
||||
FUNC("sdxc", 0, 22, 8),
|
||||
};
|
||||
|
||||
static struct mtmips_pmx_func uart0_grp[] = {
|
||||
FUNC("-", 3, 12, 2),
|
||||
FUNC("-", 2, 12, 2),
|
||||
FUNC("gpio", 1, 12, 2),
|
||||
FUNC("uart0", 0, 12, 2),
|
||||
};
|
||||
|
||||
static struct mtmips_pmx_func i2s_grp[] = {
|
||||
FUNC("antenna", 3, 0, 4),
|
||||
FUNC("pcm", 2, 0, 4),
|
||||
FUNC("gpio", 1, 0, 4),
|
||||
FUNC("i2s", 0, 0, 4),
|
||||
};
|
||||
|
||||
static struct mtmips_pmx_func spi_cs1_grp[] = {
|
||||
FUNC("-", 3, 6, 1),
|
||||
FUNC("refclk", 2, 6, 1),
|
||||
FUNC("gpio", 1, 6, 1),
|
||||
FUNC("spi refclk", 2, 6, 1),
|
||||
FUNC("spi cs1", 0, 6, 1),
|
||||
};
|
||||
|
||||
static struct mtmips_pmx_func spis_grp[] = {
|
||||
FUNC("pwm_uart2", 3, 14, 4),
|
||||
FUNC("utif", 2, 14, 4),
|
||||
FUNC("gpio", 1, 14, 4),
|
||||
FUNC("spis utif", 2, 14, 4),
|
||||
FUNC("spis", 0, 14, 4),
|
||||
};
|
||||
|
||||
static struct mtmips_pmx_func gpio_grp[] = {
|
||||
FUNC("pcie", 3, 11, 1),
|
||||
FUNC("refclk", 2, 11, 1),
|
||||
FUNC("gpio", 1, 11, 1),
|
||||
FUNC("gpio", 0, 11, 1),
|
||||
FUNC("gpio refclk", 2, 11, 1),
|
||||
};
|
||||
|
||||
static struct mtmips_pmx_func p4led_kn_grp[] = {
|
||||
FUNC("jtag", 3, 30, 1),
|
||||
FUNC("utif", 2, 30, 1),
|
||||
FUNC("gpio", 1, 30, 1),
|
||||
FUNC("p4led_kn jtag", 3, 30, 1),
|
||||
FUNC("p4led_kn utif", 2, 30, 1),
|
||||
FUNC("p4led_kn", 0, 30, 1),
|
||||
};
|
||||
|
||||
static struct mtmips_pmx_func p3led_kn_grp[] = {
|
||||
FUNC("jtag", 3, 31, 1),
|
||||
FUNC("utif", 2, 31, 1),
|
||||
FUNC("gpio", 1, 31, 1),
|
||||
FUNC("p3led_kn jtag", 3, 31, 1),
|
||||
FUNC("p3led_kn utif", 2, 31, 1),
|
||||
FUNC("p3led_kn", 0, 31, 1),
|
||||
};
|
||||
|
||||
static struct mtmips_pmx_func p2led_kn_grp[] = {
|
||||
FUNC("jtag", 3, 32, 1),
|
||||
FUNC("utif", 2, 32, 1),
|
||||
FUNC("gpio", 1, 32, 1),
|
||||
FUNC("p2led_kn jtag", 3, 32, 1),
|
||||
FUNC("p2led_kn utif", 2, 32, 1),
|
||||
FUNC("p2led_kn", 0, 32, 1),
|
||||
};
|
||||
|
||||
static struct mtmips_pmx_func p1led_kn_grp[] = {
|
||||
FUNC("jtag", 3, 33, 1),
|
||||
FUNC("utif", 2, 33, 1),
|
||||
FUNC("gpio", 1, 33, 1),
|
||||
FUNC("p1led_kn jtag", 3, 33, 1),
|
||||
FUNC("p1led_kn utif", 2, 33, 1),
|
||||
FUNC("p1led_kn", 0, 33, 1),
|
||||
};
|
||||
|
||||
static struct mtmips_pmx_func p0led_kn_grp[] = {
|
||||
FUNC("jtag", 3, 34, 1),
|
||||
FUNC("rsvd", 2, 34, 1),
|
||||
FUNC("gpio", 1, 34, 1),
|
||||
FUNC("p0led_kn jtag", 3, 34, 1),
|
||||
FUNC("p0led_kn", 0, 34, 1),
|
||||
};
|
||||
|
||||
static struct mtmips_pmx_func wled_kn_grp[] = {
|
||||
FUNC("rsvd", 3, 35, 1),
|
||||
FUNC("rsvd", 2, 35, 1),
|
||||
FUNC("gpio", 1, 35, 1),
|
||||
FUNC("wled_kn", 0, 35, 1),
|
||||
};
|
||||
|
||||
static struct mtmips_pmx_func p4led_an_grp[] = {
|
||||
FUNC("jtag", 3, 39, 1),
|
||||
FUNC("utif", 2, 39, 1),
|
||||
FUNC("gpio", 1, 39, 1),
|
||||
FUNC("p4led_an jtag", 3, 39, 1),
|
||||
FUNC("p4led_an utif", 2, 39, 1),
|
||||
FUNC("p4led_an", 0, 39, 1),
|
||||
};
|
||||
|
||||
static struct mtmips_pmx_func p3led_an_grp[] = {
|
||||
FUNC("jtag", 3, 40, 1),
|
||||
FUNC("utif", 2, 40, 1),
|
||||
FUNC("gpio", 1, 40, 1),
|
||||
FUNC("p3led_an jtag", 3, 40, 1),
|
||||
FUNC("p3led_an utif", 2, 40, 1),
|
||||
FUNC("p3led_an", 0, 40, 1),
|
||||
};
|
||||
|
||||
static struct mtmips_pmx_func p2led_an_grp[] = {
|
||||
FUNC("jtag", 3, 41, 1),
|
||||
FUNC("utif", 2, 41, 1),
|
||||
FUNC("gpio", 1, 41, 1),
|
||||
FUNC("p2led_an jtag", 3, 41, 1),
|
||||
FUNC("p2led_an utif", 2, 41, 1),
|
||||
FUNC("p2led_an", 0, 41, 1),
|
||||
};
|
||||
|
||||
static struct mtmips_pmx_func p1led_an_grp[] = {
|
||||
FUNC("jtag", 3, 42, 1),
|
||||
FUNC("utif", 2, 42, 1),
|
||||
FUNC("gpio", 1, 42, 1),
|
||||
FUNC("p1led_an jtag", 3, 42, 1),
|
||||
FUNC("p1led_an utif", 2, 42, 1),
|
||||
FUNC("p1led_an", 0, 42, 1),
|
||||
};
|
||||
|
||||
static struct mtmips_pmx_func p0led_an_grp[] = {
|
||||
FUNC("jtag", 3, 43, 1),
|
||||
FUNC("rsvd", 2, 43, 1),
|
||||
FUNC("gpio", 1, 43, 1),
|
||||
FUNC("p0led_an jtag", 3, 43, 1),
|
||||
FUNC("p0led_an", 0, 43, 1),
|
||||
};
|
||||
|
||||
static struct mtmips_pmx_func wled_an_grp[] = {
|
||||
FUNC("rsvd", 3, 44, 1),
|
||||
FUNC("rsvd", 2, 44, 1),
|
||||
FUNC("gpio", 1, 44, 1),
|
||||
FUNC("wled_an", 0, 44, 1),
|
||||
};
|
||||
|
||||
|
||||
@ -978,23 +978,23 @@ static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdi
|
||||
static const char *mt7981_ant_groups[] = { "ant_sel", };
|
||||
|
||||
static const struct function_desc mt7981_functions[] = {
|
||||
{"wa_aice", mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)},
|
||||
{"dfd", mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)},
|
||||
{"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)},
|
||||
{"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)},
|
||||
{"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)},
|
||||
{"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)},
|
||||
{"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)},
|
||||
{"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)},
|
||||
{"eth", mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)},
|
||||
{"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)},
|
||||
{"led", mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)},
|
||||
{"pwm", mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)},
|
||||
{"spi", mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)},
|
||||
{"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)},
|
||||
{"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)},
|
||||
{"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)},
|
||||
{"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)},
|
||||
PINCTRL_PIN_FUNCTION("wa_aice", mt7981_wa_aice),
|
||||
PINCTRL_PIN_FUNCTION("dfd", mt7981_dfd),
|
||||
PINCTRL_PIN_FUNCTION("jtag", mt7981_jtag),
|
||||
PINCTRL_PIN_FUNCTION("pta", mt7981_pta),
|
||||
PINCTRL_PIN_FUNCTION("pcm", mt7981_pcm),
|
||||
PINCTRL_PIN_FUNCTION("udi", mt7981_udi),
|
||||
PINCTRL_PIN_FUNCTION("usb", mt7981_usb),
|
||||
PINCTRL_PIN_FUNCTION("ant", mt7981_ant),
|
||||
PINCTRL_PIN_FUNCTION("eth", mt7981_ethernet),
|
||||
PINCTRL_PIN_FUNCTION("i2c", mt7981_i2c),
|
||||
PINCTRL_PIN_FUNCTION("led", mt7981_led),
|
||||
PINCTRL_PIN_FUNCTION("pwm", mt7981_pwm),
|
||||
PINCTRL_PIN_FUNCTION("spi", mt7981_spi),
|
||||
PINCTRL_PIN_FUNCTION("uart", mt7981_uart),
|
||||
PINCTRL_PIN_FUNCTION("watchdog", mt7981_wdt),
|
||||
PINCTRL_PIN_FUNCTION("flash", mt7981_flash),
|
||||
PINCTRL_PIN_FUNCTION("pcie", mt7981_pcie),
|
||||
};
|
||||
|
||||
static const struct mtk_eint_hw mt7981_eint_hw = {
|
||||
|
||||
@ -879,18 +879,18 @@ static const char *mt7986_wdt_groups[] = { "watchdog", };
|
||||
static const char *mt7986_wf_groups[] = { "wf_2g", "wf_5g", "wf_dbdc", };
|
||||
|
||||
static const struct function_desc mt7986_functions[] = {
|
||||
{"audio", mt7986_audio_groups, ARRAY_SIZE(mt7986_audio_groups)},
|
||||
{"emmc", mt7986_emmc_groups, ARRAY_SIZE(mt7986_emmc_groups)},
|
||||
{"eth", mt7986_ethernet_groups, ARRAY_SIZE(mt7986_ethernet_groups)},
|
||||
{"i2c", mt7986_i2c_groups, ARRAY_SIZE(mt7986_i2c_groups)},
|
||||
{"led", mt7986_led_groups, ARRAY_SIZE(mt7986_led_groups)},
|
||||
{"flash", mt7986_flash_groups, ARRAY_SIZE(mt7986_flash_groups)},
|
||||
{"pcie", mt7986_pcie_groups, ARRAY_SIZE(mt7986_pcie_groups)},
|
||||
{"pwm", mt7986_pwm_groups, ARRAY_SIZE(mt7986_pwm_groups)},
|
||||
{"spi", mt7986_spi_groups, ARRAY_SIZE(mt7986_spi_groups)},
|
||||
{"uart", mt7986_uart_groups, ARRAY_SIZE(mt7986_uart_groups)},
|
||||
{"watchdog", mt7986_wdt_groups, ARRAY_SIZE(mt7986_wdt_groups)},
|
||||
{"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)},
|
||||
PINCTRL_PIN_FUNCTION("audio", mt7986_audio),
|
||||
PINCTRL_PIN_FUNCTION("emmc", mt7986_emmc),
|
||||
PINCTRL_PIN_FUNCTION("eth", mt7986_ethernet),
|
||||
PINCTRL_PIN_FUNCTION("i2c", mt7986_i2c),
|
||||
PINCTRL_PIN_FUNCTION("led", mt7986_led),
|
||||
PINCTRL_PIN_FUNCTION("flash", mt7986_flash),
|
||||
PINCTRL_PIN_FUNCTION("pcie", mt7986_pcie),
|
||||
PINCTRL_PIN_FUNCTION("pwm", mt7986_pwm),
|
||||
PINCTRL_PIN_FUNCTION("spi", mt7986_spi),
|
||||
PINCTRL_PIN_FUNCTION("uart", mt7986_uart),
|
||||
PINCTRL_PIN_FUNCTION("watchdog", mt7986_wdt),
|
||||
PINCTRL_PIN_FUNCTION("wifi", mt7986_wf),
|
||||
};
|
||||
|
||||
static const struct mtk_eint_hw mt7986a_eint_hw = {
|
||||
|
||||
@ -621,7 +621,6 @@ static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
struct device_node *np_config,
|
||||
struct pinctrl_map **map, unsigned *num_maps)
|
||||
{
|
||||
struct device_node *np;
|
||||
unsigned reserved_maps;
|
||||
int ret;
|
||||
|
||||
@ -629,12 +628,11 @@ static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
*num_maps = 0;
|
||||
reserved_maps = 0;
|
||||
|
||||
for_each_child_of_node(np_config, np) {
|
||||
for_each_child_of_node_scoped(np_config, np) {
|
||||
ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
|
||||
&reserved_maps, num_maps);
|
||||
if (ret < 0) {
|
||||
pinctrl_utils_free_map(pctldev, *map, *num_maps);
|
||||
of_node_put(np);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
@ -536,7 +536,6 @@ static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_map **map,
|
||||
unsigned *num_maps)
|
||||
{
|
||||
struct device_node *np;
|
||||
unsigned reserved_maps;
|
||||
int ret;
|
||||
|
||||
@ -544,13 +543,12 @@ static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
*num_maps = 0;
|
||||
reserved_maps = 0;
|
||||
|
||||
for_each_child_of_node(np_config, np) {
|
||||
for_each_child_of_node_scoped(np_config, np) {
|
||||
ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
|
||||
&reserved_maps,
|
||||
num_maps);
|
||||
if (ret < 0) {
|
||||
pinctrl_utils_free_map(pctldev, *map, *num_maps);
|
||||
of_node_put(np);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
@ -936,4 +936,5 @@ static struct platform_driver meson_a1_pinctrl_driver = {
|
||||
};
|
||||
|
||||
module_platform_driver(meson_a1_pinctrl_driver);
|
||||
MODULE_DESCRIPTION("Amlogic Meson A1 SoC pinctrl driver");
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
|
||||
@ -117,4 +117,5 @@ const struct pinmux_ops meson_axg_pmx_ops = {
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(meson_axg_pmx_ops);
|
||||
|
||||
MODULE_DESCRIPTION("Amlogic Meson AXG second generation pinmux driver");
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
|
||||
@ -1091,4 +1091,5 @@ static struct platform_driver meson_axg_pinctrl_driver = {
|
||||
};
|
||||
|
||||
module_platform_driver(meson_axg_pinctrl_driver);
|
||||
MODULE_DESCRIPTION("Amlogic Meson AXG pinctrl driver");
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
|
||||
@ -1426,4 +1426,5 @@ static struct platform_driver meson_g12a_pinctrl_driver = {
|
||||
};
|
||||
|
||||
module_platform_driver(meson_g12a_pinctrl_driver);
|
||||
MODULE_DESCRIPTION("Amlogic Meson G12A SoC pinctrl driver");
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
|
||||
@ -910,4 +910,5 @@ static struct platform_driver meson_gxbb_pinctrl_driver = {
|
||||
},
|
||||
};
|
||||
module_platform_driver(meson_gxbb_pinctrl_driver);
|
||||
MODULE_DESCRIPTION("Amlogic Meson GXBB pinctrl driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
@ -871,4 +871,5 @@ static struct platform_driver meson_gxl_pinctrl_driver = {
|
||||
},
|
||||
};
|
||||
module_platform_driver(meson_gxl_pinctrl_driver);
|
||||
MODULE_DESCRIPTION("Amlogic Meson GXL pinctrl driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
@ -1230,4 +1230,5 @@ static struct platform_driver meson_s4_pinctrl_driver = {
|
||||
};
|
||||
module_platform_driver(meson_s4_pinctrl_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Amlogic Meson S4 SoC pinctrl driver");
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
|
||||
@ -767,4 +767,5 @@ int meson_pinctrl_probe(struct platform_device *pdev)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(meson_pinctrl_probe);
|
||||
|
||||
MODULE_DESCRIPTION("Amlogic Meson SoCs core pinctrl driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
@ -101,4 +101,5 @@ const struct pinmux_ops meson8_pmx_ops = {
|
||||
.gpio_request_enable = meson8_pmx_request_gpio,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(meson8_pmx_ops);
|
||||
MODULE_DESCRIPTION("Amlogic Meson SoCs first generation pinmux driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
@ -811,19 +811,17 @@ static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_map **map, unsigned *num_maps)
|
||||
{
|
||||
unsigned reserved_maps;
|
||||
struct device_node *np;
|
||||
int ret;
|
||||
|
||||
reserved_maps = 0;
|
||||
*map = NULL;
|
||||
*num_maps = 0;
|
||||
|
||||
for_each_child_of_node(np_config, np) {
|
||||
for_each_child_of_node_scoped(np_config, np) {
|
||||
ret = abx500_dt_subnode_to_map(pctldev, np, map,
|
||||
&reserved_maps, num_maps);
|
||||
if (ret < 0) {
|
||||
pinctrl_utils_free_map(pctldev, *map, *num_maps);
|
||||
of_node_put(np);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
@ -804,19 +804,17 @@ static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
unsigned int *num_maps)
|
||||
{
|
||||
unsigned int reserved_maps;
|
||||
struct device_node *np;
|
||||
int ret;
|
||||
|
||||
reserved_maps = 0;
|
||||
*map = NULL;
|
||||
*num_maps = 0;
|
||||
|
||||
for_each_child_of_node(np_config, np) {
|
||||
for_each_child_of_node_scoped(np_config, np) {
|
||||
ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
|
||||
&reserved_maps, num_maps);
|
||||
if (ret < 0) {
|
||||
pinctrl_utils_free_map(pctldev, *map, *num_maps);
|
||||
of_node_put(np);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
@ -45,3 +45,22 @@ config PINCTRL_NPCM8XX
|
||||
Say Y or M here to enable pin controller and GPIO support for
|
||||
the Nuvoton NPCM8XX SoC. This is strongly recommended when
|
||||
building a kernel that will run on this chip.
|
||||
|
||||
config PINCTRL_MA35
|
||||
bool
|
||||
depends on (ARCH_MA35 || COMPILE_TEST) && OF
|
||||
select GENERIC_PINCTRL_GROUPS
|
||||
select GENERIC_PINMUX_FUNCTIONS
|
||||
select GENERIC_PINCONF
|
||||
select GPIOLIB
|
||||
select GPIO_GENERIC
|
||||
select GPIOLIB_IRQCHIP
|
||||
select MFD_SYSCON
|
||||
|
||||
config PINCTRL_MA35D1
|
||||
bool "Pinctrl and GPIO driver for Nuvoton MA35D1"
|
||||
depends on (ARCH_MA35 || COMPILE_TEST) && OF
|
||||
select PINCTRL_MA35
|
||||
help
|
||||
Say Y here to enable pin controller and GPIO support
|
||||
for Nuvoton MA35D1 SoC.
|
||||
|
||||
@ -4,3 +4,5 @@
|
||||
obj-$(CONFIG_PINCTRL_WPCM450) += pinctrl-wpcm450.o
|
||||
obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o
|
||||
obj-$(CONFIG_PINCTRL_NPCM8XX) += pinctrl-npcm8xx.o
|
||||
obj-$(CONFIG_PINCTRL_MA35) += pinctrl-ma35.o
|
||||
obj-$(CONFIG_PINCTRL_MA35D1) += pinctrl-ma35d1.o
|
||||
|
||||
1187
drivers/pinctrl/nuvoton/pinctrl-ma35.c
Normal file
1187
drivers/pinctrl/nuvoton/pinctrl-ma35.c
Normal file
File diff suppressed because it is too large
Load Diff
52
drivers/pinctrl/nuvoton/pinctrl-ma35.h
Normal file
52
drivers/pinctrl/nuvoton/pinctrl-ma35.h
Normal file
@ -0,0 +1,52 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2024 Nuvoton Technology Corp.
|
||||
*
|
||||
* Author: Shan-Chun Hung <schung@nuvoton.com>
|
||||
* * Jacky Huang <ychuang3@nuvoton.com>
|
||||
*/
|
||||
#ifndef __PINCTRL_MA35_H
|
||||
#define __PINCTRL_MA35_H
|
||||
|
||||
#include <linux/pinctrl/pinconf-generic.h>
|
||||
#include <linux/pinctrl/pinmux.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
struct ma35_mux_desc {
|
||||
const char *name;
|
||||
u32 muxval;
|
||||
};
|
||||
|
||||
struct ma35_pin_data {
|
||||
u32 offset;
|
||||
u32 shift;
|
||||
struct ma35_mux_desc *muxes;
|
||||
};
|
||||
|
||||
struct ma35_pinctrl_soc_info {
|
||||
const struct pinctrl_pin_desc *pins;
|
||||
unsigned int npins;
|
||||
int (*get_pin_num)(int offset, int shift);
|
||||
};
|
||||
|
||||
#define MA35_PIN(num, n, o, s, ...) { \
|
||||
.number = num, \
|
||||
.name = #n, \
|
||||
.drv_data = &(struct ma35_pin_data) { \
|
||||
.offset = o, \
|
||||
.shift = s, \
|
||||
.muxes = (struct ma35_mux_desc[]) { \
|
||||
__VA_ARGS__, { } }, \
|
||||
}, \
|
||||
}
|
||||
|
||||
#define MA35_MUX(_val, _name) { \
|
||||
.name = _name, \
|
||||
.muxval = _val, \
|
||||
}
|
||||
|
||||
int ma35_pinctrl_probe(struct platform_device *pdev, const struct ma35_pinctrl_soc_info *info);
|
||||
int ma35_pinctrl_suspend(struct device *dev);
|
||||
int ma35_pinctrl_resume(struct device *dev);
|
||||
|
||||
#endif /* __PINCTRL_MA35_H */
|
||||
1799
drivers/pinctrl/nuvoton/pinctrl-ma35d1.c
Normal file
1799
drivers/pinctrl/nuvoton/pinctrl-ma35d1.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -268,28 +268,23 @@ static int s32_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
unsigned int *num_maps)
|
||||
{
|
||||
unsigned int reserved_maps;
|
||||
struct device_node *np;
|
||||
int ret = 0;
|
||||
int ret;
|
||||
|
||||
reserved_maps = 0;
|
||||
*map = NULL;
|
||||
*num_maps = 0;
|
||||
|
||||
for_each_available_child_of_node(np_config, np) {
|
||||
for_each_available_child_of_node_scoped(np_config, np) {
|
||||
ret = s32_dt_group_node_to_map(pctldev, np, map,
|
||||
&reserved_maps, num_maps,
|
||||
np_config->name);
|
||||
if (ret < 0) {
|
||||
of_node_put(np);
|
||||
break;
|
||||
pinctrl_utils_free_map(pctldev, *map, *num_maps);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
if (ret)
|
||||
pinctrl_utils_free_map(pctldev, *map, *num_maps);
|
||||
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct pinctrl_ops s32_pctrl_ops = {
|
||||
@ -786,7 +781,6 @@ static int s32_pinctrl_parse_functions(struct device_node *np,
|
||||
struct s32_pinctrl_soc_info *info,
|
||||
u32 index)
|
||||
{
|
||||
struct device_node *child;
|
||||
struct pinfunction *func;
|
||||
struct s32_pin_group *grp;
|
||||
const char **groups;
|
||||
@ -810,14 +804,12 @@ static int s32_pinctrl_parse_functions(struct device_node *np,
|
||||
if (!groups)
|
||||
return -ENOMEM;
|
||||
|
||||
for_each_child_of_node(np, child) {
|
||||
for_each_child_of_node_scoped(np, child) {
|
||||
groups[i] = child->name;
|
||||
grp = &info->groups[info->grp_index++];
|
||||
ret = s32_pinctrl_parse_groups(child, grp, info);
|
||||
if (ret) {
|
||||
of_node_put(child);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
i++;
|
||||
}
|
||||
|
||||
@ -831,7 +823,6 @@ static int s32_pinctrl_probe_dt(struct platform_device *pdev,
|
||||
{
|
||||
struct s32_pinctrl_soc_info *info = ipctl->info;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct device_node *child;
|
||||
struct resource *res;
|
||||
struct regmap *map;
|
||||
void __iomem *base;
|
||||
@ -889,7 +880,7 @@ static int s32_pinctrl_probe_dt(struct platform_device *pdev,
|
||||
return -ENOMEM;
|
||||
|
||||
info->ngroups = 0;
|
||||
for_each_child_of_node(np, child)
|
||||
for_each_child_of_node_scoped(np, child)
|
||||
info->ngroups += of_get_child_count(child);
|
||||
|
||||
info->groups = devm_kcalloc(&pdev->dev, info->ngroups,
|
||||
@ -898,12 +889,10 @@ static int s32_pinctrl_probe_dt(struct platform_device *pdev,
|
||||
return -ENOMEM;
|
||||
|
||||
i = 0;
|
||||
for_each_child_of_node(np, child) {
|
||||
for_each_child_of_node_scoped(np, child) {
|
||||
ret = s32_pinctrl_parse_functions(child, info, i++);
|
||||
if (ret) {
|
||||
of_node_put(child);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
@ -382,7 +382,6 @@ int pinconf_generic_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
unsigned int *num_maps, enum pinctrl_map_type type)
|
||||
{
|
||||
unsigned int reserved_maps;
|
||||
struct device_node *np;
|
||||
int ret;
|
||||
|
||||
reserved_maps = 0;
|
||||
@ -394,13 +393,11 @@ int pinconf_generic_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
if (ret < 0)
|
||||
goto exit;
|
||||
|
||||
for_each_available_child_of_node(np_config, np) {
|
||||
for_each_available_child_of_node_scoped(np_config, np) {
|
||||
ret = pinconf_generic_dt_subnode_to_map(pctldev, np, map,
|
||||
&reserved_maps, num_maps, type);
|
||||
if (ret < 0) {
|
||||
of_node_put(np);
|
||||
if (ret < 0)
|
||||
goto exit;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
|
||||
|
||||
@ -632,7 +632,6 @@ static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_map **map,
|
||||
unsigned int *num_maps)
|
||||
{
|
||||
struct device_node *np;
|
||||
unsigned int reserved_maps;
|
||||
int ret;
|
||||
|
||||
@ -648,13 +647,11 @@ static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map,
|
||||
&reserved_maps, num_maps);
|
||||
if (ret) {
|
||||
for_each_child_of_node(np_config, np) {
|
||||
for_each_child_of_node_scoped(np_config, np) {
|
||||
ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map,
|
||||
&reserved_maps, num_maps);
|
||||
if (ret < 0) {
|
||||
of_node_put(np);
|
||||
if (ret < 0)
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -1244,7 +1244,6 @@ static int at91_pinctrl_parse_groups(struct device_node *np,
|
||||
static int at91_pinctrl_parse_functions(struct device_node *np,
|
||||
struct at91_pinctrl *info, u32 index)
|
||||
{
|
||||
struct device_node *child;
|
||||
struct at91_pmx_func *func;
|
||||
struct at91_pin_group *grp;
|
||||
int ret;
|
||||
@ -1267,14 +1266,12 @@ static int at91_pinctrl_parse_functions(struct device_node *np,
|
||||
if (!func->groups)
|
||||
return -ENOMEM;
|
||||
|
||||
for_each_child_of_node(np, child) {
|
||||
for_each_child_of_node_scoped(np, child) {
|
||||
func->groups[i] = child->name;
|
||||
grp = &info->groups[grp_index++];
|
||||
ret = at91_pinctrl_parse_groups(child, grp, info, i++);
|
||||
if (ret) {
|
||||
of_node_put(child);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
@ -1296,7 +1293,6 @@ static int at91_pinctrl_probe_dt(struct platform_device *pdev,
|
||||
int i, j, ngpio_chips_enabled = 0;
|
||||
uint32_t *tmp;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct device_node *child;
|
||||
|
||||
if (!np)
|
||||
return -ENODEV;
|
||||
@ -1349,14 +1345,12 @@ static int at91_pinctrl_probe_dt(struct platform_device *pdev,
|
||||
|
||||
i = 0;
|
||||
|
||||
for_each_child_of_node(np, child) {
|
||||
for_each_child_of_node_scoped(np, child) {
|
||||
if (of_device_is_compatible(child, gpio_compat))
|
||||
continue;
|
||||
ret = at91_pinctrl_parse_functions(child, info, i++);
|
||||
if (ret) {
|
||||
of_node_put(child);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "failed to parse function\n");
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
@ -9,6 +9,7 @@
|
||||
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/bitmap.h>
|
||||
#include <linux/cleanup.h>
|
||||
#include <linux/dmi.h>
|
||||
#include <linux/gpio/driver.h>
|
||||
#include <linux/gpio/consumer.h>
|
||||
@ -58,9 +59,14 @@
|
||||
|
||||
#define CY8C95X0_PIN_TO_OFFSET(x) (((x) >= 20) ? ((x) + 4) : (x))
|
||||
|
||||
#define CY8C95X0_MUX_REGMAP_TO_PORT(x) ((x) / MUXED_STRIDE)
|
||||
#define CY8C95X0_MUX_REGMAP_TO_REG(x) (((x) % MUXED_STRIDE) + CY8C95X0_INTMASK)
|
||||
#define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) ((x) - CY8C95X0_INTMASK + (p) * MUXED_STRIDE)
|
||||
#define MAX_BANK 8
|
||||
#define BANK_SZ 8
|
||||
#define MAX_LINE (MAX_BANK * BANK_SZ)
|
||||
#define MUXED_STRIDE (CY8C95X0_DRV_HIZ - CY8C95X0_INTMASK)
|
||||
#define CY8C95X0_GPIO_MASK GENMASK(7, 0)
|
||||
#define CY8C95X0_VIRTUAL (CY8C95X0_COMMAND + 1)
|
||||
#define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) \
|
||||
(CY8C95X0_VIRTUAL + (x) - CY8C95X0_INTMASK + (p) * MUXED_STRIDE)
|
||||
|
||||
static const struct i2c_device_id cy8c95x0_id[] = {
|
||||
{ "cy8c9520", 20, },
|
||||
@ -120,18 +126,11 @@ static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = {
|
||||
{}
|
||||
};
|
||||
|
||||
#define MAX_BANK 8
|
||||
#define BANK_SZ 8
|
||||
#define MAX_LINE (MAX_BANK * BANK_SZ)
|
||||
#define MUXED_STRIDE 16
|
||||
#define CY8C95X0_GPIO_MASK GENMASK(7, 0)
|
||||
|
||||
/**
|
||||
* struct cy8c95x0_pinctrl - driver data
|
||||
* @regmap: Device's regmap. Only direct access registers.
|
||||
* @muxed_regmap: Regmap for all muxed registers.
|
||||
* @irq_lock: IRQ bus lock
|
||||
* @i2c_lock: Mutex for the device internal mux register
|
||||
* @i2c_lock: Mutex to hold while using the regmap
|
||||
* @irq_mask: I/O bits affected by interrupts
|
||||
* @irq_trig_raise: I/O bits affected by raising voltage level
|
||||
* @irq_trig_fall: I/O bits affected by falling voltage level
|
||||
@ -152,7 +151,6 @@ static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = {
|
||||
*/
|
||||
struct cy8c95x0_pinctrl {
|
||||
struct regmap *regmap;
|
||||
struct regmap *muxed_regmap;
|
||||
struct mutex irq_lock;
|
||||
struct mutex i2c_lock;
|
||||
DECLARE_BITMAP(irq_mask, MAX_LINE);
|
||||
@ -331,6 +329,9 @@ static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin)
|
||||
|
||||
static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg)
|
||||
{
|
||||
if (reg >= CY8C95X0_VIRTUAL)
|
||||
return true;
|
||||
|
||||
switch (reg) {
|
||||
case 0x24 ... 0x27:
|
||||
return false;
|
||||
@ -341,6 +342,9 @@ static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg)
|
||||
|
||||
static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg)
|
||||
{
|
||||
if (reg >= CY8C95X0_VIRTUAL)
|
||||
return true;
|
||||
|
||||
switch (reg) {
|
||||
case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
|
||||
return false;
|
||||
@ -433,115 +437,34 @@ static bool cy8c95x0_quick_path_register(unsigned int reg)
|
||||
}
|
||||
}
|
||||
|
||||
static const struct reg_default cy8c95x0_reg_defaults[] = {
|
||||
{ CY8C95X0_OUTPUT_(0), GENMASK(7, 0) },
|
||||
{ CY8C95X0_OUTPUT_(1), GENMASK(7, 0) },
|
||||
{ CY8C95X0_OUTPUT_(2), GENMASK(7, 0) },
|
||||
{ CY8C95X0_OUTPUT_(3), GENMASK(7, 0) },
|
||||
{ CY8C95X0_OUTPUT_(4), GENMASK(7, 0) },
|
||||
{ CY8C95X0_OUTPUT_(5), GENMASK(7, 0) },
|
||||
{ CY8C95X0_OUTPUT_(6), GENMASK(7, 0) },
|
||||
{ CY8C95X0_OUTPUT_(7), GENMASK(7, 0) },
|
||||
{ CY8C95X0_PORTSEL, 0 },
|
||||
{ CY8C95X0_PWMSEL, 0 },
|
||||
static const struct regmap_range_cfg cy8c95x0_ranges[] = {
|
||||
{
|
||||
.range_min = CY8C95X0_VIRTUAL,
|
||||
.range_max = 0, /* Updated at runtime */
|
||||
.selector_reg = CY8C95X0_PORTSEL,
|
||||
.selector_mask = 0x07,
|
||||
.selector_shift = 0x0,
|
||||
.window_start = CY8C95X0_INTMASK,
|
||||
.window_len = MUXED_STRIDE,
|
||||
}
|
||||
};
|
||||
|
||||
static int
|
||||
cy8c95x0_mux_reg_read(void *context, unsigned int off, unsigned int *val)
|
||||
{
|
||||
struct cy8c95x0_pinctrl *chip = context;
|
||||
u8 port = CY8C95X0_MUX_REGMAP_TO_PORT(off);
|
||||
int ret, reg = CY8C95X0_MUX_REGMAP_TO_REG(off);
|
||||
|
||||
mutex_lock(&chip->i2c_lock);
|
||||
/* Select the correct bank */
|
||||
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
/*
|
||||
* Read the register through direct access regmap. The target range
|
||||
* is marked volatile.
|
||||
*/
|
||||
ret = regmap_read(chip->regmap, reg, val);
|
||||
out:
|
||||
mutex_unlock(&chip->i2c_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
cy8c95x0_mux_reg_write(void *context, unsigned int off, unsigned int val)
|
||||
{
|
||||
struct cy8c95x0_pinctrl *chip = context;
|
||||
u8 port = CY8C95X0_MUX_REGMAP_TO_PORT(off);
|
||||
int ret, reg = CY8C95X0_MUX_REGMAP_TO_REG(off);
|
||||
|
||||
mutex_lock(&chip->i2c_lock);
|
||||
/* Select the correct bank */
|
||||
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
/*
|
||||
* Write the register through direct access regmap. The target range
|
||||
* is marked volatile.
|
||||
*/
|
||||
ret = regmap_write(chip->regmap, reg, val);
|
||||
out:
|
||||
mutex_unlock(&chip->i2c_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static bool cy8c95x0_mux_accessible_register(struct device *dev, unsigned int off)
|
||||
{
|
||||
struct i2c_client *i2c = to_i2c_client(dev);
|
||||
struct cy8c95x0_pinctrl *chip = i2c_get_clientdata(i2c);
|
||||
u8 port = CY8C95X0_MUX_REGMAP_TO_PORT(off);
|
||||
u8 reg = CY8C95X0_MUX_REGMAP_TO_REG(off);
|
||||
|
||||
if (port >= chip->nport)
|
||||
return false;
|
||||
|
||||
return cy8c95x0_muxed_register(reg);
|
||||
}
|
||||
|
||||
static struct regmap_bus cy8c95x0_regmap_bus = {
|
||||
.reg_read = cy8c95x0_mux_reg_read,
|
||||
.reg_write = cy8c95x0_mux_reg_write,
|
||||
};
|
||||
|
||||
/* Regmap for muxed registers CY8C95X0_INTMASK - CY8C95X0_DRV_HIZ */
|
||||
static const struct regmap_config cy8c95x0_muxed_regmap = {
|
||||
.name = "muxed",
|
||||
static const struct regmap_config cy8c9520_i2c_regmap = {
|
||||
.reg_bits = 8,
|
||||
.val_bits = 8,
|
||||
.cache_type = REGCACHE_FLAT,
|
||||
.use_single_read = true,
|
||||
.use_single_write = true,
|
||||
.max_register = MUXED_STRIDE * BANK_SZ,
|
||||
.num_reg_defaults_raw = MUXED_STRIDE * BANK_SZ,
|
||||
.readable_reg = cy8c95x0_mux_accessible_register,
|
||||
.writeable_reg = cy8c95x0_mux_accessible_register,
|
||||
};
|
||||
|
||||
/* Direct access regmap */
|
||||
static const struct regmap_config cy8c95x0_i2c_regmap = {
|
||||
.name = "direct",
|
||||
.reg_bits = 8,
|
||||
.val_bits = 8,
|
||||
|
||||
.reg_defaults = cy8c95x0_reg_defaults,
|
||||
.num_reg_defaults = ARRAY_SIZE(cy8c95x0_reg_defaults),
|
||||
|
||||
.readable_reg = cy8c95x0_readable_register,
|
||||
.writeable_reg = cy8c95x0_writeable_register,
|
||||
.volatile_reg = cy8c95x0_volatile_register,
|
||||
.precious_reg = cy8c95x0_precious_register,
|
||||
|
||||
.cache_type = REGCACHE_FLAT,
|
||||
.max_register = CY8C95X0_COMMAND,
|
||||
.cache_type = REGCACHE_MAPLE,
|
||||
.ranges = NULL, /* Updated at runtime */
|
||||
.num_ranges = 1,
|
||||
.max_register = 0, /* Updated at runtime */
|
||||
.num_reg_defaults_raw = 0, /* Updated at runtime */
|
||||
.use_single_read = true, /* Workaround for regcache bug */
|
||||
.disable_locking = true,
|
||||
};
|
||||
|
||||
static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip,
|
||||
@ -552,48 +475,42 @@ static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip
|
||||
bool *change, bool async,
|
||||
bool force)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int ret, off, i, read_val;
|
||||
int ret, off, i;
|
||||
|
||||
/* Caller should never modify PORTSEL directly */
|
||||
if (reg == CY8C95X0_PORTSEL)
|
||||
return -EINVAL;
|
||||
|
||||
/* Registers behind the PORTSEL mux have their own regmap */
|
||||
/* Registers behind the PORTSEL mux have their own range in regmap */
|
||||
if (cy8c95x0_muxed_register(reg)) {
|
||||
regmap = chip->muxed_regmap;
|
||||
off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port);
|
||||
} else {
|
||||
regmap = chip->regmap;
|
||||
/* Quick path direct access registers honor the port argument */
|
||||
if (cy8c95x0_quick_path_register(reg))
|
||||
off = reg + port;
|
||||
else
|
||||
off = reg;
|
||||
}
|
||||
guard(mutex)(&chip->i2c_lock);
|
||||
|
||||
ret = regmap_update_bits_base(regmap, off, mask, val, change, async, force);
|
||||
ret = regmap_update_bits_base(chip->regmap, off, mask, val, change, async, force);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Update the cache when a WC bit is written */
|
||||
/* Mimic what hardware does and update the cache when a WC bit is written.
|
||||
* Allows to mark the registers as non-volatile and reduces I/O cycles.
|
||||
*/
|
||||
if (cy8c95x0_wc_register(reg) && (mask & val)) {
|
||||
/* Writing a 1 clears set bits in the other drive mode registers */
|
||||
regcache_cache_only(chip->regmap, true);
|
||||
for (i = CY8C95X0_DRV_PU; i <= CY8C95X0_DRV_HIZ; i++) {
|
||||
if (i == reg)
|
||||
continue;
|
||||
|
||||
off = CY8C95X0_MUX_REGMAP_TO_OFFSET(i, port);
|
||||
|
||||
ret = regmap_read(regmap, off, &read_val);
|
||||
if (ret < 0)
|
||||
continue;
|
||||
|
||||
if (!(read_val & mask & val))
|
||||
continue;
|
||||
|
||||
regcache_cache_only(regmap, true);
|
||||
regmap_update_bits(regmap, off, mask & val, 0);
|
||||
regcache_cache_only(regmap, false);
|
||||
regmap_clear_bits(chip->regmap, off, mask & val);
|
||||
}
|
||||
regcache_cache_only(chip->regmap, false);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -666,23 +583,23 @@ static int cy8c95x0_regmap_update_bits(struct cy8c95x0_pinctrl *chip, unsigned i
|
||||
static int cy8c95x0_regmap_read(struct cy8c95x0_pinctrl *chip, unsigned int reg,
|
||||
unsigned int port, unsigned int *read_val)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int off;
|
||||
int off, ret;
|
||||
|
||||
/* Registers behind the PORTSEL mux have their own regmap */
|
||||
/* Registers behind the PORTSEL mux have their own range in regmap */
|
||||
if (cy8c95x0_muxed_register(reg)) {
|
||||
regmap = chip->muxed_regmap;
|
||||
off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port);
|
||||
} else {
|
||||
regmap = chip->regmap;
|
||||
/* Quick path direct access registers honor the port argument */
|
||||
if (cy8c95x0_quick_path_register(reg))
|
||||
off = reg + port;
|
||||
else
|
||||
off = reg;
|
||||
}
|
||||
guard(mutex)(&chip->i2c_lock);
|
||||
|
||||
return regmap_read(regmap, off, read_val);
|
||||
ret = regmap_read(chip->regmap, off, read_val);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
|
||||
@ -1511,6 +1428,8 @@ static int cy8c95x0_detect(struct i2c_client *client,
|
||||
static int cy8c95x0_probe(struct i2c_client *client)
|
||||
{
|
||||
struct cy8c95x0_pinctrl *chip;
|
||||
struct regmap_config regmap_conf;
|
||||
struct regmap_range_cfg regmap_range_conf;
|
||||
struct regulator *reg;
|
||||
int ret;
|
||||
|
||||
@ -1530,15 +1449,20 @@ static int cy8c95x0_probe(struct i2c_client *client)
|
||||
chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK;
|
||||
chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ);
|
||||
|
||||
memcpy(®map_range_conf, &cy8c95x0_ranges[0], sizeof(regmap_range_conf));
|
||||
|
||||
switch (chip->tpin) {
|
||||
case 20:
|
||||
strscpy(chip->name, cy8c95x0_id[0].name, I2C_NAME_SIZE);
|
||||
regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 3 * MUXED_STRIDE;
|
||||
break;
|
||||
case 40:
|
||||
strscpy(chip->name, cy8c95x0_id[1].name, I2C_NAME_SIZE);
|
||||
regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 6 * MUXED_STRIDE;
|
||||
break;
|
||||
case 60:
|
||||
strscpy(chip->name, cy8c95x0_id[2].name, I2C_NAME_SIZE);
|
||||
regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 8 * MUXED_STRIDE;
|
||||
break;
|
||||
default:
|
||||
return -ENODEV;
|
||||
@ -1571,22 +1495,18 @@ static int cy8c95x0_probe(struct i2c_client *client)
|
||||
gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET");
|
||||
}
|
||||
|
||||
/* Generic regmap for direct access registers */
|
||||
chip->regmap = devm_regmap_init_i2c(client, &cy8c95x0_i2c_regmap);
|
||||
/* Regmap for direct and paged registers */
|
||||
memcpy(®map_conf, &cy8c9520_i2c_regmap, sizeof(regmap_conf));
|
||||
regmap_conf.ranges = ®map_range_conf;
|
||||
regmap_conf.max_register = regmap_range_conf.range_max;
|
||||
regmap_conf.num_reg_defaults_raw = regmap_range_conf.range_max;
|
||||
|
||||
chip->regmap = devm_regmap_init_i2c(client, ®map_conf);
|
||||
if (IS_ERR(chip->regmap)) {
|
||||
ret = PTR_ERR(chip->regmap);
|
||||
goto err_exit;
|
||||
}
|
||||
|
||||
/* Port specific regmap behind PORTSEL mux */
|
||||
chip->muxed_regmap = devm_regmap_init(&client->dev, &cy8c95x0_regmap_bus,
|
||||
chip, &cy8c95x0_muxed_regmap);
|
||||
if (IS_ERR(chip->muxed_regmap)) {
|
||||
ret = dev_err_probe(&client->dev, PTR_ERR(chip->muxed_regmap),
|
||||
"Failed to register muxed regmap\n");
|
||||
goto err_exit;
|
||||
}
|
||||
|
||||
bitmap_zero(chip->push_pull, MAX_LINE);
|
||||
bitmap_zero(chip->shiftmask, MAX_LINE);
|
||||
bitmap_set(chip->shiftmask, 0, 20);
|
||||
|
||||
@ -566,8 +566,8 @@ static const struct pinconf_ops eqbr_pinconf_ops = {
|
||||
.pin_config_config_dbg_show = pinconf_generic_dump_config,
|
||||
};
|
||||
|
||||
static bool is_func_exist(struct eqbr_pmx_func *funcs, const char *name,
|
||||
unsigned int nr_funcs, unsigned int *idx)
|
||||
static bool is_func_exist(struct pinfunction *funcs, const char *name,
|
||||
unsigned int nr_funcs, unsigned int *idx)
|
||||
{
|
||||
int i;
|
||||
|
||||
@ -584,18 +584,18 @@ static bool is_func_exist(struct eqbr_pmx_func *funcs, const char *name,
|
||||
return false;
|
||||
}
|
||||
|
||||
static int funcs_utils(struct device *dev, struct eqbr_pmx_func *funcs,
|
||||
static int funcs_utils(struct device *dev, struct pinfunction *funcs,
|
||||
unsigned int *nr_funcs, funcs_util_ops op)
|
||||
{
|
||||
struct device_node *node = dev->of_node;
|
||||
struct device_node *np;
|
||||
struct property *prop;
|
||||
const char *fn_name;
|
||||
const char **groups;
|
||||
unsigned int fid;
|
||||
int i, j;
|
||||
|
||||
i = 0;
|
||||
for_each_child_of_node(node, np) {
|
||||
for_each_child_of_node_scoped(node, np) {
|
||||
prop = of_find_property(np, "groups", NULL);
|
||||
if (!prop)
|
||||
continue;
|
||||
@ -620,20 +620,20 @@ static int funcs_utils(struct device *dev, struct eqbr_pmx_func *funcs,
|
||||
|
||||
case OP_COUNT_NR_FUNC_GRPS:
|
||||
if (is_func_exist(funcs, fn_name, *nr_funcs, &fid))
|
||||
funcs[fid].nr_groups++;
|
||||
funcs[fid].ngroups++;
|
||||
break;
|
||||
|
||||
case OP_ADD_FUNC_GRPS:
|
||||
if (is_func_exist(funcs, fn_name, *nr_funcs, &fid)) {
|
||||
for (j = 0; j < funcs[fid].nr_groups; j++)
|
||||
if (!funcs[fid].groups[j])
|
||||
groups = (const char **)funcs[fid].groups;
|
||||
for (j = 0; j < funcs[fid].ngroups; j++)
|
||||
if (!groups[j])
|
||||
break;
|
||||
funcs[fid].groups[j] = prop->value;
|
||||
groups[j] = prop->value;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
of_node_put(np);
|
||||
return -EINVAL;
|
||||
}
|
||||
i++;
|
||||
@ -645,7 +645,7 @@ static int funcs_utils(struct device *dev, struct eqbr_pmx_func *funcs,
|
||||
static int eqbr_build_functions(struct eqbr_pinctrl_drv_data *drvdata)
|
||||
{
|
||||
struct device *dev = drvdata->dev;
|
||||
struct eqbr_pmx_func *funcs = NULL;
|
||||
struct pinfunction *funcs = NULL;
|
||||
unsigned int nr_funcs = 0;
|
||||
int i, ret;
|
||||
|
||||
@ -666,9 +666,9 @@ static int eqbr_build_functions(struct eqbr_pinctrl_drv_data *drvdata)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < nr_funcs; i++) {
|
||||
if (!funcs[i].nr_groups)
|
||||
if (!funcs[i].ngroups)
|
||||
continue;
|
||||
funcs[i].groups = devm_kcalloc(dev, funcs[i].nr_groups,
|
||||
funcs[i].groups = devm_kcalloc(dev, funcs[i].ngroups,
|
||||
sizeof(*(funcs[i].groups)),
|
||||
GFP_KERNEL);
|
||||
if (!funcs[i].groups)
|
||||
@ -688,7 +688,7 @@ static int eqbr_build_functions(struct eqbr_pinctrl_drv_data *drvdata)
|
||||
ret = pinmux_generic_add_function(drvdata->pctl_dev,
|
||||
funcs[i].name,
|
||||
funcs[i].groups,
|
||||
funcs[i].nr_groups,
|
||||
funcs[i].ngroups,
|
||||
drvdata);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "Failed to register function %s\n",
|
||||
@ -706,11 +706,10 @@ static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata)
|
||||
struct device_node *node = dev->of_node;
|
||||
unsigned int *pins, *pinmux, pin_id, pinmux_id;
|
||||
struct pingroup group, *grp = &group;
|
||||
struct device_node *np;
|
||||
struct property *prop;
|
||||
int j, err;
|
||||
|
||||
for_each_child_of_node(node, np) {
|
||||
for_each_child_of_node_scoped(node, np) {
|
||||
prop = of_find_property(np, "groups", NULL);
|
||||
if (!prop)
|
||||
continue;
|
||||
@ -718,42 +717,35 @@ static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata)
|
||||
err = of_property_count_u32_elems(np, "pins");
|
||||
if (err < 0) {
|
||||
dev_err(dev, "No pins in the group: %s\n", prop->name);
|
||||
of_node_put(np);
|
||||
return err;
|
||||
}
|
||||
grp->npins = err;
|
||||
grp->name = prop->value;
|
||||
pins = devm_kcalloc(dev, grp->npins, sizeof(*pins), GFP_KERNEL);
|
||||
if (!pins) {
|
||||
of_node_put(np);
|
||||
if (!pins)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
grp->pins = pins;
|
||||
|
||||
pinmux = devm_kcalloc(dev, grp->npins, sizeof(*pinmux), GFP_KERNEL);
|
||||
if (!pinmux) {
|
||||
of_node_put(np);
|
||||
if (!pinmux)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
for (j = 0; j < grp->npins; j++) {
|
||||
if (of_property_read_u32_index(np, "pins", j, &pin_id)) {
|
||||
dev_err(dev, "Group %s: Read intel pins id failed\n",
|
||||
grp->name);
|
||||
of_node_put(np);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (pin_id >= drvdata->pctl_desc.npins) {
|
||||
dev_err(dev, "Group %s: Invalid pin ID, idx: %d, pin %u\n",
|
||||
grp->name, j, pin_id);
|
||||
of_node_put(np);
|
||||
return -EINVAL;
|
||||
}
|
||||
pins[j] = pin_id;
|
||||
if (of_property_read_u32_index(np, "pinmux", j, &pinmux_id)) {
|
||||
dev_err(dev, "Group %s: Read intel pinmux id failed\n",
|
||||
grp->name);
|
||||
of_node_put(np);
|
||||
return -EINVAL;
|
||||
}
|
||||
pinmux[j] = pinmux_id;
|
||||
@ -764,7 +756,6 @@ static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata)
|
||||
pinmux);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "Failed to register group %s\n", grp->name);
|
||||
of_node_put(np);
|
||||
return err;
|
||||
}
|
||||
memset(&group, 0, sizeof(group));
|
||||
|
||||
@ -67,18 +67,6 @@ struct gpio_irq_type {
|
||||
unsigned int logic_type;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct eqbr_pmx_func: represent a pin function.
|
||||
* @name: name of the pin function, used to lookup the function.
|
||||
* @groups: one or more names of pin groups that provide this function.
|
||||
* @nr_groups: number of groups included in @groups.
|
||||
*/
|
||||
struct eqbr_pmx_func {
|
||||
const char *name;
|
||||
const char **groups;
|
||||
unsigned int nr_groups;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct eqbr_pin_bank: represent a pin bank.
|
||||
* @membase: base address of the pin bank register.
|
||||
|
||||
@ -94,6 +94,12 @@
|
||||
.data = (void *)func, \
|
||||
}
|
||||
|
||||
#define INGENIC_PIN_FUNCTION(_name_, id) \
|
||||
{ \
|
||||
.func = PINCTRL_PINFUNCTION(_name_, id##_groups, ARRAY_SIZE(id##_groups)), \
|
||||
.data = NULL, \
|
||||
}
|
||||
|
||||
enum jz_version {
|
||||
ID_JZ4730,
|
||||
ID_JZ4740,
|
||||
@ -238,15 +244,15 @@ static const char *jz4730_pwm0_groups[] = { "pwm0", };
|
||||
static const char *jz4730_pwm1_groups[] = { "pwm1", };
|
||||
|
||||
static const struct function_desc jz4730_functions[] = {
|
||||
{ "mmc", jz4730_mmc_groups, ARRAY_SIZE(jz4730_mmc_groups), },
|
||||
{ "uart0", jz4730_uart0_groups, ARRAY_SIZE(jz4730_uart0_groups), },
|
||||
{ "uart1", jz4730_uart1_groups, ARRAY_SIZE(jz4730_uart1_groups), },
|
||||
{ "uart2", jz4730_uart2_groups, ARRAY_SIZE(jz4730_uart2_groups), },
|
||||
{ "uart3", jz4730_uart3_groups, ARRAY_SIZE(jz4730_uart3_groups), },
|
||||
{ "lcd", jz4730_lcd_groups, ARRAY_SIZE(jz4730_lcd_groups), },
|
||||
{ "nand", jz4730_nand_groups, ARRAY_SIZE(jz4730_nand_groups), },
|
||||
{ "pwm0", jz4730_pwm0_groups, ARRAY_SIZE(jz4730_pwm0_groups), },
|
||||
{ "pwm1", jz4730_pwm1_groups, ARRAY_SIZE(jz4730_pwm1_groups), },
|
||||
INGENIC_PIN_FUNCTION("mmc", jz4730_mmc),
|
||||
INGENIC_PIN_FUNCTION("uart0", jz4730_uart0),
|
||||
INGENIC_PIN_FUNCTION("uart1", jz4730_uart1),
|
||||
INGENIC_PIN_FUNCTION("uart2", jz4730_uart2),
|
||||
INGENIC_PIN_FUNCTION("uart3", jz4730_uart3),
|
||||
INGENIC_PIN_FUNCTION("lcd", jz4730_lcd),
|
||||
INGENIC_PIN_FUNCTION("nand", jz4730_nand),
|
||||
INGENIC_PIN_FUNCTION("pwm0", jz4730_pwm0),
|
||||
INGENIC_PIN_FUNCTION("pwm1", jz4730_pwm1),
|
||||
};
|
||||
|
||||
static const struct ingenic_chip_info jz4730_chip_info = {
|
||||
@ -343,19 +349,19 @@ static const char *jz4740_pwm6_groups[] = { "pwm6", };
|
||||
static const char *jz4740_pwm7_groups[] = { "pwm7", };
|
||||
|
||||
static const struct function_desc jz4740_functions[] = {
|
||||
{ "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
|
||||
{ "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), },
|
||||
{ "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), },
|
||||
{ "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), },
|
||||
{ "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), },
|
||||
{ "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), },
|
||||
{ "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), },
|
||||
{ "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), },
|
||||
{ "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), },
|
||||
{ "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), },
|
||||
{ "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), },
|
||||
{ "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), },
|
||||
{ "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), },
|
||||
INGENIC_PIN_FUNCTION("mmc", jz4740_mmc),
|
||||
INGENIC_PIN_FUNCTION("uart0", jz4740_uart0),
|
||||
INGENIC_PIN_FUNCTION("uart1", jz4740_uart1),
|
||||
INGENIC_PIN_FUNCTION("lcd", jz4740_lcd),
|
||||
INGENIC_PIN_FUNCTION("nand", jz4740_nand),
|
||||
INGENIC_PIN_FUNCTION("pwm0", jz4740_pwm0),
|
||||
INGENIC_PIN_FUNCTION("pwm1", jz4740_pwm1),
|
||||
INGENIC_PIN_FUNCTION("pwm2", jz4740_pwm2),
|
||||
INGENIC_PIN_FUNCTION("pwm3", jz4740_pwm3),
|
||||
INGENIC_PIN_FUNCTION("pwm4", jz4740_pwm4),
|
||||
INGENIC_PIN_FUNCTION("pwm5", jz4740_pwm5),
|
||||
INGENIC_PIN_FUNCTION("pwm6", jz4740_pwm6),
|
||||
INGENIC_PIN_FUNCTION("pwm7", jz4740_pwm7),
|
||||
};
|
||||
|
||||
static const struct ingenic_chip_info jz4740_chip_info = {
|
||||
@ -447,17 +453,17 @@ static const char *jz4725b_pwm4_groups[] = { "pwm4", };
|
||||
static const char *jz4725b_pwm5_groups[] = { "pwm5", };
|
||||
|
||||
static const struct function_desc jz4725b_functions[] = {
|
||||
{ "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), },
|
||||
{ "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), },
|
||||
{ "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), },
|
||||
{ "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), },
|
||||
{ "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), },
|
||||
{ "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), },
|
||||
{ "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), },
|
||||
{ "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), },
|
||||
{ "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), },
|
||||
{ "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), },
|
||||
{ "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), },
|
||||
INGENIC_PIN_FUNCTION("mmc0", jz4725b_mmc0),
|
||||
INGENIC_PIN_FUNCTION("mmc1", jz4725b_mmc1),
|
||||
INGENIC_PIN_FUNCTION("uart", jz4725b_uart),
|
||||
INGENIC_PIN_FUNCTION("nand", jz4725b_nand),
|
||||
INGENIC_PIN_FUNCTION("pwm0", jz4725b_pwm0),
|
||||
INGENIC_PIN_FUNCTION("pwm1", jz4725b_pwm1),
|
||||
INGENIC_PIN_FUNCTION("pwm2", jz4725b_pwm2),
|
||||
INGENIC_PIN_FUNCTION("pwm3", jz4725b_pwm3),
|
||||
INGENIC_PIN_FUNCTION("pwm4", jz4725b_pwm4),
|
||||
INGENIC_PIN_FUNCTION("pwm5", jz4725b_pwm5),
|
||||
INGENIC_PIN_FUNCTION("lcd", jz4725b_lcd),
|
||||
};
|
||||
|
||||
static const struct ingenic_chip_info jz4725b_chip_info = {
|
||||
@ -579,22 +585,22 @@ static const char *jz4750_pwm4_groups[] = { "pwm4", };
|
||||
static const char *jz4750_pwm5_groups[] = { "pwm5", };
|
||||
|
||||
static const struct function_desc jz4750_functions[] = {
|
||||
{ "uart0", jz4750_uart0_groups, ARRAY_SIZE(jz4750_uart0_groups), },
|
||||
{ "uart1", jz4750_uart1_groups, ARRAY_SIZE(jz4750_uart1_groups), },
|
||||
{ "uart2", jz4750_uart2_groups, ARRAY_SIZE(jz4750_uart2_groups), },
|
||||
{ "uart3", jz4750_uart3_groups, ARRAY_SIZE(jz4750_uart3_groups), },
|
||||
{ "mmc0", jz4750_mmc0_groups, ARRAY_SIZE(jz4750_mmc0_groups), },
|
||||
{ "mmc1", jz4750_mmc1_groups, ARRAY_SIZE(jz4750_mmc1_groups), },
|
||||
{ "i2c", jz4750_i2c_groups, ARRAY_SIZE(jz4750_i2c_groups), },
|
||||
{ "cim", jz4750_cim_groups, ARRAY_SIZE(jz4750_cim_groups), },
|
||||
{ "lcd", jz4750_lcd_groups, ARRAY_SIZE(jz4750_lcd_groups), },
|
||||
{ "nand", jz4750_nand_groups, ARRAY_SIZE(jz4750_nand_groups), },
|
||||
{ "pwm0", jz4750_pwm0_groups, ARRAY_SIZE(jz4750_pwm0_groups), },
|
||||
{ "pwm1", jz4750_pwm1_groups, ARRAY_SIZE(jz4750_pwm1_groups), },
|
||||
{ "pwm2", jz4750_pwm2_groups, ARRAY_SIZE(jz4750_pwm2_groups), },
|
||||
{ "pwm3", jz4750_pwm3_groups, ARRAY_SIZE(jz4750_pwm3_groups), },
|
||||
{ "pwm4", jz4750_pwm4_groups, ARRAY_SIZE(jz4750_pwm4_groups), },
|
||||
{ "pwm5", jz4750_pwm5_groups, ARRAY_SIZE(jz4750_pwm5_groups), },
|
||||
INGENIC_PIN_FUNCTION("uart0", jz4750_uart0),
|
||||
INGENIC_PIN_FUNCTION("uart1", jz4750_uart1),
|
||||
INGENIC_PIN_FUNCTION("uart2", jz4750_uart2),
|
||||
INGENIC_PIN_FUNCTION("uart3", jz4750_uart3),
|
||||
INGENIC_PIN_FUNCTION("mmc0", jz4750_mmc0),
|
||||
INGENIC_PIN_FUNCTION("mmc1", jz4750_mmc1),
|
||||
INGENIC_PIN_FUNCTION("i2c", jz4750_i2c),
|
||||
INGENIC_PIN_FUNCTION("cim", jz4750_cim),
|
||||
INGENIC_PIN_FUNCTION("lcd", jz4750_lcd),
|
||||
INGENIC_PIN_FUNCTION("nand", jz4750_nand),
|
||||
INGENIC_PIN_FUNCTION("pwm0", jz4750_pwm0),
|
||||
INGENIC_PIN_FUNCTION("pwm1", jz4750_pwm1),
|
||||
INGENIC_PIN_FUNCTION("pwm2", jz4750_pwm2),
|
||||
INGENIC_PIN_FUNCTION("pwm3", jz4750_pwm3),
|
||||
INGENIC_PIN_FUNCTION("pwm4", jz4750_pwm4),
|
||||
INGENIC_PIN_FUNCTION("pwm5", jz4750_pwm5),
|
||||
};
|
||||
|
||||
static const struct ingenic_chip_info jz4750_chip_info = {
|
||||
@ -744,22 +750,22 @@ static const char *jz4755_pwm4_groups[] = { "pwm4", };
|
||||
static const char *jz4755_pwm5_groups[] = { "pwm5", };
|
||||
|
||||
static const struct function_desc jz4755_functions[] = {
|
||||
{ "uart0", jz4755_uart0_groups, ARRAY_SIZE(jz4755_uart0_groups), },
|
||||
{ "uart1", jz4755_uart1_groups, ARRAY_SIZE(jz4755_uart1_groups), },
|
||||
{ "uart2", jz4755_uart2_groups, ARRAY_SIZE(jz4755_uart2_groups), },
|
||||
{ "ssi", jz4755_ssi_groups, ARRAY_SIZE(jz4755_ssi_groups), },
|
||||
{ "mmc0", jz4755_mmc0_groups, ARRAY_SIZE(jz4755_mmc0_groups), },
|
||||
{ "mmc1", jz4755_mmc1_groups, ARRAY_SIZE(jz4755_mmc1_groups), },
|
||||
{ "i2c", jz4755_i2c_groups, ARRAY_SIZE(jz4755_i2c_groups), },
|
||||
{ "cim", jz4755_cim_groups, ARRAY_SIZE(jz4755_cim_groups), },
|
||||
{ "lcd", jz4755_lcd_groups, ARRAY_SIZE(jz4755_lcd_groups), },
|
||||
{ "nand", jz4755_nand_groups, ARRAY_SIZE(jz4755_nand_groups), },
|
||||
{ "pwm0", jz4755_pwm0_groups, ARRAY_SIZE(jz4755_pwm0_groups), },
|
||||
{ "pwm1", jz4755_pwm1_groups, ARRAY_SIZE(jz4755_pwm1_groups), },
|
||||
{ "pwm2", jz4755_pwm2_groups, ARRAY_SIZE(jz4755_pwm2_groups), },
|
||||
{ "pwm3", jz4755_pwm3_groups, ARRAY_SIZE(jz4755_pwm3_groups), },
|
||||
{ "pwm4", jz4755_pwm4_groups, ARRAY_SIZE(jz4755_pwm4_groups), },
|
||||
{ "pwm5", jz4755_pwm5_groups, ARRAY_SIZE(jz4755_pwm5_groups), },
|
||||
INGENIC_PIN_FUNCTION("uart0", jz4755_uart0),
|
||||
INGENIC_PIN_FUNCTION("uart1", jz4755_uart1),
|
||||
INGENIC_PIN_FUNCTION("uart2", jz4755_uart2),
|
||||
INGENIC_PIN_FUNCTION("ssi", jz4755_ssi),
|
||||
INGENIC_PIN_FUNCTION("mmc0", jz4755_mmc0),
|
||||
INGENIC_PIN_FUNCTION("mmc1", jz4755_mmc1),
|
||||
INGENIC_PIN_FUNCTION("i2c", jz4755_i2c),
|
||||
INGENIC_PIN_FUNCTION("cim", jz4755_cim),
|
||||
INGENIC_PIN_FUNCTION("lcd", jz4755_lcd),
|
||||
INGENIC_PIN_FUNCTION("nand", jz4755_nand),
|
||||
INGENIC_PIN_FUNCTION("pwm0", jz4755_pwm0),
|
||||
INGENIC_PIN_FUNCTION("pwm1", jz4755_pwm1),
|
||||
INGENIC_PIN_FUNCTION("pwm2", jz4755_pwm2),
|
||||
INGENIC_PIN_FUNCTION("pwm3", jz4755_pwm3),
|
||||
INGENIC_PIN_FUNCTION("pwm4", jz4755_pwm4),
|
||||
INGENIC_PIN_FUNCTION("pwm5", jz4755_pwm5),
|
||||
};
|
||||
|
||||
static const struct ingenic_chip_info jz4755_chip_info = {
|
||||
@ -1079,35 +1085,35 @@ static const char *jz4760_pwm7_groups[] = { "pwm7", };
|
||||
static const char *jz4760_otg_groups[] = { "otg-vbus", };
|
||||
|
||||
static const struct function_desc jz4760_functions[] = {
|
||||
{ "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), },
|
||||
{ "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), },
|
||||
{ "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), },
|
||||
{ "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), },
|
||||
{ "ssi0", jz4760_ssi0_groups, ARRAY_SIZE(jz4760_ssi0_groups), },
|
||||
{ "ssi1", jz4760_ssi1_groups, ARRAY_SIZE(jz4760_ssi1_groups), },
|
||||
{ "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), },
|
||||
{ "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), },
|
||||
{ "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), },
|
||||
{ "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), },
|
||||
{ "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), },
|
||||
{ "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), },
|
||||
{ "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), },
|
||||
{ "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), },
|
||||
{ "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), },
|
||||
{ "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), },
|
||||
{ "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), },
|
||||
{ "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), },
|
||||
{ "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), },
|
||||
{ "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), },
|
||||
{ "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), },
|
||||
{ "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), },
|
||||
{ "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), },
|
||||
{ "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), },
|
||||
{ "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), },
|
||||
{ "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), },
|
||||
{ "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), },
|
||||
{ "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), },
|
||||
{ "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), },
|
||||
INGENIC_PIN_FUNCTION("uart0", jz4760_uart0),
|
||||
INGENIC_PIN_FUNCTION("uart1", jz4760_uart1),
|
||||
INGENIC_PIN_FUNCTION("uart2", jz4760_uart2),
|
||||
INGENIC_PIN_FUNCTION("uart3", jz4760_uart3),
|
||||
INGENIC_PIN_FUNCTION("ssi0", jz4760_ssi0),
|
||||
INGENIC_PIN_FUNCTION("ssi1", jz4760_ssi1),
|
||||
INGENIC_PIN_FUNCTION("mmc0", jz4760_mmc0),
|
||||
INGENIC_PIN_FUNCTION("mmc1", jz4760_mmc1),
|
||||
INGENIC_PIN_FUNCTION("mmc2", jz4760_mmc2),
|
||||
INGENIC_PIN_FUNCTION("nemc", jz4760_nemc),
|
||||
INGENIC_PIN_FUNCTION("nemc-cs1", jz4760_cs1),
|
||||
INGENIC_PIN_FUNCTION("nemc-cs2", jz4760_cs2),
|
||||
INGENIC_PIN_FUNCTION("nemc-cs3", jz4760_cs3),
|
||||
INGENIC_PIN_FUNCTION("nemc-cs4", jz4760_cs4),
|
||||
INGENIC_PIN_FUNCTION("nemc-cs5", jz4760_cs5),
|
||||
INGENIC_PIN_FUNCTION("nemc-cs6", jz4760_cs6),
|
||||
INGENIC_PIN_FUNCTION("i2c0", jz4760_i2c0),
|
||||
INGENIC_PIN_FUNCTION("i2c1", jz4760_i2c1),
|
||||
INGENIC_PIN_FUNCTION("cim", jz4760_cim),
|
||||
INGENIC_PIN_FUNCTION("lcd", jz4760_lcd),
|
||||
INGENIC_PIN_FUNCTION("pwm0", jz4760_pwm0),
|
||||
INGENIC_PIN_FUNCTION("pwm1", jz4760_pwm1),
|
||||
INGENIC_PIN_FUNCTION("pwm2", jz4760_pwm2),
|
||||
INGENIC_PIN_FUNCTION("pwm3", jz4760_pwm3),
|
||||
INGENIC_PIN_FUNCTION("pwm4", jz4760_pwm4),
|
||||
INGENIC_PIN_FUNCTION("pwm5", jz4760_pwm5),
|
||||
INGENIC_PIN_FUNCTION("pwm6", jz4760_pwm6),
|
||||
INGENIC_PIN_FUNCTION("pwm7", jz4760_pwm7),
|
||||
INGENIC_PIN_FUNCTION("otg", jz4760_otg),
|
||||
};
|
||||
|
||||
static const struct ingenic_chip_info jz4760_chip_info = {
|
||||
@ -1417,37 +1423,37 @@ static const char *jz4770_pwm7_groups[] = { "pwm7", };
|
||||
static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
|
||||
|
||||
static const struct function_desc jz4770_functions[] = {
|
||||
{ "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
|
||||
{ "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
|
||||
{ "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), },
|
||||
{ "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
|
||||
{ "ssi0", jz4770_ssi0_groups, ARRAY_SIZE(jz4770_ssi0_groups), },
|
||||
{ "ssi1", jz4770_ssi1_groups, ARRAY_SIZE(jz4770_ssi1_groups), },
|
||||
{ "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
|
||||
{ "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
|
||||
{ "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), },
|
||||
{ "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
|
||||
{ "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
|
||||
{ "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
|
||||
{ "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
|
||||
{ "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
|
||||
{ "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
|
||||
{ "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
|
||||
{ "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
|
||||
{ "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
|
||||
{ "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
|
||||
{ "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), },
|
||||
{ "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
|
||||
{ "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
|
||||
{ "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
|
||||
{ "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
|
||||
{ "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
|
||||
{ "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
|
||||
{ "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
|
||||
{ "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
|
||||
{ "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
|
||||
{ "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), },
|
||||
{ "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), },
|
||||
INGENIC_PIN_FUNCTION("uart0", jz4770_uart0),
|
||||
INGENIC_PIN_FUNCTION("uart1", jz4770_uart1),
|
||||
INGENIC_PIN_FUNCTION("uart2", jz4770_uart2),
|
||||
INGENIC_PIN_FUNCTION("uart3", jz4770_uart3),
|
||||
INGENIC_PIN_FUNCTION("ssi0", jz4770_ssi0),
|
||||
INGENIC_PIN_FUNCTION("ssi1", jz4770_ssi1),
|
||||
INGENIC_PIN_FUNCTION("mmc0", jz4770_mmc0),
|
||||
INGENIC_PIN_FUNCTION("mmc1", jz4770_mmc1),
|
||||
INGENIC_PIN_FUNCTION("mmc2", jz4770_mmc2),
|
||||
INGENIC_PIN_FUNCTION("nemc", jz4770_nemc),
|
||||
INGENIC_PIN_FUNCTION("nemc-cs1", jz4770_cs1),
|
||||
INGENIC_PIN_FUNCTION("nemc-cs2", jz4770_cs2),
|
||||
INGENIC_PIN_FUNCTION("nemc-cs3", jz4770_cs3),
|
||||
INGENIC_PIN_FUNCTION("nemc-cs4", jz4770_cs4),
|
||||
INGENIC_PIN_FUNCTION("nemc-cs5", jz4770_cs5),
|
||||
INGENIC_PIN_FUNCTION("nemc-cs6", jz4770_cs6),
|
||||
INGENIC_PIN_FUNCTION("i2c0", jz4770_i2c0),
|
||||
INGENIC_PIN_FUNCTION("i2c1", jz4770_i2c1),
|
||||
INGENIC_PIN_FUNCTION("i2c2", jz4770_i2c2),
|
||||
INGENIC_PIN_FUNCTION("cim", jz4770_cim),
|
||||
INGENIC_PIN_FUNCTION("lcd", jz4770_lcd),
|
||||
INGENIC_PIN_FUNCTION("pwm0", jz4770_pwm0),
|
||||
INGENIC_PIN_FUNCTION("pwm1", jz4770_pwm1),
|
||||
INGENIC_PIN_FUNCTION("pwm2", jz4770_pwm2),
|
||||
INGENIC_PIN_FUNCTION("pwm3", jz4770_pwm3),
|
||||
INGENIC_PIN_FUNCTION("pwm4", jz4770_pwm4),
|
||||
INGENIC_PIN_FUNCTION("pwm5", jz4770_pwm5),
|
||||
INGENIC_PIN_FUNCTION("pwm6", jz4770_pwm6),
|
||||
INGENIC_PIN_FUNCTION("pwm7", jz4770_pwm7),
|
||||
INGENIC_PIN_FUNCTION("mac", jz4770_mac),
|
||||
INGENIC_PIN_FUNCTION("otg", jz4760_otg),
|
||||
};
|
||||
|
||||
static const struct ingenic_chip_info jz4770_chip_info = {
|
||||
@ -1696,31 +1702,31 @@ static const char *jz4775_mac_groups[] = {
|
||||
static const char *jz4775_otg_groups[] = { "otg-vbus", };
|
||||
|
||||
static const struct function_desc jz4775_functions[] = {
|
||||
{ "uart0", jz4775_uart0_groups, ARRAY_SIZE(jz4775_uart0_groups), },
|
||||
{ "uart1", jz4775_uart1_groups, ARRAY_SIZE(jz4775_uart1_groups), },
|
||||
{ "uart2", jz4775_uart2_groups, ARRAY_SIZE(jz4775_uart2_groups), },
|
||||
{ "uart3", jz4775_uart3_groups, ARRAY_SIZE(jz4775_uart3_groups), },
|
||||
{ "ssi", jz4775_ssi_groups, ARRAY_SIZE(jz4775_ssi_groups), },
|
||||
{ "mmc0", jz4775_mmc0_groups, ARRAY_SIZE(jz4775_mmc0_groups), },
|
||||
{ "mmc1", jz4775_mmc1_groups, ARRAY_SIZE(jz4775_mmc1_groups), },
|
||||
{ "mmc2", jz4775_mmc2_groups, ARRAY_SIZE(jz4775_mmc2_groups), },
|
||||
{ "nemc", jz4775_nemc_groups, ARRAY_SIZE(jz4775_nemc_groups), },
|
||||
{ "nemc-cs1", jz4775_cs1_groups, ARRAY_SIZE(jz4775_cs1_groups), },
|
||||
{ "nemc-cs2", jz4775_cs2_groups, ARRAY_SIZE(jz4775_cs2_groups), },
|
||||
{ "nemc-cs3", jz4775_cs3_groups, ARRAY_SIZE(jz4775_cs3_groups), },
|
||||
{ "i2c0", jz4775_i2c0_groups, ARRAY_SIZE(jz4775_i2c0_groups), },
|
||||
{ "i2c1", jz4775_i2c1_groups, ARRAY_SIZE(jz4775_i2c1_groups), },
|
||||
{ "i2c2", jz4775_i2c2_groups, ARRAY_SIZE(jz4775_i2c2_groups), },
|
||||
{ "i2s", jz4775_i2s_groups, ARRAY_SIZE(jz4775_i2s_groups), },
|
||||
{ "dmic", jz4775_dmic_groups, ARRAY_SIZE(jz4775_dmic_groups), },
|
||||
{ "cim", jz4775_cim_groups, ARRAY_SIZE(jz4775_cim_groups), },
|
||||
{ "lcd", jz4775_lcd_groups, ARRAY_SIZE(jz4775_lcd_groups), },
|
||||
{ "pwm0", jz4775_pwm0_groups, ARRAY_SIZE(jz4775_pwm0_groups), },
|
||||
{ "pwm1", jz4775_pwm1_groups, ARRAY_SIZE(jz4775_pwm1_groups), },
|
||||
{ "pwm2", jz4775_pwm2_groups, ARRAY_SIZE(jz4775_pwm2_groups), },
|
||||
{ "pwm3", jz4775_pwm3_groups, ARRAY_SIZE(jz4775_pwm3_groups), },
|
||||
{ "mac", jz4775_mac_groups, ARRAY_SIZE(jz4775_mac_groups), },
|
||||
{ "otg", jz4775_otg_groups, ARRAY_SIZE(jz4775_otg_groups), },
|
||||
INGENIC_PIN_FUNCTION("uart0", jz4775_uart0),
|
||||
INGENIC_PIN_FUNCTION("uart1", jz4775_uart1),
|
||||
INGENIC_PIN_FUNCTION("uart2", jz4775_uart2),
|
||||
INGENIC_PIN_FUNCTION("uart3", jz4775_uart3),
|
||||
INGENIC_PIN_FUNCTION("ssi", jz4775_ssi),
|
||||
INGENIC_PIN_FUNCTION("mmc0", jz4775_mmc0),
|
||||
INGENIC_PIN_FUNCTION("mmc1", jz4775_mmc1),
|
||||
INGENIC_PIN_FUNCTION("mmc2", jz4775_mmc2),
|
||||
INGENIC_PIN_FUNCTION("nemc", jz4775_nemc),
|
||||
INGENIC_PIN_FUNCTION("nemc-cs1", jz4775_cs1),
|
||||
INGENIC_PIN_FUNCTION("nemc-cs2", jz4775_cs2),
|
||||
INGENIC_PIN_FUNCTION("nemc-cs3", jz4775_cs3),
|
||||
INGENIC_PIN_FUNCTION("i2c0", jz4775_i2c0),
|
||||
INGENIC_PIN_FUNCTION("i2c1", jz4775_i2c1),
|
||||
INGENIC_PIN_FUNCTION("i2c2", jz4775_i2c2),
|
||||
INGENIC_PIN_FUNCTION("i2s", jz4775_i2s),
|
||||
INGENIC_PIN_FUNCTION("dmic", jz4775_dmic),
|
||||
INGENIC_PIN_FUNCTION("cim", jz4775_cim),
|
||||
INGENIC_PIN_FUNCTION("lcd", jz4775_lcd),
|
||||
INGENIC_PIN_FUNCTION("pwm0", jz4775_pwm0),
|
||||
INGENIC_PIN_FUNCTION("pwm1", jz4775_pwm1),
|
||||
INGENIC_PIN_FUNCTION("pwm2", jz4775_pwm2),
|
||||
INGENIC_PIN_FUNCTION("pwm3", jz4775_pwm3),
|
||||
INGENIC_PIN_FUNCTION("mac", jz4775_mac),
|
||||
INGENIC_PIN_FUNCTION("otg", jz4775_otg),
|
||||
};
|
||||
|
||||
static const struct ingenic_chip_info jz4775_chip_info = {
|
||||
@ -1949,42 +1955,41 @@ static const char *jz4780_cim_groups[] = { "cim-data", };
|
||||
static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", };
|
||||
|
||||
static const struct function_desc jz4780_functions[] = {
|
||||
{ "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
|
||||
{ "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
|
||||
{ "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), },
|
||||
{ "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
|
||||
{ "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), },
|
||||
{ "ssi0", jz4780_ssi0_groups, ARRAY_SIZE(jz4780_ssi0_groups), },
|
||||
{ "ssi1", jz4780_ssi1_groups, ARRAY_SIZE(jz4780_ssi1_groups), },
|
||||
{ "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), },
|
||||
{ "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), },
|
||||
{ "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), },
|
||||
{ "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), },
|
||||
{ "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
|
||||
{ "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
|
||||
{ "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
|
||||
{ "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
|
||||
{ "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
|
||||
{ "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
|
||||
{ "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
|
||||
{ "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
|
||||
{ "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
|
||||
{ "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), },
|
||||
{ "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), },
|
||||
{ "i2s", jz4780_i2s_groups, ARRAY_SIZE(jz4780_i2s_groups), },
|
||||
{ "dmic", jz4780_dmic_groups, ARRAY_SIZE(jz4780_dmic_groups), },
|
||||
{ "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), },
|
||||
{ "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
|
||||
{ "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
|
||||
{ "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
|
||||
{ "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
|
||||
{ "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
|
||||
{ "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
|
||||
{ "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
|
||||
{ "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
|
||||
{ "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
|
||||
{ "hdmi-ddc", jz4780_hdmi_ddc_groups,
|
||||
ARRAY_SIZE(jz4780_hdmi_ddc_groups), },
|
||||
INGENIC_PIN_FUNCTION("uart0", jz4770_uart0),
|
||||
INGENIC_PIN_FUNCTION("uart1", jz4770_uart1),
|
||||
INGENIC_PIN_FUNCTION("uart2", jz4780_uart2),
|
||||
INGENIC_PIN_FUNCTION("uart3", jz4770_uart3),
|
||||
INGENIC_PIN_FUNCTION("uart4", jz4780_uart4),
|
||||
INGENIC_PIN_FUNCTION("ssi0", jz4780_ssi0),
|
||||
INGENIC_PIN_FUNCTION("ssi1", jz4780_ssi1),
|
||||
INGENIC_PIN_FUNCTION("mmc0", jz4780_mmc0),
|
||||
INGENIC_PIN_FUNCTION("mmc1", jz4780_mmc1),
|
||||
INGENIC_PIN_FUNCTION("mmc2", jz4780_mmc2),
|
||||
INGENIC_PIN_FUNCTION("nemc", jz4780_nemc),
|
||||
INGENIC_PIN_FUNCTION("nemc-cs1", jz4770_cs1),
|
||||
INGENIC_PIN_FUNCTION("nemc-cs2", jz4770_cs2),
|
||||
INGENIC_PIN_FUNCTION("nemc-cs3", jz4770_cs3),
|
||||
INGENIC_PIN_FUNCTION("nemc-cs4", jz4770_cs4),
|
||||
INGENIC_PIN_FUNCTION("nemc-cs5", jz4770_cs5),
|
||||
INGENIC_PIN_FUNCTION("nemc-cs6", jz4770_cs6),
|
||||
INGENIC_PIN_FUNCTION("i2c0", jz4770_i2c0),
|
||||
INGENIC_PIN_FUNCTION("i2c1", jz4770_i2c1),
|
||||
INGENIC_PIN_FUNCTION("i2c2", jz4770_i2c2),
|
||||
INGENIC_PIN_FUNCTION("i2c3", jz4780_i2c3),
|
||||
INGENIC_PIN_FUNCTION("i2c4", jz4780_i2c4),
|
||||
INGENIC_PIN_FUNCTION("i2s", jz4780_i2s),
|
||||
INGENIC_PIN_FUNCTION("dmic", jz4780_dmic),
|
||||
INGENIC_PIN_FUNCTION("cim", jz4780_cim),
|
||||
INGENIC_PIN_FUNCTION("lcd", jz4770_lcd),
|
||||
INGENIC_PIN_FUNCTION("pwm0", jz4770_pwm0),
|
||||
INGENIC_PIN_FUNCTION("pwm1", jz4770_pwm1),
|
||||
INGENIC_PIN_FUNCTION("pwm2", jz4770_pwm2),
|
||||
INGENIC_PIN_FUNCTION("pwm3", jz4770_pwm3),
|
||||
INGENIC_PIN_FUNCTION("pwm4", jz4770_pwm4),
|
||||
INGENIC_PIN_FUNCTION("pwm5", jz4770_pwm5),
|
||||
INGENIC_PIN_FUNCTION("pwm6", jz4770_pwm6),
|
||||
INGENIC_PIN_FUNCTION("pwm7", jz4770_pwm7),
|
||||
INGENIC_PIN_FUNCTION("hdmi-ddc", jz4780_hdmi_ddc),
|
||||
};
|
||||
|
||||
static const struct ingenic_chip_info jz4780_chip_info = {
|
||||
@ -2185,29 +2190,29 @@ static const char *x1000_pwm4_groups[] = { "pwm4", };
|
||||
static const char *x1000_mac_groups[] = { "mac", };
|
||||
|
||||
static const struct function_desc x1000_functions[] = {
|
||||
{ "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), },
|
||||
{ "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), },
|
||||
{ "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), },
|
||||
{ "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
|
||||
{ "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), },
|
||||
{ "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), },
|
||||
{ "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), },
|
||||
{ "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), },
|
||||
{ "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), },
|
||||
{ "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), },
|
||||
{ "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), },
|
||||
{ "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), },
|
||||
{ "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), },
|
||||
{ "i2s", x1000_i2s_groups, ARRAY_SIZE(x1000_i2s_groups), },
|
||||
{ "dmic", x1000_dmic_groups, ARRAY_SIZE(x1000_dmic_groups), },
|
||||
{ "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), },
|
||||
{ "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), },
|
||||
{ "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), },
|
||||
{ "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), },
|
||||
{ "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), },
|
||||
{ "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), },
|
||||
{ "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), },
|
||||
{ "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), },
|
||||
INGENIC_PIN_FUNCTION("uart0", x1000_uart0),
|
||||
INGENIC_PIN_FUNCTION("uart1", x1000_uart1),
|
||||
INGENIC_PIN_FUNCTION("uart2", x1000_uart2),
|
||||
INGENIC_PIN_FUNCTION("sfc", x1000_sfc),
|
||||
INGENIC_PIN_FUNCTION("ssi", x1000_ssi),
|
||||
INGENIC_PIN_FUNCTION("mmc0", x1000_mmc0),
|
||||
INGENIC_PIN_FUNCTION("mmc1", x1000_mmc1),
|
||||
INGENIC_PIN_FUNCTION("emc", x1000_emc),
|
||||
INGENIC_PIN_FUNCTION("emc-cs1", x1000_cs1),
|
||||
INGENIC_PIN_FUNCTION("emc-cs2", x1000_cs2),
|
||||
INGENIC_PIN_FUNCTION("i2c0", x1000_i2c0),
|
||||
INGENIC_PIN_FUNCTION("i2c1", x1000_i2c1),
|
||||
INGENIC_PIN_FUNCTION("i2c2", x1000_i2c2),
|
||||
INGENIC_PIN_FUNCTION("i2s", x1000_i2s),
|
||||
INGENIC_PIN_FUNCTION("dmic", x1000_dmic),
|
||||
INGENIC_PIN_FUNCTION("cim", x1000_cim),
|
||||
INGENIC_PIN_FUNCTION("lcd", x1000_lcd),
|
||||
INGENIC_PIN_FUNCTION("pwm0", x1000_pwm0),
|
||||
INGENIC_PIN_FUNCTION("pwm1", x1000_pwm1),
|
||||
INGENIC_PIN_FUNCTION("pwm2", x1000_pwm2),
|
||||
INGENIC_PIN_FUNCTION("pwm3", x1000_pwm3),
|
||||
INGENIC_PIN_FUNCTION("pwm4", x1000_pwm4),
|
||||
INGENIC_PIN_FUNCTION("mac", x1000_mac),
|
||||
};
|
||||
|
||||
static const struct regmap_range x1000_access_ranges[] = {
|
||||
@ -2315,22 +2320,22 @@ static const char *x1500_pwm3_groups[] = { "pwm3", };
|
||||
static const char *x1500_pwm4_groups[] = { "pwm4", };
|
||||
|
||||
static const struct function_desc x1500_functions[] = {
|
||||
{ "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), },
|
||||
{ "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), },
|
||||
{ "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), },
|
||||
{ "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
|
||||
{ "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), },
|
||||
{ "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), },
|
||||
{ "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), },
|
||||
{ "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), },
|
||||
{ "i2s", x1500_i2s_groups, ARRAY_SIZE(x1500_i2s_groups), },
|
||||
{ "dmic", x1500_dmic_groups, ARRAY_SIZE(x1500_dmic_groups), },
|
||||
{ "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), },
|
||||
{ "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), },
|
||||
{ "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), },
|
||||
{ "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), },
|
||||
{ "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), },
|
||||
{ "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), },
|
||||
INGENIC_PIN_FUNCTION("uart0", x1500_uart0),
|
||||
INGENIC_PIN_FUNCTION("uart1", x1500_uart1),
|
||||
INGENIC_PIN_FUNCTION("uart2", x1500_uart2),
|
||||
INGENIC_PIN_FUNCTION("sfc", x1000_sfc),
|
||||
INGENIC_PIN_FUNCTION("mmc", x1500_mmc),
|
||||
INGENIC_PIN_FUNCTION("i2c0", x1500_i2c0),
|
||||
INGENIC_PIN_FUNCTION("i2c1", x1500_i2c1),
|
||||
INGENIC_PIN_FUNCTION("i2c2", x1500_i2c2),
|
||||
INGENIC_PIN_FUNCTION("i2s", x1500_i2s),
|
||||
INGENIC_PIN_FUNCTION("dmic", x1500_dmic),
|
||||
INGENIC_PIN_FUNCTION("cim", x1500_cim),
|
||||
INGENIC_PIN_FUNCTION("pwm0", x1500_pwm0),
|
||||
INGENIC_PIN_FUNCTION("pwm1", x1500_pwm1),
|
||||
INGENIC_PIN_FUNCTION("pwm2", x1500_pwm2),
|
||||
INGENIC_PIN_FUNCTION("pwm3", x1500_pwm3),
|
||||
INGENIC_PIN_FUNCTION("pwm4", x1500_pwm4),
|
||||
};
|
||||
|
||||
static const struct ingenic_chip_info x1500_chip_info = {
|
||||
@ -2526,28 +2531,28 @@ static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", };
|
||||
static const char *x1830_mac_groups[] = { "mac", };
|
||||
|
||||
static const struct function_desc x1830_functions[] = {
|
||||
{ "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), },
|
||||
{ "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), },
|
||||
{ "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), },
|
||||
{ "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), },
|
||||
{ "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), },
|
||||
{ "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), },
|
||||
{ "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), },
|
||||
{ "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), },
|
||||
{ "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), },
|
||||
{ "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), },
|
||||
{ "i2s", x1830_i2s_groups, ARRAY_SIZE(x1830_i2s_groups), },
|
||||
{ "dmic", x1830_dmic_groups, ARRAY_SIZE(x1830_dmic_groups), },
|
||||
{ "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), },
|
||||
{ "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), },
|
||||
{ "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), },
|
||||
{ "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), },
|
||||
{ "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), },
|
||||
{ "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), },
|
||||
{ "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), },
|
||||
{ "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), },
|
||||
{ "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), },
|
||||
{ "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), },
|
||||
INGENIC_PIN_FUNCTION("uart0", x1830_uart0),
|
||||
INGENIC_PIN_FUNCTION("uart1", x1830_uart1),
|
||||
INGENIC_PIN_FUNCTION("sfc", x1830_sfc),
|
||||
INGENIC_PIN_FUNCTION("ssi0", x1830_ssi0),
|
||||
INGENIC_PIN_FUNCTION("ssi1", x1830_ssi1),
|
||||
INGENIC_PIN_FUNCTION("mmc0", x1830_mmc0),
|
||||
INGENIC_PIN_FUNCTION("mmc1", x1830_mmc1),
|
||||
INGENIC_PIN_FUNCTION("i2c0", x1830_i2c0),
|
||||
INGENIC_PIN_FUNCTION("i2c1", x1830_i2c1),
|
||||
INGENIC_PIN_FUNCTION("i2c2", x1830_i2c2),
|
||||
INGENIC_PIN_FUNCTION("i2s", x1830_i2s),
|
||||
INGENIC_PIN_FUNCTION("dmic", x1830_dmic),
|
||||
INGENIC_PIN_FUNCTION("lcd", x1830_lcd),
|
||||
INGENIC_PIN_FUNCTION("pwm0", x1830_pwm0),
|
||||
INGENIC_PIN_FUNCTION("pwm1", x1830_pwm1),
|
||||
INGENIC_PIN_FUNCTION("pwm2", x1830_pwm2),
|
||||
INGENIC_PIN_FUNCTION("pwm3", x1830_pwm3),
|
||||
INGENIC_PIN_FUNCTION("pwm4", x1830_pwm4),
|
||||
INGENIC_PIN_FUNCTION("pwm5", x1830_pwm5),
|
||||
INGENIC_PIN_FUNCTION("pwm6", x1830_pwm6),
|
||||
INGENIC_PIN_FUNCTION("pwm7", x1830_pwm7),
|
||||
INGENIC_PIN_FUNCTION("mac", x1830_mac),
|
||||
};
|
||||
|
||||
static const struct regmap_range x1830_access_ranges[] = {
|
||||
@ -2972,56 +2977,56 @@ static const char *x2000_mac1_groups[] = { "mac1-rmii", "mac1-rgmii", };
|
||||
static const char *x2000_otg_groups[] = { "otg-vbus", };
|
||||
|
||||
static const struct function_desc x2000_functions[] = {
|
||||
{ "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), },
|
||||
{ "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), },
|
||||
{ "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), },
|
||||
{ "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), },
|
||||
{ "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), },
|
||||
{ "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), },
|
||||
{ "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), },
|
||||
{ "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), },
|
||||
{ "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), },
|
||||
{ "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), },
|
||||
{ "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), },
|
||||
{ "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), },
|
||||
{ "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), },
|
||||
{ "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), },
|
||||
{ "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), },
|
||||
{ "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), },
|
||||
{ "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), },
|
||||
{ "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), },
|
||||
{ "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), },
|
||||
{ "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), },
|
||||
{ "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), },
|
||||
{ "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), },
|
||||
{ "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), },
|
||||
{ "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), },
|
||||
{ "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), },
|
||||
{ "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), },
|
||||
{ "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), },
|
||||
{ "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), },
|
||||
{ "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), },
|
||||
{ "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), },
|
||||
{ "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), },
|
||||
{ "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), },
|
||||
{ "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), },
|
||||
{ "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), },
|
||||
{ "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), },
|
||||
{ "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), },
|
||||
{ "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), },
|
||||
{ "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), },
|
||||
{ "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), },
|
||||
{ "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), },
|
||||
{ "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), },
|
||||
{ "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), },
|
||||
{ "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), },
|
||||
{ "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), },
|
||||
{ "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), },
|
||||
{ "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), },
|
||||
{ "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), },
|
||||
{ "mac0", x2000_mac0_groups, ARRAY_SIZE(x2000_mac0_groups), },
|
||||
{ "mac1", x2000_mac1_groups, ARRAY_SIZE(x2000_mac1_groups), },
|
||||
{ "otg", x2000_otg_groups, ARRAY_SIZE(x2000_otg_groups), },
|
||||
INGENIC_PIN_FUNCTION("uart0", x2000_uart0),
|
||||
INGENIC_PIN_FUNCTION("uart1", x2000_uart1),
|
||||
INGENIC_PIN_FUNCTION("uart2", x2000_uart2),
|
||||
INGENIC_PIN_FUNCTION("uart3", x2000_uart3),
|
||||
INGENIC_PIN_FUNCTION("uart4", x2000_uart4),
|
||||
INGENIC_PIN_FUNCTION("uart5", x2000_uart5),
|
||||
INGENIC_PIN_FUNCTION("uart6", x2000_uart6),
|
||||
INGENIC_PIN_FUNCTION("uart7", x2000_uart7),
|
||||
INGENIC_PIN_FUNCTION("uart8", x2000_uart8),
|
||||
INGENIC_PIN_FUNCTION("uart9", x2000_uart9),
|
||||
INGENIC_PIN_FUNCTION("sfc", x2000_sfc),
|
||||
INGENIC_PIN_FUNCTION("ssi0", x2000_ssi0),
|
||||
INGENIC_PIN_FUNCTION("ssi1", x2000_ssi1),
|
||||
INGENIC_PIN_FUNCTION("mmc0", x2000_mmc0),
|
||||
INGENIC_PIN_FUNCTION("mmc1", x2000_mmc1),
|
||||
INGENIC_PIN_FUNCTION("mmc2", x2000_mmc2),
|
||||
INGENIC_PIN_FUNCTION("emc", x2000_emc),
|
||||
INGENIC_PIN_FUNCTION("emc-cs1", x2000_cs1),
|
||||
INGENIC_PIN_FUNCTION("emc-cs2", x2000_cs2),
|
||||
INGENIC_PIN_FUNCTION("i2c0", x2000_i2c0),
|
||||
INGENIC_PIN_FUNCTION("i2c1", x2000_i2c1),
|
||||
INGENIC_PIN_FUNCTION("i2c2", x2000_i2c2),
|
||||
INGENIC_PIN_FUNCTION("i2c3", x2000_i2c3),
|
||||
INGENIC_PIN_FUNCTION("i2c4", x2000_i2c4),
|
||||
INGENIC_PIN_FUNCTION("i2c5", x2000_i2c5),
|
||||
INGENIC_PIN_FUNCTION("i2s1", x2000_i2s1),
|
||||
INGENIC_PIN_FUNCTION("i2s2", x2000_i2s2),
|
||||
INGENIC_PIN_FUNCTION("i2s3", x2000_i2s3),
|
||||
INGENIC_PIN_FUNCTION("dmic", x2000_dmic),
|
||||
INGENIC_PIN_FUNCTION("cim", x2000_cim),
|
||||
INGENIC_PIN_FUNCTION("lcd", x2000_lcd),
|
||||
INGENIC_PIN_FUNCTION("pwm0", x2000_pwm0),
|
||||
INGENIC_PIN_FUNCTION("pwm1", x2000_pwm1),
|
||||
INGENIC_PIN_FUNCTION("pwm2", x2000_pwm2),
|
||||
INGENIC_PIN_FUNCTION("pwm3", x2000_pwm3),
|
||||
INGENIC_PIN_FUNCTION("pwm4", x2000_pwm4),
|
||||
INGENIC_PIN_FUNCTION("pwm5", x2000_pwm5),
|
||||
INGENIC_PIN_FUNCTION("pwm6", x2000_pwm6),
|
||||
INGENIC_PIN_FUNCTION("pwm7", x2000_pwm7),
|
||||
INGENIC_PIN_FUNCTION("pwm8", x2000_pwm8),
|
||||
INGENIC_PIN_FUNCTION("pwm9", x2000_pwm9),
|
||||
INGENIC_PIN_FUNCTION("pwm10", x2000_pwm10),
|
||||
INGENIC_PIN_FUNCTION("pwm11", x2000_pwm11),
|
||||
INGENIC_PIN_FUNCTION("pwm12", x2000_pwm12),
|
||||
INGENIC_PIN_FUNCTION("pwm13", x2000_pwm13),
|
||||
INGENIC_PIN_FUNCTION("pwm14", x2000_pwm14),
|
||||
INGENIC_PIN_FUNCTION("pwm15", x2000_pwm15),
|
||||
INGENIC_PIN_FUNCTION("mac0", x2000_mac0),
|
||||
INGENIC_PIN_FUNCTION("mac1", x2000_mac1),
|
||||
INGENIC_PIN_FUNCTION("otg", x2000_otg),
|
||||
};
|
||||
|
||||
static const struct regmap_range x2000_access_ranges[] = {
|
||||
@ -3196,54 +3201,54 @@ static const struct group_desc x2100_groups[] = {
|
||||
static const char *x2100_mac_groups[] = { "mac", };
|
||||
|
||||
static const struct function_desc x2100_functions[] = {
|
||||
{ "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), },
|
||||
{ "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), },
|
||||
{ "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), },
|
||||
{ "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), },
|
||||
{ "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), },
|
||||
{ "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), },
|
||||
{ "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), },
|
||||
{ "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), },
|
||||
{ "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), },
|
||||
{ "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), },
|
||||
{ "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), },
|
||||
{ "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), },
|
||||
{ "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), },
|
||||
{ "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), },
|
||||
{ "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), },
|
||||
{ "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), },
|
||||
{ "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), },
|
||||
{ "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), },
|
||||
{ "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), },
|
||||
{ "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), },
|
||||
{ "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), },
|
||||
{ "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), },
|
||||
{ "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), },
|
||||
{ "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), },
|
||||
{ "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), },
|
||||
{ "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), },
|
||||
{ "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), },
|
||||
{ "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), },
|
||||
{ "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), },
|
||||
{ "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), },
|
||||
{ "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), },
|
||||
{ "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), },
|
||||
{ "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), },
|
||||
{ "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), },
|
||||
{ "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), },
|
||||
{ "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), },
|
||||
{ "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), },
|
||||
{ "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), },
|
||||
{ "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), },
|
||||
{ "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), },
|
||||
{ "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), },
|
||||
{ "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), },
|
||||
{ "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), },
|
||||
{ "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), },
|
||||
{ "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), },
|
||||
{ "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), },
|
||||
{ "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), },
|
||||
{ "mac", x2100_mac_groups, ARRAY_SIZE(x2100_mac_groups), },
|
||||
INGENIC_PIN_FUNCTION("uart0", x2000_uart0),
|
||||
INGENIC_PIN_FUNCTION("uart1", x2000_uart1),
|
||||
INGENIC_PIN_FUNCTION("uart2", x2000_uart2),
|
||||
INGENIC_PIN_FUNCTION("uart3", x2000_uart3),
|
||||
INGENIC_PIN_FUNCTION("uart4", x2000_uart4),
|
||||
INGENIC_PIN_FUNCTION("uart5", x2000_uart5),
|
||||
INGENIC_PIN_FUNCTION("uart6", x2000_uart6),
|
||||
INGENIC_PIN_FUNCTION("uart7", x2000_uart7),
|
||||
INGENIC_PIN_FUNCTION("uart8", x2000_uart8),
|
||||
INGENIC_PIN_FUNCTION("uart9", x2000_uart9),
|
||||
INGENIC_PIN_FUNCTION("sfc", x2000_sfc),
|
||||
INGENIC_PIN_FUNCTION("ssi0", x2000_ssi0),
|
||||
INGENIC_PIN_FUNCTION("ssi1", x2000_ssi1),
|
||||
INGENIC_PIN_FUNCTION("mmc0", x2000_mmc0),
|
||||
INGENIC_PIN_FUNCTION("mmc1", x2000_mmc1),
|
||||
INGENIC_PIN_FUNCTION("mmc2", x2000_mmc2),
|
||||
INGENIC_PIN_FUNCTION("emc", x2000_emc),
|
||||
INGENIC_PIN_FUNCTION("emc-cs1", x2000_cs1),
|
||||
INGENIC_PIN_FUNCTION("emc-cs2", x2000_cs2),
|
||||
INGENIC_PIN_FUNCTION("i2c0", x2000_i2c0),
|
||||
INGENIC_PIN_FUNCTION("i2c1", x2000_i2c1),
|
||||
INGENIC_PIN_FUNCTION("i2c2", x2000_i2c2),
|
||||
INGENIC_PIN_FUNCTION("i2c3", x2000_i2c3),
|
||||
INGENIC_PIN_FUNCTION("i2c4", x2000_i2c4),
|
||||
INGENIC_PIN_FUNCTION("i2c5", x2000_i2c5),
|
||||
INGENIC_PIN_FUNCTION("i2s1", x2000_i2s1),
|
||||
INGENIC_PIN_FUNCTION("i2s2", x2000_i2s2),
|
||||
INGENIC_PIN_FUNCTION("i2s3", x2000_i2s3),
|
||||
INGENIC_PIN_FUNCTION("dmic", x2000_dmic),
|
||||
INGENIC_PIN_FUNCTION("cim", x2000_cim),
|
||||
INGENIC_PIN_FUNCTION("lcd", x2000_lcd),
|
||||
INGENIC_PIN_FUNCTION("pwm0", x2000_pwm0),
|
||||
INGENIC_PIN_FUNCTION("pwm1", x2000_pwm1),
|
||||
INGENIC_PIN_FUNCTION("pwm2", x2000_pwm2),
|
||||
INGENIC_PIN_FUNCTION("pwm3", x2000_pwm3),
|
||||
INGENIC_PIN_FUNCTION("pwm4", x2000_pwm4),
|
||||
INGENIC_PIN_FUNCTION("pwm5", x2000_pwm5),
|
||||
INGENIC_PIN_FUNCTION("pwm6", x2000_pwm6),
|
||||
INGENIC_PIN_FUNCTION("pwm7", x2000_pwm7),
|
||||
INGENIC_PIN_FUNCTION("pwm8", x2000_pwm8),
|
||||
INGENIC_PIN_FUNCTION("pwm9", x2000_pwm9),
|
||||
INGENIC_PIN_FUNCTION("pwm10", x2000_pwm10),
|
||||
INGENIC_PIN_FUNCTION("pwm11", x2000_pwm11),
|
||||
INGENIC_PIN_FUNCTION("pwm12", x2000_pwm12),
|
||||
INGENIC_PIN_FUNCTION("pwm13", x2000_pwm13),
|
||||
INGENIC_PIN_FUNCTION("pwm14", x2000_pwm14),
|
||||
INGENIC_PIN_FUNCTION("pwm15", x2000_pwm15),
|
||||
INGENIC_PIN_FUNCTION("mac", x2100_mac),
|
||||
};
|
||||
|
||||
static const struct ingenic_chip_info x2100_chip_info = {
|
||||
@ -3762,7 +3767,7 @@ static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev,
|
||||
return -EINVAL;
|
||||
|
||||
dev_dbg(pctldev->dev, "enable function %s group %s\n",
|
||||
func->name, grp->grp.name);
|
||||
func->func.name, grp->grp.name);
|
||||
|
||||
mode = (uintptr_t)grp->data;
|
||||
if (mode <= 3) {
|
||||
@ -4310,14 +4315,14 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
for (i = 0; i < chip_info->num_functions; i++) {
|
||||
const struct function_desc *func = &chip_info->functions[i];
|
||||
const struct function_desc *function = &chip_info->functions[i];
|
||||
const struct pinfunction *func = &function->func;
|
||||
|
||||
err = pinmux_generic_add_function(jzpc->pctl, func->name,
|
||||
func->group_names, func->num_group_names,
|
||||
func->data);
|
||||
func->groups, func->ngroups,
|
||||
function->data);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "Failed to register function %s\n",
|
||||
func->name);
|
||||
dev_err(dev, "Failed to register function %s\n", func->name);
|
||||
return err;
|
||||
}
|
||||
}
|
||||
|
||||
@ -849,7 +849,6 @@ static int k210_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
unsigned int *num_maps)
|
||||
{
|
||||
unsigned int reserved_maps;
|
||||
struct device_node *np;
|
||||
int ret;
|
||||
|
||||
reserved_maps = 0;
|
||||
@ -861,13 +860,11 @@ static int k210_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
|
||||
for_each_available_child_of_node(np_config, np) {
|
||||
for_each_available_child_of_node_scoped(np_config, np) {
|
||||
ret = k210_pinctrl_dt_subnode_to_map(pctldev, np, map,
|
||||
&reserved_maps, num_maps);
|
||||
if (ret < 0) {
|
||||
of_node_put(np);
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
|
||||
|
||||
@ -1566,7 +1566,7 @@ static int keembay_add_functions(struct keembay_pinctrl *kpc,
|
||||
unsigned int grp_idx = 0;
|
||||
int j;
|
||||
|
||||
group_names = devm_kcalloc(kpc->dev, func->num_group_names,
|
||||
group_names = devm_kcalloc(kpc->dev, func->func.ngroups,
|
||||
sizeof(*group_names), GFP_KERNEL);
|
||||
if (!group_names)
|
||||
return -ENOMEM;
|
||||
@ -1576,20 +1576,20 @@ static int keembay_add_functions(struct keembay_pinctrl *kpc,
|
||||
struct keembay_mux_desc *mux;
|
||||
|
||||
for (mux = pdesc->drv_data; mux->name; mux++) {
|
||||
if (!strcmp(mux->name, func->name))
|
||||
if (!strcmp(mux->name, func->func.name))
|
||||
group_names[grp_idx++] = pdesc->name;
|
||||
}
|
||||
}
|
||||
|
||||
func->group_names = group_names;
|
||||
func->func.groups = group_names;
|
||||
}
|
||||
|
||||
/* Add all functions */
|
||||
for (i = 0; i < kpc->nfuncs; i++) {
|
||||
pinmux_generic_add_function(kpc->pctrl,
|
||||
functions[i].name,
|
||||
functions[i].group_names,
|
||||
functions[i].num_group_names,
|
||||
functions[i].func.name,
|
||||
functions[i].func.groups,
|
||||
functions[i].func.ngroups,
|
||||
functions[i].data);
|
||||
}
|
||||
|
||||
@ -1619,17 +1619,17 @@ static int keembay_build_functions(struct keembay_pinctrl *kpc)
|
||||
struct function_desc *fdesc;
|
||||
|
||||
/* Check if we already have function for this mux */
|
||||
for (fdesc = keembay_funcs; fdesc->name; fdesc++) {
|
||||
if (!strcmp(mux->name, fdesc->name)) {
|
||||
fdesc->num_group_names++;
|
||||
for (fdesc = keembay_funcs; fdesc->func.name; fdesc++) {
|
||||
if (!strcmp(mux->name, fdesc->func.name)) {
|
||||
fdesc->func.ngroups++;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Setup new function for this mux we didn't see before */
|
||||
if (!fdesc->name) {
|
||||
fdesc->name = mux->name;
|
||||
fdesc->num_group_names = 1;
|
||||
if (!fdesc->func.name) {
|
||||
fdesc->func.name = mux->name;
|
||||
fdesc->func.ngroups = 1;
|
||||
fdesc->data = &mux->mode;
|
||||
kpc->nfuncs++;
|
||||
}
|
||||
|
||||
@ -696,4 +696,5 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mcp23s08_probe_one);
|
||||
|
||||
MODULE_DESCRIPTION("MCP23S08 SPI/I2C GPIO driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
@ -111,4 +111,5 @@ static void mcp23s08_i2c_exit(void)
|
||||
}
|
||||
module_exit(mcp23s08_i2c_exit);
|
||||
|
||||
MODULE_DESCRIPTION("MCP23S08 I2C GPIO driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
@ -263,4 +263,5 @@ static void mcp23s08_spi_exit(void)
|
||||
}
|
||||
module_exit(mcp23s08_spi_exit);
|
||||
|
||||
MODULE_DESCRIPTION("MCP23S08 SPI GPIO driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
@ -259,16 +259,16 @@ static int mlxbf3_pinctrl_probe(struct platform_device *pdev)
|
||||
return PTR_ERR(priv->fw_ctrl_set0);
|
||||
|
||||
priv->fw_ctrl_clr0 = devm_platform_ioremap_resource(pdev, 1);
|
||||
if (IS_ERR(priv->fw_ctrl_set0))
|
||||
return PTR_ERR(priv->fw_ctrl_set0);
|
||||
if (IS_ERR(priv->fw_ctrl_clr0))
|
||||
return PTR_ERR(priv->fw_ctrl_clr0);
|
||||
|
||||
priv->fw_ctrl_set1 = devm_platform_ioremap_resource(pdev, 2);
|
||||
if (IS_ERR(priv->fw_ctrl_set0))
|
||||
return PTR_ERR(priv->fw_ctrl_set0);
|
||||
if (IS_ERR(priv->fw_ctrl_set1))
|
||||
return PTR_ERR(priv->fw_ctrl_set1);
|
||||
|
||||
priv->fw_ctrl_clr1 = devm_platform_ioremap_resource(pdev, 3);
|
||||
if (IS_ERR(priv->fw_ctrl_set0))
|
||||
return PTR_ERR(priv->fw_ctrl_set0);
|
||||
if (IS_ERR(priv->fw_ctrl_clr1))
|
||||
return PTR_ERR(priv->fw_ctrl_clr1);
|
||||
|
||||
ret = devm_pinctrl_register_and_init(dev,
|
||||
&mlxbf3_pin_desc,
|
||||
|
||||
@ -915,9 +915,8 @@ static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
|
||||
RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
|
||||
RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
|
||||
RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
|
||||
RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */
|
||||
RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */
|
||||
RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */
|
||||
RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x314, BIT(16 + 4)), /* i2c3_sdam0 */
|
||||
RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x314, BIT(16 + 4) | BIT(4)), /* i2c3_sdam1 */
|
||||
RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
|
||||
RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
|
||||
RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
|
||||
@ -926,18 +925,6 @@ static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
|
||||
RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
|
||||
RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
|
||||
RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
|
||||
RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */
|
||||
RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */
|
||||
RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */
|
||||
RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */
|
||||
RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */
|
||||
RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */
|
||||
RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */
|
||||
RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */
|
||||
RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */
|
||||
RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */
|
||||
RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */
|
||||
RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */
|
||||
};
|
||||
|
||||
static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
|
||||
@ -3107,7 +3094,6 @@ static int rockchip_pinctrl_parse_functions(struct device_node *np,
|
||||
u32 index)
|
||||
{
|
||||
struct device *dev = info->dev;
|
||||
struct device_node *child;
|
||||
struct rockchip_pmx_func *func;
|
||||
struct rockchip_pin_group *grp;
|
||||
int ret;
|
||||
@ -3128,14 +3114,12 @@ static int rockchip_pinctrl_parse_functions(struct device_node *np,
|
||||
if (!func->groups)
|
||||
return -ENOMEM;
|
||||
|
||||
for_each_child_of_node(np, child) {
|
||||
for_each_child_of_node_scoped(np, child) {
|
||||
func->groups[i] = child->name;
|
||||
grp = &info->groups[grp_index++];
|
||||
ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
|
||||
if (ret) {
|
||||
of_node_put(child);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
@ -3146,7 +3130,6 @@ static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct device_node *child;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
@ -3165,14 +3148,13 @@ static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
|
||||
|
||||
i = 0;
|
||||
|
||||
for_each_child_of_node(np, child) {
|
||||
for_each_child_of_node_scoped(np, child) {
|
||||
if (of_match_node(rockchip_bank_match, child))
|
||||
continue;
|
||||
|
||||
ret = rockchip_pinctrl_parse_functions(child, info, i++);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to parse function\n");
|
||||
of_node_put(child);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
@ -11,6 +11,7 @@
|
||||
#include <linux/errno.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/scmi_protocol.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/types.h>
|
||||
@ -504,6 +505,11 @@ static int pinctrl_scmi_get_pins(struct scmi_pinctrl *pmx,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char * const scmi_pinctrl_blocklist[] = {
|
||||
"fsl,imx95",
|
||||
NULL
|
||||
};
|
||||
|
||||
static int scmi_pinctrl_probe(struct scmi_device *sdev)
|
||||
{
|
||||
int ret;
|
||||
@ -515,6 +521,9 @@ static int scmi_pinctrl_probe(struct scmi_device *sdev)
|
||||
if (!sdev->handle)
|
||||
return -EINVAL;
|
||||
|
||||
if (of_machine_compatible_match(scmi_pinctrl_blocklist))
|
||||
return -ENODEV;
|
||||
|
||||
handle = sdev->handle;
|
||||
|
||||
pinctrl_ops = handle->devm_protocol_get(sdev, SCMI_PROTOCOL_PINCTRL, &ph);
|
||||
|
||||
@ -1329,7 +1329,6 @@ static void pcs_irq_free(struct pcs_device *pcs)
|
||||
static void pcs_free_resources(struct pcs_device *pcs)
|
||||
{
|
||||
pcs_irq_free(pcs);
|
||||
pinctrl_unregister(pcs->pctl);
|
||||
|
||||
#if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
|
||||
if (pcs->missing_nr_pinctrl_cells)
|
||||
@ -1879,7 +1878,7 @@ static int pcs_probe(struct platform_device *pdev)
|
||||
if (ret < 0)
|
||||
goto free;
|
||||
|
||||
ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
|
||||
ret = devm_pinctrl_register_and_init(pcs->dev, &pcs->desc, pcs, &pcs->pctl);
|
||||
if (ret) {
|
||||
dev_err(pcs->dev, "could not register single pinctrl driver\n");
|
||||
goto free;
|
||||
@ -1912,8 +1911,10 @@ static int pcs_probe(struct platform_device *pdev)
|
||||
|
||||
dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
|
||||
|
||||
return pinctrl_enable(pcs->pctl);
|
||||
if (pinctrl_enable(pcs->pctl))
|
||||
goto free;
|
||||
|
||||
return 0;
|
||||
free:
|
||||
pcs_free_resources(pcs);
|
||||
|
||||
|
||||
@ -1195,10 +1195,10 @@ static int st_pctl_dt_parse_groups(struct device_node *np,
|
||||
struct property *pp;
|
||||
struct device *dev = info->dev;
|
||||
struct st_pinconf *conf;
|
||||
struct device_node *pins;
|
||||
struct device_node *pins __free(device_node) = NULL;
|
||||
phandle bank;
|
||||
unsigned int offset;
|
||||
int i = 0, npins = 0, nr_props, ret = 0;
|
||||
int i = 0, npins = 0, nr_props;
|
||||
|
||||
pins = of_get_child_by_name(np, "st,pins");
|
||||
if (!pins)
|
||||
@ -1213,8 +1213,7 @@ static int st_pctl_dt_parse_groups(struct device_node *np,
|
||||
npins++;
|
||||
} else {
|
||||
pr_warn("Invalid st,pins in %pOFn node\n", np);
|
||||
ret = -EINVAL;
|
||||
goto out_put_node;
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
@ -1223,10 +1222,8 @@ static int st_pctl_dt_parse_groups(struct device_node *np,
|
||||
grp->pins = devm_kcalloc(dev, npins, sizeof(*grp->pins), GFP_KERNEL);
|
||||
grp->pin_conf = devm_kcalloc(dev, npins, sizeof(*grp->pin_conf), GFP_KERNEL);
|
||||
|
||||
if (!grp->pins || !grp->pin_conf) {
|
||||
ret = -ENOMEM;
|
||||
goto out_put_node;
|
||||
}
|
||||
if (!grp->pins || !grp->pin_conf)
|
||||
return -ENOMEM;
|
||||
|
||||
/* <bank offset mux direction rt_type rt_delay rt_clk> */
|
||||
for_each_property_of_node(pins, pp) {
|
||||
@ -1260,17 +1257,13 @@ static int st_pctl_dt_parse_groups(struct device_node *np,
|
||||
i++;
|
||||
}
|
||||
|
||||
out_put_node:
|
||||
of_node_put(pins);
|
||||
|
||||
return ret;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int st_pctl_parse_functions(struct device_node *np,
|
||||
struct st_pinctrl *info, u32 index, int *grp_index)
|
||||
{
|
||||
struct device *dev = info->dev;
|
||||
struct device_node *child;
|
||||
struct st_pmx_func *func;
|
||||
struct st_pctl_group *grp;
|
||||
int ret, i;
|
||||
@ -1285,15 +1278,13 @@ static int st_pctl_parse_functions(struct device_node *np,
|
||||
return -ENOMEM;
|
||||
|
||||
i = 0;
|
||||
for_each_child_of_node(np, child) {
|
||||
for_each_child_of_node_scoped(np, child) {
|
||||
func->groups[i] = child->name;
|
||||
grp = &info->groups[*grp_index];
|
||||
*grp_index += 1;
|
||||
ret = st_pctl_dt_parse_groups(child, grp, info, i++);
|
||||
if (ret) {
|
||||
of_node_put(child);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
dev_info(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups);
|
||||
|
||||
@ -1601,7 +1592,6 @@ static int st_pctl_probe_dt(struct platform_device *pdev,
|
||||
int i = 0, j = 0, k = 0, bank;
|
||||
struct pinctrl_pin_desc *pdesc;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct device_node *child;
|
||||
int grp_index = 0;
|
||||
int irq = 0;
|
||||
|
||||
@ -1646,25 +1636,21 @@ static int st_pctl_probe_dt(struct platform_device *pdev,
|
||||
pctl_desc->pins = pdesc;
|
||||
|
||||
bank = 0;
|
||||
for_each_child_of_node(np, child) {
|
||||
for_each_child_of_node_scoped(np, child) {
|
||||
if (of_property_read_bool(child, "gpio-controller")) {
|
||||
const char *bank_name = NULL;
|
||||
char **pin_names;
|
||||
|
||||
ret = st_gpiolib_register_bank(info, bank, child);
|
||||
if (ret) {
|
||||
of_node_put(child);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
k = info->banks[bank].range.pin_base;
|
||||
bank_name = info->banks[bank].range.name;
|
||||
|
||||
pin_names = devm_kasprintf_strarray(dev, bank_name, ST_GPIO_PINS_PER_BANK);
|
||||
if (IS_ERR(pin_names)) {
|
||||
of_node_put(child);
|
||||
if (IS_ERR(pin_names))
|
||||
return PTR_ERR(pin_names);
|
||||
}
|
||||
|
||||
for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) {
|
||||
pdesc->number = k;
|
||||
@ -1678,7 +1664,6 @@ static int st_pctl_probe_dt(struct platform_device *pdev,
|
||||
i++, &grp_index);
|
||||
if (ret) {
|
||||
dev_err(dev, "No functions found.\n");
|
||||
of_node_put(child);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
@ -830,4 +830,5 @@ static struct platform_driver tb10x_pinctrl_pdrv = {
|
||||
module_platform_driver(tb10x_pinctrl_pdrv);
|
||||
|
||||
MODULE_AUTHOR("Christian Ruppert <christian.ruppert@abilis.com>");
|
||||
MODULE_DESCRIPTION("Abilis Systems TB10x pinctrl driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
@ -237,13 +237,13 @@ struct muxval_remap {
|
||||
u8 remap;
|
||||
};
|
||||
|
||||
struct muxval_remap tps65224_muxval_remap[] = {
|
||||
static struct muxval_remap tps65224_muxval_remap[] = {
|
||||
{5, TPS6594_PINCTRL_DISABLE_WDOG_FUNCTION, TPS65224_PINCTRL_WKUP_FUNCTION_GPIO5},
|
||||
{5, TPS65224_PINCTRL_SYNCCLKIN_FUNCTION, TPS65224_PINCTRL_SYNCCLKIN_FUNCTION_GPIO5},
|
||||
{5, TPS65224_PINCTRL_NSLEEP2_FUNCTION, TPS65224_PINCTRL_NSLEEP2_FUNCTION_GPIO5},
|
||||
};
|
||||
|
||||
struct muxval_remap tps6594_muxval_remap[] = {
|
||||
static struct muxval_remap tps6594_muxval_remap[] = {
|
||||
{8, TPS6594_PINCTRL_DISABLE_WDOG_FUNCTION, TPS6594_PINCTRL_DISABLE_WDOG_FUNCTION_GPIO8},
|
||||
{8, TPS6594_PINCTRL_SYNCCLKOUT_FUNCTION, TPS6594_PINCTRL_SYNCCLKOUT_FUNCTION_GPIO8},
|
||||
{9, TPS6594_PINCTRL_CLK32KOUT_FUNCTION, TPS6594_PINCTRL_CLK32KOUT_FUNCTION_GPIO9},
|
||||
|
||||
@ -10,6 +10,7 @@
|
||||
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
|
||||
#include <linux/bitmap.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_address.h>
|
||||
@ -97,7 +98,7 @@ static int zynqmp_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return pctrl->ngroups;
|
||||
return pctrl->ngroups + zynqmp_desc.npins;
|
||||
}
|
||||
|
||||
static const char *zynqmp_pctrl_get_group_name(struct pinctrl_dev *pctldev,
|
||||
@ -105,7 +106,10 @@ static const char *zynqmp_pctrl_get_group_name(struct pinctrl_dev *pctldev,
|
||||
{
|
||||
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return pctrl->groups[selector].name;
|
||||
if (selector < pctrl->ngroups)
|
||||
return pctrl->groups[selector].name;
|
||||
|
||||
return zynqmp_desc.pins[selector - pctrl->ngroups].name;
|
||||
}
|
||||
|
||||
static int zynqmp_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
|
||||
@ -115,8 +119,13 @@ static int zynqmp_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
|
||||
{
|
||||
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
*pins = pctrl->groups[selector].pins;
|
||||
*npins = pctrl->groups[selector].npins;
|
||||
if (selector < pctrl->ngroups) {
|
||||
*pins = pctrl->groups[selector].pins;
|
||||
*npins = pctrl->groups[selector].npins;
|
||||
} else {
|
||||
*pins = &zynqmp_desc.pins[selector - pctrl->ngroups].number;
|
||||
*npins = 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -197,17 +206,16 @@ static int zynqmp_pinmux_set_mux(struct pinctrl_dev *pctldev,
|
||||
unsigned int function,
|
||||
unsigned int group)
|
||||
{
|
||||
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
|
||||
const struct zynqmp_pctrl_group *pgrp = &pctrl->groups[group];
|
||||
const unsigned int *pins;
|
||||
unsigned int npins;
|
||||
int ret, i;
|
||||
|
||||
for (i = 0; i < pgrp->npins; i++) {
|
||||
unsigned int pin = pgrp->pins[i];
|
||||
|
||||
ret = zynqmp_pm_pinctrl_set_function(pin, function);
|
||||
zynqmp_pctrl_get_group_pins(pctldev, group, &pins, &npins);
|
||||
for (i = 0; i < npins; i++) {
|
||||
ret = zynqmp_pm_pinctrl_set_function(pins[i], function);
|
||||
if (ret) {
|
||||
dev_err(pctldev->dev, "set mux failed for pin %u\n",
|
||||
pin);
|
||||
pins[i]);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
@ -467,12 +475,13 @@ static int zynqmp_pinconf_group_set(struct pinctrl_dev *pctldev,
|
||||
unsigned long *configs,
|
||||
unsigned int num_configs)
|
||||
{
|
||||
const unsigned int *pins;
|
||||
unsigned int npins;
|
||||
int i, ret;
|
||||
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
|
||||
const struct zynqmp_pctrl_group *pgrp = &pctrl->groups[selector];
|
||||
|
||||
for (i = 0; i < pgrp->npins; i++) {
|
||||
ret = zynqmp_pinconf_cfg_set(pctldev, pgrp->pins[i], configs,
|
||||
zynqmp_pctrl_get_group_pins(pctldev, selector, &pins, &npins);
|
||||
for (i = 0; i < npins; i++) {
|
||||
ret = zynqmp_pinconf_cfg_set(pctldev, pins[i], configs,
|
||||
num_configs);
|
||||
if (ret)
|
||||
return ret;
|
||||
@ -560,10 +569,12 @@ static int zynqmp_pinctrl_prepare_func_groups(struct device *dev, u32 fid,
|
||||
{
|
||||
u16 resp[NUM_GROUPS_PER_RESP] = {0};
|
||||
const char **fgroups;
|
||||
int ret, index, i;
|
||||
int ret, index, i, pin;
|
||||
unsigned int npins;
|
||||
unsigned long *used_pins __free(bitmap) =
|
||||
bitmap_zalloc(zynqmp_desc.npins, GFP_KERNEL);
|
||||
|
||||
fgroups = devm_kcalloc(dev, func->ngroups, sizeof(*fgroups), GFP_KERNEL);
|
||||
if (!fgroups)
|
||||
if (!used_pins)
|
||||
return -ENOMEM;
|
||||
|
||||
for (index = 0; index < func->ngroups; index += NUM_GROUPS_PER_RESP) {
|
||||
@ -578,23 +589,37 @@ static int zynqmp_pinctrl_prepare_func_groups(struct device *dev, u32 fid,
|
||||
if (resp[i] == RESERVED_GROUP)
|
||||
continue;
|
||||
|
||||
fgroups[index + i] = devm_kasprintf(dev, GFP_KERNEL,
|
||||
"%s_%d_grp",
|
||||
func->name,
|
||||
index + i);
|
||||
if (!fgroups[index + i])
|
||||
return -ENOMEM;
|
||||
|
||||
groups[resp[i]].name = devm_kasprintf(dev, GFP_KERNEL,
|
||||
"%s_%d_grp",
|
||||
func->name,
|
||||
index + i);
|
||||
if (!groups[resp[i]].name)
|
||||
return -ENOMEM;
|
||||
|
||||
for (pin = 0; pin < groups[resp[i]].npins; pin++)
|
||||
__set_bit(groups[resp[i]].pins[pin], used_pins);
|
||||
}
|
||||
}
|
||||
done:
|
||||
npins = bitmap_weight(used_pins, zynqmp_desc.npins);
|
||||
fgroups = devm_kcalloc(dev, size_add(func->ngroups, npins),
|
||||
sizeof(*fgroups), GFP_KERNEL);
|
||||
if (!fgroups)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < func->ngroups; i++) {
|
||||
fgroups[i] = devm_kasprintf(dev, GFP_KERNEL, "%s_%d_grp",
|
||||
func->name, i);
|
||||
if (!fgroups[i])
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
pin = 0;
|
||||
for_each_set_bit(pin, used_pins, zynqmp_desc.npins)
|
||||
fgroups[i++] = zynqmp_desc.pins[pin].name;
|
||||
|
||||
func->groups = fgroups;
|
||||
func->ngroups += npins;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -718,7 +743,7 @@ static int zynqmp_pinctrl_prepare_group_pins(struct device *dev,
|
||||
int ret;
|
||||
|
||||
for (pin = 0; pin < zynqmp_desc.npins; pin++) {
|
||||
ret = zynqmp_pinctrl_create_pin_groups(dev, groups, pin);
|
||||
ret = zynqmp_pinctrl_create_pin_groups(dev, groups, zynqmp_desc.pins[pin].number);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
@ -772,6 +797,10 @@ static int zynqmp_pinctrl_prepare_function_info(struct device *dev,
|
||||
if (!groups)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = zynqmp_pinctrl_prepare_group_pins(dev, groups, pctrl->ngroups);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < pctrl->nfuncs; i++) {
|
||||
ret = zynqmp_pinctrl_prepare_func_groups(dev, i, &funcs[i],
|
||||
groups);
|
||||
@ -779,10 +808,6 @@ static int zynqmp_pinctrl_prepare_function_info(struct device *dev,
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = zynqmp_pinctrl_prepare_group_pins(dev, groups, pctrl->ngroups);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pctrl->funcs = funcs;
|
||||
pctrl->groups = groups;
|
||||
|
||||
|
||||
@ -796,7 +796,7 @@ pinmux_generic_get_function_name(struct pinctrl_dev *pctldev,
|
||||
if (!function)
|
||||
return NULL;
|
||||
|
||||
return function->name;
|
||||
return function->func.name;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pinmux_generic_get_function_name);
|
||||
|
||||
@ -805,12 +805,12 @@ EXPORT_SYMBOL_GPL(pinmux_generic_get_function_name);
|
||||
* @pctldev: pin controller device
|
||||
* @selector: function number
|
||||
* @groups: array of pin groups
|
||||
* @num_groups: number of pin groups
|
||||
* @ngroups: number of pin groups
|
||||
*/
|
||||
int pinmux_generic_get_function_groups(struct pinctrl_dev *pctldev,
|
||||
unsigned int selector,
|
||||
const char * const **groups,
|
||||
unsigned int * const num_groups)
|
||||
unsigned int * const ngroups)
|
||||
{
|
||||
struct function_desc *function;
|
||||
|
||||
@ -821,8 +821,8 @@ int pinmux_generic_get_function_groups(struct pinctrl_dev *pctldev,
|
||||
__func__, selector);
|
||||
return -EINVAL;
|
||||
}
|
||||
*groups = function->group_names;
|
||||
*num_groups = function->num_group_names;
|
||||
*groups = function->func.groups;
|
||||
*ngroups = function->func.ngroups;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -852,13 +852,13 @@ EXPORT_SYMBOL_GPL(pinmux_generic_get_function);
|
||||
* @pctldev: pin controller device
|
||||
* @name: name of the function
|
||||
* @groups: array of pin groups
|
||||
* @num_groups: number of pin groups
|
||||
* @ngroups: number of pin groups
|
||||
* @data: pin controller driver specific data
|
||||
*/
|
||||
int pinmux_generic_add_function(struct pinctrl_dev *pctldev,
|
||||
const char *name,
|
||||
const char * const *groups,
|
||||
const unsigned int num_groups,
|
||||
const unsigned int ngroups,
|
||||
void *data)
|
||||
{
|
||||
struct function_desc *function;
|
||||
@ -877,10 +877,7 @@ int pinmux_generic_add_function(struct pinctrl_dev *pctldev,
|
||||
if (!function)
|
||||
return -ENOMEM;
|
||||
|
||||
function->name = name;
|
||||
function->group_names = groups;
|
||||
function->num_group_names = num_groups;
|
||||
function->data = data;
|
||||
*function = PINCTRL_FUNCTION_DESC(name, groups, ngroups, data);
|
||||
|
||||
error = radix_tree_insert(&pctldev->pin_function_tree, selector, function);
|
||||
if (error)
|
||||
|
||||
@ -133,18 +133,21 @@ static inline void pinmux_init_device_debugfs(struct dentry *devroot,
|
||||
|
||||
/**
|
||||
* struct function_desc - generic function descriptor
|
||||
* @name: name of the function
|
||||
* @group_names: array of pin group names
|
||||
* @num_group_names: number of pin group names
|
||||
* @func: generic data of the pin function (name and groups of pins)
|
||||
* @data: pin controller driver specific data
|
||||
*/
|
||||
struct function_desc {
|
||||
const char *name;
|
||||
const char * const *group_names;
|
||||
int num_group_names;
|
||||
struct pinfunction func;
|
||||
void *data;
|
||||
};
|
||||
|
||||
/* Convenient macro to define a generic pin function descriptor */
|
||||
#define PINCTRL_FUNCTION_DESC(_name, _grps, _num_grps, _data) \
|
||||
(struct function_desc) { \
|
||||
.func = PINCTRL_PINFUNCTION(_name, _grps, _num_grps), \
|
||||
.data = _data, \
|
||||
}
|
||||
|
||||
int pinmux_generic_get_function_count(struct pinctrl_dev *pctldev);
|
||||
|
||||
const char *
|
||||
@ -154,7 +157,7 @@ pinmux_generic_get_function_name(struct pinctrl_dev *pctldev,
|
||||
int pinmux_generic_get_function_groups(struct pinctrl_dev *pctldev,
|
||||
unsigned int selector,
|
||||
const char * const **groups,
|
||||
unsigned int * const num_groups);
|
||||
unsigned int * const ngroups);
|
||||
|
||||
struct function_desc *pinmux_generic_get_function(struct pinctrl_dev *pctldev,
|
||||
unsigned int selector);
|
||||
@ -162,7 +165,7 @@ struct function_desc *pinmux_generic_get_function(struct pinctrl_dev *pctldev,
|
||||
int pinmux_generic_add_function(struct pinctrl_dev *pctldev,
|
||||
const char *name,
|
||||
const char * const *groups,
|
||||
unsigned int const num_groups,
|
||||
unsigned int const ngroups,
|
||||
void *data);
|
||||
|
||||
int pinmux_generic_remove_function(struct pinctrl_dev *pctldev,
|
||||
|
||||
@ -68,6 +68,15 @@ config PINCTRL_SC7280_LPASS_LPI
|
||||
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
|
||||
(Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform.
|
||||
|
||||
config PINCTRL_SM4250_LPASS_LPI
|
||||
tristate "Qualcomm Technologies Inc SM4250 LPASS LPI pin controller driver"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
depends on PINCTRL_LPASS_LPI
|
||||
help
|
||||
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
|
||||
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
|
||||
(Low Power Island) found on the Qualcomm Technologies Inc SM4250 platform.
|
||||
|
||||
config PINCTRL_SM6115_LPASS_LPI
|
||||
tristate "Qualcomm Technologies Inc SM6115 LPASS LPI pin controller driver"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
|
||||
@ -43,6 +43,7 @@ obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
|
||||
obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
|
||||
obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o
|
||||
obj-$(CONFIG_PINCTRL_SDX75) += pinctrl-sdx75.o
|
||||
obj-$(CONFIG_PINCTRL_SM4250_LPASS_LPI) += pinctrl-sm4250-lpass-lpi.o
|
||||
obj-$(CONFIG_PINCTRL_SM4450) += pinctrl-sm4450.o
|
||||
obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o
|
||||
obj-$(CONFIG_PINCTRL_SM6115_LPASS_LPI) += pinctrl-sm6115-lpass-lpi.o
|
||||
|
||||
@ -20,7 +20,7 @@
|
||||
|
||||
#include "pinctrl-lpass-lpi.h"
|
||||
|
||||
#define MAX_NR_GPIO 23
|
||||
#define MAX_NR_GPIO 32
|
||||
#define GPIO_FUNC 0
|
||||
#define MAX_LPI_NUM_CLKS 2
|
||||
|
||||
|
||||
@ -1290,6 +1290,22 @@ static const int sdm670_reserved_gpios[] = {
|
||||
58, 59, 60, 61, 62, 63, 64, 69, 70, 71, 72, 73, 74, 104, -1
|
||||
};
|
||||
|
||||
static const struct msm_gpio_wakeirq_map sdm670_pdc_map[] = {
|
||||
{ 1, 30 }, { 3, 31 }, { 5, 32 }, { 10, 33 }, { 11, 34 },
|
||||
{ 20, 35 }, { 22, 36 }, { 24, 37 }, { 26, 38 }, { 30, 39 },
|
||||
{ 31, 117 }, { 32, 41 }, { 34, 42 }, { 36, 43 }, { 37, 44 },
|
||||
{ 38, 45 }, { 39, 46 }, { 40, 47 }, { 41, 115 }, { 43, 49 },
|
||||
{ 44, 50 }, { 46, 51 }, { 48, 52 }, { 49, 118 }, { 52, 54 },
|
||||
{ 53, 55 }, { 54, 56 }, { 56, 57 }, { 57, 58 }, { 66, 66 },
|
||||
{ 68, 67 }, { 77, 70 }, { 78, 71 }, { 79, 72 }, { 80, 73 },
|
||||
{ 84, 74 }, { 85, 75 }, { 86, 76 }, { 88, 77 }, { 89, 116 },
|
||||
{ 91, 79 }, { 92, 80 }, { 95, 81 }, { 96, 82 }, { 97, 83 },
|
||||
{ 101, 84 }, { 103, 85 }, { 115, 90 }, { 116, 91 }, { 117, 92 },
|
||||
{ 118, 93 }, { 119, 94 }, { 120, 95 }, { 121, 96 }, { 122, 97 },
|
||||
{ 123, 98 }, { 124, 99 }, { 125, 100 }, { 127, 102 }, { 128, 103 },
|
||||
{ 129, 104 }, { 130, 105 }, { 132, 106 }, { 133, 107 }, { 145, 108 },
|
||||
};
|
||||
|
||||
static const struct msm_pinctrl_soc_data sdm670_pinctrl = {
|
||||
.pins = sdm670_pins,
|
||||
.npins = ARRAY_SIZE(sdm670_pins),
|
||||
@ -1299,6 +1315,9 @@ static const struct msm_pinctrl_soc_data sdm670_pinctrl = {
|
||||
.ngroups = ARRAY_SIZE(sdm670_groups),
|
||||
.ngpios = 151,
|
||||
.reserved_gpios = sdm670_reserved_gpios,
|
||||
.wakeirq_map = sdm670_pdc_map,
|
||||
.nwakeirq_map = ARRAY_SIZE(sdm670_pdc_map),
|
||||
.wakeirq_dual_edge_errata = true,
|
||||
};
|
||||
|
||||
static int sdm670_pinctrl_probe(struct platform_device *pdev)
|
||||
|
||||
236
drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c
Normal file
236
drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c
Normal file
@ -0,0 +1,236 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2020, 2023 Linaro Ltd.
|
||||
*/
|
||||
|
||||
#include <linux/gpio/driver.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "pinctrl-lpass-lpi.h"
|
||||
|
||||
enum lpass_lpi_functions {
|
||||
LPI_MUX_dmic01_clk,
|
||||
LPI_MUX_dmic01_data,
|
||||
LPI_MUX_dmic23_clk,
|
||||
LPI_MUX_dmic23_data,
|
||||
LPI_MUX_dmic4_clk,
|
||||
LPI_MUX_dmic4_data,
|
||||
LPI_MUX_ext_mclk0_a,
|
||||
LPI_MUX_ext_mclk0_b,
|
||||
LPI_MUX_ext_mclk1_a,
|
||||
LPI_MUX_ext_mclk1_b,
|
||||
LPI_MUX_ext_mclk1_c,
|
||||
LPI_MUX_i2s1_clk,
|
||||
LPI_MUX_i2s1_data,
|
||||
LPI_MUX_i2s1_ws,
|
||||
LPI_MUX_i2s2_clk,
|
||||
LPI_MUX_i2s2_data,
|
||||
LPI_MUX_i2s2_ws,
|
||||
LPI_MUX_i2s3_clk,
|
||||
LPI_MUX_i2s3_data,
|
||||
LPI_MUX_i2s3_ws,
|
||||
LPI_MUX_qup_io_00,
|
||||
LPI_MUX_qup_io_01,
|
||||
LPI_MUX_qup_io_05,
|
||||
LPI_MUX_qup_io_10,
|
||||
LPI_MUX_qup_io_11,
|
||||
LPI_MUX_qup_io_25,
|
||||
LPI_MUX_qup_io_21,
|
||||
LPI_MUX_qup_io_26,
|
||||
LPI_MUX_qup_io_31,
|
||||
LPI_MUX_qup_io_36,
|
||||
LPI_MUX_qua_mi2s_data,
|
||||
LPI_MUX_qua_mi2s_sclk,
|
||||
LPI_MUX_qua_mi2s_ws,
|
||||
LPI_MUX_slim_clk,
|
||||
LPI_MUX_slim_data,
|
||||
LPI_MUX_sync_out,
|
||||
LPI_MUX_swr_rx_clk,
|
||||
LPI_MUX_swr_rx_data,
|
||||
LPI_MUX_swr_tx_clk,
|
||||
LPI_MUX_swr_tx_data,
|
||||
LPI_MUX_swr_wsa_clk,
|
||||
LPI_MUX_swr_wsa_data,
|
||||
LPI_MUX_gpio,
|
||||
LPI_MUX__,
|
||||
};
|
||||
|
||||
static const struct pinctrl_pin_desc sm4250_lpi_pins[] = {
|
||||
PINCTRL_PIN(0, "gpio0"),
|
||||
PINCTRL_PIN(1, "gpio1"),
|
||||
PINCTRL_PIN(2, "gpio2"),
|
||||
PINCTRL_PIN(3, "gpio3"),
|
||||
PINCTRL_PIN(4, "gpio4"),
|
||||
PINCTRL_PIN(5, "gpio5"),
|
||||
PINCTRL_PIN(6, "gpio6"),
|
||||
PINCTRL_PIN(7, "gpio7"),
|
||||
PINCTRL_PIN(8, "gpio8"),
|
||||
PINCTRL_PIN(9, "gpio9"),
|
||||
PINCTRL_PIN(10, "gpio10"),
|
||||
PINCTRL_PIN(11, "gpio11"),
|
||||
PINCTRL_PIN(12, "gpio12"),
|
||||
PINCTRL_PIN(13, "gpio13"),
|
||||
PINCTRL_PIN(14, "gpio14"),
|
||||
PINCTRL_PIN(15, "gpio15"),
|
||||
PINCTRL_PIN(16, "gpio16"),
|
||||
PINCTRL_PIN(17, "gpio17"),
|
||||
PINCTRL_PIN(18, "gpio18"),
|
||||
PINCTRL_PIN(19, "gpio19"),
|
||||
PINCTRL_PIN(20, "gpio20"),
|
||||
PINCTRL_PIN(21, "gpio21"),
|
||||
PINCTRL_PIN(22, "gpio22"),
|
||||
PINCTRL_PIN(23, "gpio23"),
|
||||
PINCTRL_PIN(24, "gpio24"),
|
||||
PINCTRL_PIN(25, "gpio25"),
|
||||
PINCTRL_PIN(26, "gpio26"),
|
||||
};
|
||||
|
||||
static const char * const dmic01_clk_groups[] = { "gpio6" };
|
||||
static const char * const dmic01_data_groups[] = { "gpio7" };
|
||||
static const char * const dmic23_clk_groups[] = { "gpio8" };
|
||||
static const char * const dmic23_data_groups[] = { "gpio9" };
|
||||
static const char * const dmic4_clk_groups[] = { "gpio10" };
|
||||
static const char * const dmic4_data_groups[] = { "gpio11" };
|
||||
static const char * const ext_mclk0_a_groups[] = { "gpio13" };
|
||||
static const char * const ext_mclk0_b_groups[] = { "gpio5" };
|
||||
static const char * const ext_mclk1_a_groups[] = { "gpio18" };
|
||||
static const char * const ext_mclk1_b_groups[] = { "gpio9" };
|
||||
static const char * const ext_mclk1_c_groups[] = { "gpio17" };
|
||||
static const char * const slim_clk_groups[] = { "gpio14" };
|
||||
static const char * const slim_data_groups[] = { "gpio15" };
|
||||
static const char * const i2s1_clk_groups[] = { "gpio6" };
|
||||
static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
|
||||
static const char * const i2s1_ws_groups[] = { "gpio7" };
|
||||
static const char * const i2s2_clk_groups[] = { "gpio10" };
|
||||
static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" };
|
||||
static const char * const i2s2_ws_groups[] = { "gpio11" };
|
||||
static const char * const i2s3_clk_groups[] = { "gpio14" };
|
||||
static const char * const i2s3_data_groups[] = { "gpio16", "gpio17" };
|
||||
static const char * const i2s3_ws_groups[] = { "gpio15" };
|
||||
static const char * const qup_io_00_groups[] = { "gpio19" };
|
||||
static const char * const qup_io_01_groups[] = { "gpio21" };
|
||||
static const char * const qup_io_05_groups[] = { "gpio23" };
|
||||
static const char * const qup_io_10_groups[] = { "gpio20" };
|
||||
static const char * const qup_io_11_groups[] = { "gpio22" };
|
||||
static const char * const qup_io_25_groups[] = { "gpio23" };
|
||||
static const char * const qup_io_21_groups[] = { "gpio25" };
|
||||
static const char * const qup_io_26_groups[] = { "gpio25" };
|
||||
static const char * const qup_io_31_groups[] = { "gpio26" };
|
||||
static const char * const qup_io_36_groups[] = { "gpio26" };
|
||||
static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" };
|
||||
static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
|
||||
static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
|
||||
static const char * const sync_out_groups[] = { "gpio19", "gpio20", "gpio21", "gpio22",
|
||||
"gpio23", "gpio24", "gpio25", "gpio26"};
|
||||
static const char * const swr_rx_clk_groups[] = { "gpio3" };
|
||||
static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
|
||||
static const char * const swr_tx_clk_groups[] = { "gpio0" };
|
||||
static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2" };
|
||||
static const char * const swr_wsa_clk_groups[] = { "gpio10" };
|
||||
static const char * const swr_wsa_data_groups[] = { "gpio11" };
|
||||
|
||||
|
||||
static const struct lpi_pingroup sm4250_groups[] = {
|
||||
LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
|
||||
LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
|
||||
LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
|
||||
LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
|
||||
LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
|
||||
LPI_PINGROUP(5, 12, swr_rx_data, ext_mclk0_b, qua_mi2s_data, _),
|
||||
LPI_PINGROUP(6, LPI_NO_SLEW, dmic01_clk, i2s1_clk, _, _),
|
||||
LPI_PINGROUP(7, LPI_NO_SLEW, dmic01_data, i2s1_ws, _, _),
|
||||
LPI_PINGROUP(8, LPI_NO_SLEW, dmic23_clk, i2s1_data, _, _),
|
||||
LPI_PINGROUP(9, LPI_NO_SLEW, dmic23_data, i2s1_data, ext_mclk1_b, _),
|
||||
LPI_PINGROUP(10, 16, i2s2_clk, swr_wsa_clk, dmic4_clk, _),
|
||||
LPI_PINGROUP(11, 18, i2s2_ws, swr_wsa_data, dmic4_data, _),
|
||||
LPI_PINGROUP(12, LPI_NO_SLEW, dmic23_clk, i2s2_data, _, _),
|
||||
LPI_PINGROUP(13, LPI_NO_SLEW, dmic23_data, i2s2_data, ext_mclk0_a, _),
|
||||
LPI_PINGROUP(14, LPI_NO_SLEW, i2s3_clk, slim_clk, _, _),
|
||||
LPI_PINGROUP(15, LPI_NO_SLEW, i2s3_ws, slim_data, _, _),
|
||||
LPI_PINGROUP(16, LPI_NO_SLEW, i2s3_data, _, _, _),
|
||||
LPI_PINGROUP(17, LPI_NO_SLEW, i2s3_data, ext_mclk1_c, _, _),
|
||||
LPI_PINGROUP(18, 20, ext_mclk1_a, swr_rx_data, _, _),
|
||||
LPI_PINGROUP(19, LPI_NO_SLEW, qup_io_00, sync_out, _, _),
|
||||
LPI_PINGROUP(20, LPI_NO_SLEW, qup_io_10, sync_out, _, _),
|
||||
LPI_PINGROUP(21, LPI_NO_SLEW, qup_io_01, sync_out, _, _),
|
||||
LPI_PINGROUP(22, LPI_NO_SLEW, qup_io_11, sync_out, _, _),
|
||||
LPI_PINGROUP(23, LPI_NO_SLEW, qup_io_25, qup_io_05, sync_out, _),
|
||||
LPI_PINGROUP(25, LPI_NO_SLEW, qup_io_26, qup_io_21, sync_out, _),
|
||||
LPI_PINGROUP(26, LPI_NO_SLEW, qup_io_36, qup_io_31, sync_out, _),
|
||||
};
|
||||
|
||||
static const struct lpi_function sm4250_functions[] = {
|
||||
LPI_FUNCTION(dmic01_clk),
|
||||
LPI_FUNCTION(dmic01_data),
|
||||
LPI_FUNCTION(dmic23_clk),
|
||||
LPI_FUNCTION(dmic23_data),
|
||||
LPI_FUNCTION(dmic4_clk),
|
||||
LPI_FUNCTION(dmic4_data),
|
||||
LPI_FUNCTION(ext_mclk0_a),
|
||||
LPI_FUNCTION(ext_mclk0_b),
|
||||
LPI_FUNCTION(ext_mclk1_a),
|
||||
LPI_FUNCTION(ext_mclk1_b),
|
||||
LPI_FUNCTION(ext_mclk1_c),
|
||||
LPI_FUNCTION(i2s1_clk),
|
||||
LPI_FUNCTION(i2s1_data),
|
||||
LPI_FUNCTION(i2s1_ws),
|
||||
LPI_FUNCTION(i2s2_clk),
|
||||
LPI_FUNCTION(i2s2_data),
|
||||
LPI_FUNCTION(i2s2_ws),
|
||||
LPI_FUNCTION(i2s3_clk),
|
||||
LPI_FUNCTION(i2s3_data),
|
||||
LPI_FUNCTION(i2s3_ws),
|
||||
LPI_FUNCTION(qup_io_00),
|
||||
LPI_FUNCTION(qup_io_01),
|
||||
LPI_FUNCTION(qup_io_05),
|
||||
LPI_FUNCTION(qup_io_10),
|
||||
LPI_FUNCTION(qup_io_11),
|
||||
LPI_FUNCTION(qup_io_25),
|
||||
LPI_FUNCTION(qup_io_21),
|
||||
LPI_FUNCTION(qup_io_26),
|
||||
LPI_FUNCTION(qup_io_31),
|
||||
LPI_FUNCTION(qup_io_36),
|
||||
LPI_FUNCTION(qua_mi2s_data),
|
||||
LPI_FUNCTION(qua_mi2s_sclk),
|
||||
LPI_FUNCTION(qua_mi2s_ws),
|
||||
LPI_FUNCTION(slim_clk),
|
||||
LPI_FUNCTION(slim_data),
|
||||
LPI_FUNCTION(sync_out),
|
||||
LPI_FUNCTION(swr_rx_clk),
|
||||
LPI_FUNCTION(swr_rx_data),
|
||||
LPI_FUNCTION(swr_tx_clk),
|
||||
LPI_FUNCTION(swr_tx_data),
|
||||
LPI_FUNCTION(swr_wsa_clk),
|
||||
LPI_FUNCTION(swr_wsa_data),
|
||||
};
|
||||
|
||||
static const struct lpi_pinctrl_variant_data sm4250_lpi_data = {
|
||||
.pins = sm4250_lpi_pins,
|
||||
.npins = ARRAY_SIZE(sm4250_lpi_pins),
|
||||
.groups = sm4250_groups,
|
||||
.ngroups = ARRAY_SIZE(sm4250_groups),
|
||||
.functions = sm4250_functions,
|
||||
.nfunctions = ARRAY_SIZE(sm4250_functions),
|
||||
};
|
||||
|
||||
static const struct of_device_id lpi_pinctrl_of_match[] = {
|
||||
{ .compatible = "qcom,sm4250-lpass-lpi-pinctrl", .data = &sm4250_lpi_data },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
|
||||
|
||||
static struct platform_driver lpi_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "qcom-sm4250-lpass-lpi-pinctrl",
|
||||
.of_match_table = lpi_pinctrl_of_match,
|
||||
},
|
||||
.probe = lpi_pinctrl_probe,
|
||||
.remove_new = lpi_pinctrl_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(lpi_pinctrl_driver);
|
||||
MODULE_DESCRIPTION("QTI SM4250 LPI GPIO pin control driver");
|
||||
MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
|
||||
MODULE_LICENSE("GPL");
|
||||
@ -1234,6 +1234,7 @@ static const struct of_device_id pmic_gpio_of_match[] = {
|
||||
{ .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
|
||||
{ .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
|
||||
{ .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
|
||||
{ .compatible = "qcom,pmc8380-gpio", .data = (void *) 10 },
|
||||
{ .compatible = "qcom,pmd8028-gpio", .data = (void *) 4 },
|
||||
{ .compatible = "qcom,pmi632-gpio", .data = (void *) 8 },
|
||||
{ .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 },
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1236,6 +1236,30 @@ static const unsigned int avb0_mdio_pins[] = {
|
||||
static const unsigned int avb0_mdio_mux[] = {
|
||||
AVB0_MDC_MARK, AVB0_MDIO_MARK,
|
||||
};
|
||||
static const unsigned int avb0_mii_pins[] = {
|
||||
/*
|
||||
* AVB0_MII_TD0, AVB0_MII_TD1, AVB0_MII_TD2,
|
||||
* AVB0_MII_TD3, AVB0_MII_RD0, AVB0_MII_RD1,
|
||||
* AVB0_MII_RD2, AVB0_MII_RD3, AVB0_MII_TXC,
|
||||
* AVB0_MII_TX_EN, AVB0_MII_TX_ER, AVB0_MII_RXC,
|
||||
* AVB0_MII_RX_DV, AVB0_MII_RX_ER, AVB0_MII_CRS,
|
||||
* AVB0_MII_COL
|
||||
*/
|
||||
RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 6),
|
||||
RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
|
||||
RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 15),
|
||||
RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 19),
|
||||
RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 1),
|
||||
RCAR_GP_PIN(7, 0),
|
||||
};
|
||||
static const unsigned int avb0_mii_mux[] = {
|
||||
AVB0_MII_TD0_MARK, AVB0_MII_TD1_MARK, AVB0_MII_TD2_MARK,
|
||||
AVB0_MII_TD3_MARK, AVB0_MII_RD0_MARK, AVB0_MII_RD1_MARK,
|
||||
AVB0_MII_RD2_MARK, AVB0_MII_RD3_MARK, AVB0_MII_TXC_MARK,
|
||||
AVB0_MII_TX_EN_MARK, AVB0_MII_TX_ER_MARK, AVB0_MII_RXC_MARK,
|
||||
AVB0_MII_RX_DV_MARK, AVB0_MII_RX_ER_MARK, AVB0_MII_CRS_MARK,
|
||||
AVB0_MII_COL_MARK,
|
||||
};
|
||||
static const unsigned int avb0_rgmii_pins[] = {
|
||||
/*
|
||||
* AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
|
||||
@ -1314,6 +1338,30 @@ static const unsigned int avb1_mdio_pins[] = {
|
||||
static const unsigned int avb1_mdio_mux[] = {
|
||||
AVB1_MDC_MARK, AVB1_MDIO_MARK,
|
||||
};
|
||||
static const unsigned int avb1_mii_pins[] = {
|
||||
/*
|
||||
* AVB1_MII_TD0, AVB1_MII_TD1, AVB1_MII_TD2,
|
||||
* AVB1_MII_TD3, AVB1_MII_RD0, AVB1_MII_RD1,
|
||||
* AVB1_MII_RD2, AVB1_MII_RD3, AVB1_MII_TXC,
|
||||
* AVB1_MII_TX_EN, AVB1_MII_TX_ER, AVB1_MII_RXC,
|
||||
* AVB1_MII_RX_DV, AVB1_MII_RX_ER, AVB1_MII_CRS,
|
||||
* AVB1_MII_COL
|
||||
*/
|
||||
RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 16),
|
||||
RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
|
||||
RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19), RCAR_GP_PIN(6, 6),
|
||||
RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 8),
|
||||
RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 11),
|
||||
RCAR_GP_PIN(6, 10),
|
||||
};
|
||||
static const unsigned int avb1_mii_mux[] = {
|
||||
AVB1_MII_TD0_MARK, AVB1_MII_TD1_MARK, AVB1_MII_TD2_MARK,
|
||||
AVB1_MII_TD3_MARK, AVB1_MII_RD0_MARK, AVB1_MII_RD1_MARK,
|
||||
AVB1_MII_RD2_MARK, AVB1_MII_RD3_MARK, AVB1_MII_TXC_MARK,
|
||||
AVB1_MII_TX_EN_MARK, AVB1_MII_TX_ER_MARK, AVB1_MII_RXC_MARK,
|
||||
AVB1_MII_RX_DV_MARK, AVB1_MII_RX_ER_MARK, AVB1_MII_CRS_MARK,
|
||||
AVB1_MII_COL_MARK,
|
||||
};
|
||||
static const unsigned int avb1_rgmii_pins[] = {
|
||||
/*
|
||||
* AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,
|
||||
@ -1509,7 +1557,7 @@ static const unsigned int hscif0_ctrl_mux[] = {
|
||||
HRTS0_N_MARK, HCTS0_N_MARK,
|
||||
};
|
||||
|
||||
/* - HSCIF1_A ----------------------------------------------------------------- */
|
||||
/* - HSCIF1 ------------------------------------------------------------------- */
|
||||
static const unsigned int hscif1_data_a_pins[] = {
|
||||
/* HRX1_A, HTX1_A */
|
||||
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
|
||||
@ -1532,7 +1580,6 @@ static const unsigned int hscif1_ctrl_a_mux[] = {
|
||||
HRTS1_N_A_MARK, HCTS1_N_A_MARK,
|
||||
};
|
||||
|
||||
/* - HSCIF1_B ---------------------------------------------------------------- */
|
||||
static const unsigned int hscif1_data_b_pins[] = {
|
||||
/* HRX1_B, HTX1_B */
|
||||
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
|
||||
@ -1578,7 +1625,7 @@ static const unsigned int hscif2_ctrl_mux[] = {
|
||||
HRTS2_N_MARK, HCTS2_N_MARK,
|
||||
};
|
||||
|
||||
/* - HSCIF3_A ----------------------------------------------------------------- */
|
||||
/* - HSCIF3 ------------------------------------------------------------------- */
|
||||
static const unsigned int hscif3_data_a_pins[] = {
|
||||
/* HRX3_A, HTX3_A */
|
||||
RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
|
||||
@ -1601,7 +1648,6 @@ static const unsigned int hscif3_ctrl_a_mux[] = {
|
||||
HRTS3_N_A_MARK, HCTS3_N_A_MARK,
|
||||
};
|
||||
|
||||
/* - HSCIF3_B ----------------------------------------------------------------- */
|
||||
static const unsigned int hscif3_data_b_pins[] = {
|
||||
/* HRX3_B, HTX3_B */
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
|
||||
@ -2061,7 +2107,7 @@ static const unsigned int pcie0_clkreq_n_mux[] = {
|
||||
PCIE0_CLKREQ_N_MARK,
|
||||
};
|
||||
|
||||
/* - PWM0_A ------------------------------------------------------------------- */
|
||||
/* - PWM0 --------------------------------------------------------------------- */
|
||||
static const unsigned int pwm0_a_pins[] = {
|
||||
/* PWM0_A */
|
||||
RCAR_GP_PIN(1, 15),
|
||||
@ -2070,7 +2116,6 @@ static const unsigned int pwm0_a_mux[] = {
|
||||
PWM0_A_MARK,
|
||||
};
|
||||
|
||||
/* - PWM0_B ------------------------------------------------------------------- */
|
||||
static const unsigned int pwm0_b_pins[] = {
|
||||
/* PWM0_B */
|
||||
RCAR_GP_PIN(1, 14),
|
||||
@ -2079,7 +2124,7 @@ static const unsigned int pwm0_b_mux[] = {
|
||||
PWM0_B_MARK,
|
||||
};
|
||||
|
||||
/* - PWM1_A ------------------------------------------------------------------- */
|
||||
/* - PWM1 --------------------------------------------------------------------- */
|
||||
static const unsigned int pwm1_a_pins[] = {
|
||||
/* PWM1_A */
|
||||
RCAR_GP_PIN(3, 13),
|
||||
@ -2088,7 +2133,6 @@ static const unsigned int pwm1_a_mux[] = {
|
||||
PWM1_A_MARK,
|
||||
};
|
||||
|
||||
/* - PWM1_B ------------------------------------------------------------------- */
|
||||
static const unsigned int pwm1_b_pins[] = {
|
||||
/* PWM1_B */
|
||||
RCAR_GP_PIN(2, 13),
|
||||
@ -2097,7 +2141,6 @@ static const unsigned int pwm1_b_mux[] = {
|
||||
PWM1_B_MARK,
|
||||
};
|
||||
|
||||
/* - PWM1_C ------------------------------------------------------------------- */
|
||||
static const unsigned int pwm1_c_pins[] = {
|
||||
/* PWM1_C */
|
||||
RCAR_GP_PIN(2, 17),
|
||||
@ -2106,7 +2149,7 @@ static const unsigned int pwm1_c_mux[] = {
|
||||
PWM1_C_MARK,
|
||||
};
|
||||
|
||||
/* - PWM2_A ------------------------------------------------------------------- */
|
||||
/* - PWM2 --------------------------------------------------------------------- */
|
||||
static const unsigned int pwm2_a_pins[] = {
|
||||
/* PWM2_A */
|
||||
RCAR_GP_PIN(3, 14),
|
||||
@ -2115,7 +2158,6 @@ static const unsigned int pwm2_a_mux[] = {
|
||||
PWM2_A_MARK,
|
||||
};
|
||||
|
||||
/* - PWM2_B ------------------------------------------------------------------- */
|
||||
static const unsigned int pwm2_b_pins[] = {
|
||||
/* PWM2_B */
|
||||
RCAR_GP_PIN(2, 14),
|
||||
@ -2124,7 +2166,6 @@ static const unsigned int pwm2_b_mux[] = {
|
||||
PWM2_B_MARK,
|
||||
};
|
||||
|
||||
/* - PWM2_C ------------------------------------------------------------------- */
|
||||
static const unsigned int pwm2_c_pins[] = {
|
||||
/* PWM2_C */
|
||||
RCAR_GP_PIN(2, 19),
|
||||
@ -2133,7 +2174,7 @@ static const unsigned int pwm2_c_mux[] = {
|
||||
PWM2_C_MARK,
|
||||
};
|
||||
|
||||
/* - PWM3_A ------------------------------------------------------------------- */
|
||||
/* - PWM3 --------------------------------------------------------------------- */
|
||||
static const unsigned int pwm3_a_pins[] = {
|
||||
/* PWM3_A */
|
||||
RCAR_GP_PIN(4, 14),
|
||||
@ -2142,7 +2183,6 @@ static const unsigned int pwm3_a_mux[] = {
|
||||
PWM3_A_MARK,
|
||||
};
|
||||
|
||||
/* - PWM3_B ------------------------------------------------------------------- */
|
||||
static const unsigned int pwm3_b_pins[] = {
|
||||
/* PWM3_B */
|
||||
RCAR_GP_PIN(2, 15),
|
||||
@ -2151,7 +2191,6 @@ static const unsigned int pwm3_b_mux[] = {
|
||||
PWM3_B_MARK,
|
||||
};
|
||||
|
||||
/* - PWM3_C ------------------------------------------------------------------- */
|
||||
static const unsigned int pwm3_c_pins[] = {
|
||||
/* PWM3_C */
|
||||
RCAR_GP_PIN(1, 22),
|
||||
@ -2228,7 +2267,7 @@ static const unsigned int scif0_ctrl_mux[] = {
|
||||
RTS0_N_MARK, CTS0_N_MARK,
|
||||
};
|
||||
|
||||
/* - SCIF1_A ------------------------------------------------------------------ */
|
||||
/* - SCIF1 -------------------------------------------------------------------- */
|
||||
static const unsigned int scif1_data_a_pins[] = {
|
||||
/* RX1_A, TX1_A */
|
||||
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
|
||||
@ -2251,7 +2290,6 @@ static const unsigned int scif1_ctrl_a_mux[] = {
|
||||
RTS1_N_A_MARK, CTS1_N_A_MARK,
|
||||
};
|
||||
|
||||
/* - SCIF1_B ------------------------------------------------------------------ */
|
||||
static const unsigned int scif1_data_b_pins[] = {
|
||||
/* RX1_B, TX1_B */
|
||||
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
|
||||
@ -2274,7 +2312,7 @@ static const unsigned int scif1_ctrl_b_mux[] = {
|
||||
RTS1_N_B_MARK, CTS1_N_B_MARK,
|
||||
};
|
||||
|
||||
/* - SCIF3_A ------------------------------------------------------------------ */
|
||||
/* - SCIF3 -------------------------------------------------------------------- */
|
||||
static const unsigned int scif3_data_a_pins[] = {
|
||||
/* RX3_A, TX3_A */
|
||||
RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
|
||||
@ -2297,7 +2335,6 @@ static const unsigned int scif3_ctrl_a_mux[] = {
|
||||
RTS3_N_A_MARK, CTS3_N_A_MARK,
|
||||
};
|
||||
|
||||
/* - SCIF3_B ------------------------------------------------------------------ */
|
||||
static const unsigned int scif3_data_b_pins[] = {
|
||||
/* RX3_B, TX3_B */
|
||||
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
|
||||
@ -2376,7 +2413,7 @@ static const unsigned int ssi_ctrl_mux[] = {
|
||||
SSI_SCK_MARK, SSI_WS_MARK,
|
||||
};
|
||||
|
||||
/* - TPU_A ------------------------------------------------------------------- */
|
||||
/* - TPU --------------------------------------------------------------------- */
|
||||
static const unsigned int tpu_to0_a_pins[] = {
|
||||
/* TPU0TO0_A */
|
||||
RCAR_GP_PIN(2, 8),
|
||||
@ -2406,7 +2443,6 @@ static const unsigned int tpu_to3_a_mux[] = {
|
||||
TPU0TO3_A_MARK,
|
||||
};
|
||||
|
||||
/* - TPU_B ------------------------------------------------------------------- */
|
||||
static const unsigned int tpu_to0_b_pins[] = {
|
||||
/* TPU0TO0_B */
|
||||
RCAR_GP_PIN(1, 25),
|
||||
@ -2444,6 +2480,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(avb0_magic),
|
||||
SH_PFC_PIN_GROUP(avb0_phy_int),
|
||||
SH_PFC_PIN_GROUP(avb0_mdio),
|
||||
SH_PFC_PIN_GROUP(avb0_mii),
|
||||
SH_PFC_PIN_GROUP(avb0_rgmii),
|
||||
SH_PFC_PIN_GROUP(avb0_txcrefclk),
|
||||
SH_PFC_PIN_GROUP(avb0_avtp_pps),
|
||||
@ -2454,6 +2491,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(avb1_magic),
|
||||
SH_PFC_PIN_GROUP(avb1_phy_int),
|
||||
SH_PFC_PIN_GROUP(avb1_mdio),
|
||||
SH_PFC_PIN_GROUP(avb1_mii),
|
||||
SH_PFC_PIN_GROUP(avb1_rgmii),
|
||||
SH_PFC_PIN_GROUP(avb1_txcrefclk),
|
||||
SH_PFC_PIN_GROUP(avb1_avtp_pps),
|
||||
@ -2628,6 +2666,7 @@ static const char * const avb0_groups[] = {
|
||||
"avb0_magic",
|
||||
"avb0_phy_int",
|
||||
"avb0_mdio",
|
||||
"avb0_mii",
|
||||
"avb0_rgmii",
|
||||
"avb0_txcrefclk",
|
||||
"avb0_avtp_pps",
|
||||
@ -2640,6 +2679,7 @@ static const char * const avb1_groups[] = {
|
||||
"avb1_magic",
|
||||
"avb1_phy_int",
|
||||
"avb1_mdio",
|
||||
"avb1_mii",
|
||||
"avb1_rgmii",
|
||||
"avb1_txcrefclk",
|
||||
"avb1_avtp_pps",
|
||||
|
||||
@ -4024,7 +4024,7 @@ static const struct pinmux_irq pinmux_irqs[] = {
|
||||
|
||||
static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)
|
||||
{
|
||||
struct sh_pfc *pfc = reg->reg_data;
|
||||
struct sh_pfc *pfc = rdev_get_drvdata(reg);
|
||||
void __iomem *addr = pfc->windows[1].virt + 4;
|
||||
unsigned long flags;
|
||||
u32 value;
|
||||
@ -4057,7 +4057,7 @@ static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg)
|
||||
|
||||
static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)
|
||||
{
|
||||
struct sh_pfc *pfc = reg->reg_data;
|
||||
struct sh_pfc *pfc = rdev_get_drvdata(reg);
|
||||
void __iomem *addr = pfc->windows[1].virt + 4;
|
||||
unsigned long flags;
|
||||
u32 value;
|
||||
|
||||
@ -852,7 +852,6 @@ static const struct gpio_chip rza1_gpiochip_template = {
|
||||
*/
|
||||
static int rza1_dt_node_pin_count(struct device_node *np)
|
||||
{
|
||||
struct device_node *child;
|
||||
struct property *of_pins;
|
||||
unsigned int npins;
|
||||
|
||||
@ -861,12 +860,10 @@ static int rza1_dt_node_pin_count(struct device_node *np)
|
||||
return of_pins->length / sizeof(u32);
|
||||
|
||||
npins = 0;
|
||||
for_each_child_of_node(np, child) {
|
||||
for_each_child_of_node_scoped(np, child) {
|
||||
of_pins = of_find_property(child, "pinmux", NULL);
|
||||
if (!of_pins) {
|
||||
of_node_put(child);
|
||||
if (!of_pins)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
npins += of_pins->length / sizeof(u32);
|
||||
}
|
||||
@ -986,7 +983,6 @@ static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct rza1_mux_conf *mux_confs, *mux_conf;
|
||||
unsigned int *grpins, *grpin;
|
||||
struct device_node *child;
|
||||
const char *grpname;
|
||||
const char **fngrps;
|
||||
int ret, npins;
|
||||
@ -1023,13 +1019,11 @@ static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
|
||||
ret = rza1_parse_pinmux_node(rza1_pctl, np, mux_conf, grpin);
|
||||
if (ret == -ENOENT)
|
||||
for_each_child_of_node(np, child) {
|
||||
for_each_child_of_node_scoped(np, child) {
|
||||
ret = rza1_parse_pinmux_node(rza1_pctl, child, mux_conf,
|
||||
grpin);
|
||||
if (ret < 0) {
|
||||
of_node_put(child);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
grpin += ret;
|
||||
mux_conf += ret;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -404,7 +404,6 @@ static int rzn1_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_map **map,
|
||||
unsigned int *num_maps)
|
||||
{
|
||||
struct device_node *child;
|
||||
int ret;
|
||||
|
||||
*map = NULL;
|
||||
@ -414,12 +413,10 @@ static int rzn1_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
for_each_child_of_node(np, child) {
|
||||
for_each_child_of_node_scoped(np, child) {
|
||||
ret = rzn1_dt_node_to_map_one(pctldev, child, map, num_maps);
|
||||
if (ret < 0) {
|
||||
of_node_put(child);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
@ -740,13 +737,12 @@ static int rzn1_pinctrl_parse_groups(struct device_node *np,
|
||||
|
||||
static int rzn1_pinctrl_count_function_groups(struct device_node *np)
|
||||
{
|
||||
struct device_node *child;
|
||||
int count = 0;
|
||||
|
||||
if (of_property_count_u32_elems(np, RZN1_PINS_PROP) > 0)
|
||||
count++;
|
||||
|
||||
for_each_child_of_node(np, child) {
|
||||
for_each_child_of_node_scoped(np, child) {
|
||||
if (of_property_count_u32_elems(child, RZN1_PINS_PROP) > 0)
|
||||
count++;
|
||||
}
|
||||
@ -760,7 +756,6 @@ static int rzn1_pinctrl_parse_functions(struct device_node *np,
|
||||
{
|
||||
struct rzn1_pmx_func *func;
|
||||
struct rzn1_pin_group *grp;
|
||||
struct device_node *child;
|
||||
unsigned int i = 0;
|
||||
int ret;
|
||||
|
||||
@ -793,15 +788,13 @@ static int rzn1_pinctrl_parse_functions(struct device_node *np,
|
||||
ipctl->ngroups++;
|
||||
}
|
||||
|
||||
for_each_child_of_node(np, child) {
|
||||
for_each_child_of_node_scoped(np, child) {
|
||||
func->groups[i] = child->name;
|
||||
grp = &ipctl->groups[ipctl->ngroups];
|
||||
grp->func = func->name;
|
||||
ret = rzn1_pinctrl_parse_groups(child, grp, ipctl);
|
||||
if (ret < 0) {
|
||||
of_node_put(child);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
i++;
|
||||
ipctl->ngroups++;
|
||||
}
|
||||
@ -816,7 +809,6 @@ static int rzn1_pinctrl_probe_dt(struct platform_device *pdev,
|
||||
struct rzn1_pinctrl *ipctl)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct device_node *child;
|
||||
unsigned int maxgroups = 0;
|
||||
unsigned int i = 0;
|
||||
int nfuncs = 0;
|
||||
@ -834,7 +826,7 @@ static int rzn1_pinctrl_probe_dt(struct platform_device *pdev,
|
||||
return -ENOMEM;
|
||||
|
||||
ipctl->ngroups = 0;
|
||||
for_each_child_of_node(np, child)
|
||||
for_each_child_of_node_scoped(np, child)
|
||||
maxgroups += rzn1_pinctrl_count_function_groups(child);
|
||||
|
||||
ipctl->groups = devm_kmalloc_array(&pdev->dev,
|
||||
@ -844,12 +836,10 @@ static int rzn1_pinctrl_probe_dt(struct platform_device *pdev,
|
||||
if (!ipctl->groups)
|
||||
return -ENOMEM;
|
||||
|
||||
for_each_child_of_node(np, child) {
|
||||
for_each_child_of_node_scoped(np, child) {
|
||||
ret = rzn1_pinctrl_parse_functions(child, ipctl, i++);
|
||||
if (ret < 0) {
|
||||
of_node_put(child);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
@ -388,7 +388,6 @@ static int rzv2m_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
unsigned int *num_maps)
|
||||
{
|
||||
struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct device_node *child;
|
||||
unsigned int index;
|
||||
int ret;
|
||||
|
||||
@ -396,13 +395,11 @@ static int rzv2m_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
*num_maps = 0;
|
||||
index = 0;
|
||||
|
||||
for_each_child_of_node(np, child) {
|
||||
for_each_child_of_node_scoped(np, child) {
|
||||
ret = rzv2m_dt_subnode_to_map(pctldev, child, np, map,
|
||||
num_maps, &index);
|
||||
if (ret < 0) {
|
||||
of_node_put(child);
|
||||
if (ret < 0)
|
||||
goto done;
|
||||
}
|
||||
}
|
||||
|
||||
if (*num_maps == 0) {
|
||||
|
||||
@ -241,7 +241,6 @@ static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
{
|
||||
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct device *dev = pmx->pfc->dev;
|
||||
struct device_node *child;
|
||||
unsigned int index;
|
||||
int ret;
|
||||
|
||||
@ -249,13 +248,11 @@ static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
*num_maps = 0;
|
||||
index = 0;
|
||||
|
||||
for_each_child_of_node(np, child) {
|
||||
for_each_child_of_node_scoped(np, child) {
|
||||
ret = sh_pfc_dt_subnode_to_map(pctldev, child, map, num_maps,
|
||||
&index);
|
||||
if (ret < 0) {
|
||||
of_node_put(child);
|
||||
if (ret < 0)
|
||||
goto done;
|
||||
}
|
||||
}
|
||||
|
||||
/* If no mapping has been found in child nodes try the config node. */
|
||||
|
||||
@ -151,24 +151,19 @@ static int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
unsigned *num_maps)
|
||||
{
|
||||
struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct device_node *np;
|
||||
struct property *prop;
|
||||
const char *function, *group;
|
||||
int ret, index = 0, count = 0;
|
||||
|
||||
/* calculate number of maps required */
|
||||
for_each_child_of_node(np_config, np) {
|
||||
for_each_child_of_node_scoped(np_config, np) {
|
||||
ret = of_property_read_string(np, "st,function", &function);
|
||||
if (ret < 0) {
|
||||
of_node_put(np);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = of_property_count_strings(np, "st,pins");
|
||||
if (ret < 0) {
|
||||
of_node_put(np);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
count += ret;
|
||||
}
|
||||
@ -182,7 +177,7 @@ static int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
if (!*map)
|
||||
return -ENOMEM;
|
||||
|
||||
for_each_child_of_node(np_config, np) {
|
||||
for_each_child_of_node_scoped(np_config, np) {
|
||||
of_property_read_string(np, "st,function", &function);
|
||||
of_property_for_each_string(np, "st,pins", prop, group) {
|
||||
(*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
|
||||
|
||||
@ -934,7 +934,6 @@ static int sprd_pinctrl_parse_dt(struct sprd_pinctrl *sprd_pctl)
|
||||
{
|
||||
struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
|
||||
struct device_node *np = sprd_pctl->dev->of_node;
|
||||
struct device_node *child, *sub_child;
|
||||
struct sprd_pin_group *grp;
|
||||
const char **temp;
|
||||
int ret;
|
||||
@ -962,25 +961,20 @@ static int sprd_pinctrl_parse_dt(struct sprd_pinctrl *sprd_pctl)
|
||||
temp = info->grp_names;
|
||||
grp = info->groups;
|
||||
|
||||
for_each_child_of_node(np, child) {
|
||||
for_each_child_of_node_scoped(np, child) {
|
||||
ret = sprd_pinctrl_parse_groups(child, sprd_pctl, grp);
|
||||
if (ret) {
|
||||
of_node_put(child);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
*temp++ = grp->name;
|
||||
grp++;
|
||||
|
||||
if (of_get_child_count(child) > 0) {
|
||||
for_each_child_of_node(child, sub_child) {
|
||||
for_each_child_of_node_scoped(child, sub_child) {
|
||||
ret = sprd_pinctrl_parse_groups(sub_child,
|
||||
sprd_pctl, grp);
|
||||
if (ret) {
|
||||
of_node_put(sub_child);
|
||||
of_node_put(child);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
*temp++ = grp->name;
|
||||
grp++;
|
||||
|
||||
@ -480,7 +480,6 @@ static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
{
|
||||
struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct device *dev = sfp->gc.parent;
|
||||
struct device_node *child;
|
||||
struct pinctrl_map *map;
|
||||
const char **pgnames;
|
||||
const char *grpname;
|
||||
@ -492,20 +491,18 @@ static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
|
||||
nmaps = 0;
|
||||
ngroups = 0;
|
||||
for_each_available_child_of_node(np, child) {
|
||||
for_each_available_child_of_node_scoped(np, child) {
|
||||
int npinmux = of_property_count_u32_elems(child, "pinmux");
|
||||
int npins = of_property_count_u32_elems(child, "pins");
|
||||
|
||||
if (npinmux > 0 && npins > 0) {
|
||||
dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: both pinmux and pins set\n",
|
||||
np, child);
|
||||
of_node_put(child);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (npinmux == 0 && npins == 0) {
|
||||
dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: neither pinmux nor pins set\n",
|
||||
np, child);
|
||||
of_node_put(child);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
@ -527,14 +524,14 @@ static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
nmaps = 0;
|
||||
ngroups = 0;
|
||||
mutex_lock(&sfp->mutex);
|
||||
for_each_available_child_of_node(np, child) {
|
||||
for_each_available_child_of_node_scoped(np, child) {
|
||||
int npins;
|
||||
int i;
|
||||
|
||||
grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);
|
||||
if (!grpname) {
|
||||
ret = -ENOMEM;
|
||||
goto put_child;
|
||||
goto free_map;
|
||||
}
|
||||
|
||||
pgnames[ngroups++] = grpname;
|
||||
@ -543,18 +540,18 @@ static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
|
||||
if (!pins) {
|
||||
ret = -ENOMEM;
|
||||
goto put_child;
|
||||
goto free_map;
|
||||
}
|
||||
|
||||
pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL);
|
||||
if (!pinmux) {
|
||||
ret = -ENOMEM;
|
||||
goto put_child;
|
||||
goto free_map;
|
||||
}
|
||||
|
||||
ret = of_property_read_u32_array(child, "pinmux", pinmux, npins);
|
||||
if (ret)
|
||||
goto put_child;
|
||||
goto free_map;
|
||||
|
||||
for (i = 0; i < npins; i++) {
|
||||
unsigned int gpio = starfive_pinmux_to_gpio(pinmux[i]);
|
||||
@ -570,7 +567,7 @@ static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
|
||||
if (!pins) {
|
||||
ret = -ENOMEM;
|
||||
goto put_child;
|
||||
goto free_map;
|
||||
}
|
||||
|
||||
pinmux = NULL;
|
||||
@ -580,18 +577,18 @@ static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
|
||||
ret = of_property_read_u32_index(child, "pins", i, &v);
|
||||
if (ret)
|
||||
goto put_child;
|
||||
goto free_map;
|
||||
pins[i] = v;
|
||||
}
|
||||
} else {
|
||||
ret = -EINVAL;
|
||||
goto put_child;
|
||||
goto free_map;
|
||||
}
|
||||
|
||||
ret = pinctrl_generic_add_group(pctldev, grpname, pins, npins, pinmux);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "error adding group %s: %d\n", grpname, ret);
|
||||
goto put_child;
|
||||
goto free_map;
|
||||
}
|
||||
|
||||
ret = pinconf_generic_parse_dt_config(child, pctldev,
|
||||
@ -600,7 +597,7 @@ static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
if (ret) {
|
||||
dev_err(dev, "error parsing pin config of group %s: %d\n",
|
||||
grpname, ret);
|
||||
goto put_child;
|
||||
goto free_map;
|
||||
}
|
||||
|
||||
/* don't create a map if there are no pinconf settings */
|
||||
@ -623,8 +620,6 @@ static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
mutex_unlock(&sfp->mutex);
|
||||
return 0;
|
||||
|
||||
put_child:
|
||||
of_node_put(child);
|
||||
free_map:
|
||||
pinctrl_utils_free_map(pctldev, map, nmaps);
|
||||
mutex_unlock(&sfp->mutex);
|
||||
|
||||
@ -150,7 +150,7 @@ static int jh7110_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
nmaps = 0;
|
||||
ngroups = 0;
|
||||
mutex_lock(&sfp->mutex);
|
||||
for_each_available_child_of_node(np, child) {
|
||||
for_each_available_child_of_node_scoped(np, child) {
|
||||
int npins = of_property_count_u32_elems(child, "pinmux");
|
||||
int *pins;
|
||||
u32 *pinmux;
|
||||
@ -161,13 +161,13 @@ static int jh7110_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
"invalid pinctrl group %pOFn.%pOFn: pinmux not set\n",
|
||||
np, child);
|
||||
ret = -EINVAL;
|
||||
goto put_child;
|
||||
goto free_map;
|
||||
}
|
||||
|
||||
grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);
|
||||
if (!grpname) {
|
||||
ret = -ENOMEM;
|
||||
goto put_child;
|
||||
goto free_map;
|
||||
}
|
||||
|
||||
pgnames[ngroups++] = grpname;
|
||||
@ -175,18 +175,18 @@ static int jh7110_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
|
||||
if (!pins) {
|
||||
ret = -ENOMEM;
|
||||
goto put_child;
|
||||
goto free_map;
|
||||
}
|
||||
|
||||
pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL);
|
||||
if (!pinmux) {
|
||||
ret = -ENOMEM;
|
||||
goto put_child;
|
||||
goto free_map;
|
||||
}
|
||||
|
||||
ret = of_property_read_u32_array(child, "pinmux", pinmux, npins);
|
||||
if (ret)
|
||||
goto put_child;
|
||||
goto free_map;
|
||||
|
||||
for (i = 0; i < npins; i++)
|
||||
pins[i] = jh7110_pinmux_pin(pinmux[i]);
|
||||
@ -200,7 +200,7 @@ static int jh7110_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
pins, npins, pinmux);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "error adding group %s: %d\n", grpname, ret);
|
||||
goto put_child;
|
||||
goto free_map;
|
||||
}
|
||||
|
||||
ret = pinconf_generic_parse_dt_config(child, pctldev,
|
||||
@ -209,7 +209,7 @@ static int jh7110_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
if (ret) {
|
||||
dev_err(dev, "error parsing pin config of group %s: %d\n",
|
||||
grpname, ret);
|
||||
goto put_child;
|
||||
goto free_map;
|
||||
}
|
||||
|
||||
/* don't create a map if there are no pinconf settings */
|
||||
@ -233,8 +233,6 @@ static int jh7110_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
*num_maps = nmaps;
|
||||
return 0;
|
||||
|
||||
put_child:
|
||||
of_node_put(child);
|
||||
free_map:
|
||||
pinctrl_utils_free_map(pctldev, map, nmaps);
|
||||
mutex_unlock(&sfp->mutex);
|
||||
|
||||
@ -670,7 +670,6 @@ static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
struct device_node *np_config,
|
||||
struct pinctrl_map **map, unsigned *num_maps)
|
||||
{
|
||||
struct device_node *np;
|
||||
unsigned reserved_maps;
|
||||
int ret;
|
||||
|
||||
@ -678,12 +677,11 @@ static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
*num_maps = 0;
|
||||
reserved_maps = 0;
|
||||
|
||||
for_each_child_of_node(np_config, np) {
|
||||
for_each_child_of_node_scoped(np_config, np) {
|
||||
ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
|
||||
&reserved_maps, num_maps);
|
||||
if (ret < 0) {
|
||||
pinctrl_utils_free_map(pctldev, *map, *num_maps);
|
||||
of_node_put(np);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
@ -238,20 +238,17 @@ static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl,
|
||||
{
|
||||
struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
|
||||
unsigned int reserved_maps = 0;
|
||||
struct device_node *np;
|
||||
int err;
|
||||
|
||||
*num_maps = 0;
|
||||
*maps = NULL;
|
||||
|
||||
for_each_child_of_node(parent, np) {
|
||||
for_each_child_of_node_scoped(parent, np) {
|
||||
err = tegra_xusb_padctl_parse_subnode(padctl, np, maps,
|
||||
&reserved_maps,
|
||||
num_maps);
|
||||
if (err < 0) {
|
||||
of_node_put(np);
|
||||
if (err < 0)
|
||||
return err;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
@ -188,20 +188,18 @@ static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
unsigned *num_maps)
|
||||
{
|
||||
unsigned reserved_maps;
|
||||
struct device_node *np;
|
||||
int ret;
|
||||
|
||||
reserved_maps = 0;
|
||||
*map = NULL;
|
||||
*num_maps = 0;
|
||||
|
||||
for_each_child_of_node(np_config, np) {
|
||||
for_each_child_of_node_scoped(np_config, np) {
|
||||
ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
|
||||
&reserved_maps, num_maps);
|
||||
if (ret < 0) {
|
||||
pinctrl_utils_free_map(pctldev, *map,
|
||||
*num_maps);
|
||||
of_node_put(np);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
@ -822,53 +822,48 @@ MODULE_DEVICE_TABLE(of, ti_iodelay_of_match);
|
||||
static int ti_iodelay_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = of_node_get(dev->of_node);
|
||||
struct device_node *np __free(device_node) = of_node_get(dev->of_node);
|
||||
struct resource *res;
|
||||
struct ti_iodelay_device *iod;
|
||||
int ret = 0;
|
||||
int ret;
|
||||
|
||||
if (!np) {
|
||||
ret = -EINVAL;
|
||||
dev_err(dev, "No OF node\n");
|
||||
goto exit_out;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
iod = devm_kzalloc(dev, sizeof(*iod), GFP_KERNEL);
|
||||
if (!iod) {
|
||||
ret = -ENOMEM;
|
||||
goto exit_out;
|
||||
}
|
||||
if (!iod)
|
||||
return -ENOMEM;
|
||||
|
||||
iod->dev = dev;
|
||||
iod->reg_data = device_get_match_data(dev);
|
||||
if (!iod->reg_data) {
|
||||
ret = -EINVAL;
|
||||
dev_err(dev, "No DATA match\n");
|
||||
goto exit_out;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* So far We can assume there is only 1 bank of registers */
|
||||
iod->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
|
||||
if (IS_ERR(iod->reg_base)) {
|
||||
ret = PTR_ERR(iod->reg_base);
|
||||
goto exit_out;
|
||||
}
|
||||
if (IS_ERR(iod->reg_base))
|
||||
return PTR_ERR(iod->reg_base);
|
||||
|
||||
iod->phys_base = res->start;
|
||||
|
||||
iod->regmap = devm_regmap_init_mmio(dev, iod->reg_base,
|
||||
iod->reg_data->regmap_config);
|
||||
if (IS_ERR(iod->regmap)) {
|
||||
dev_err(dev, "Regmap MMIO init failed.\n");
|
||||
ret = PTR_ERR(iod->regmap);
|
||||
goto exit_out;
|
||||
return PTR_ERR(iod->regmap);
|
||||
}
|
||||
|
||||
ret = ti_iodelay_pinconf_init_dev(iod);
|
||||
if (ret)
|
||||
goto exit_out;
|
||||
return ret;
|
||||
|
||||
ret = ti_iodelay_alloc_pins(dev, iod, res->start);
|
||||
if (ret)
|
||||
goto exit_out;
|
||||
return ret;
|
||||
|
||||
iod->desc.pctlops = &ti_iodelay_pinctrl_ops;
|
||||
/* no pinmux ops - we are pinconf */
|
||||
@ -876,19 +871,15 @@ static int ti_iodelay_probe(struct platform_device *pdev)
|
||||
iod->desc.name = dev_name(dev);
|
||||
iod->desc.owner = THIS_MODULE;
|
||||
|
||||
ret = pinctrl_register_and_init(&iod->desc, dev, iod, &iod->pctl);
|
||||
ret = devm_pinctrl_register_and_init(dev, &iod->desc, iod, &iod->pctl);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to register pinctrl\n");
|
||||
goto exit_out;
|
||||
return ret;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, iod);
|
||||
|
||||
return pinctrl_enable(iod->pctl);
|
||||
|
||||
exit_out:
|
||||
of_node_put(np);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -899,9 +890,6 @@ static void ti_iodelay_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct ti_iodelay_device *iod = platform_get_drvdata(pdev);
|
||||
|
||||
if (iod->pctl)
|
||||
pinctrl_unregister(iod->pctl);
|
||||
|
||||
ti_iodelay_pinconf_deinit_dev(iod);
|
||||
|
||||
/* Expect other allocations to be freed by devm */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user