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net: phy: Broadcom Cygnus internal Etherent PHY driver
Add support for the Broadcom Cygnus SoCs internal PHY's. The PHYs are 1000M/100M/10M capable with support for 'EEE' and 'APD' (Auto Power Down). This driver supports the following Broadcom Cygnus SoCs: - BCM583XX (BCM58300, BCM58302, BCM58303, BCM58305) - BCM113XX (BCM11300, BCM11320, BCM11350, BCM11360) The PHY's on these SoC's require some workarounds for stable operation, both during configuration time and during suspend/resume. This driver handles the application of the workarounds. Signed-off-by: Arun Parameswaran <arunp@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Arun Parameswaran
David S. Miller
parent
a1cba5613e
commit
8e185d6997
@ -79,6 +79,19 @@ config BROADCOM_PHY
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Currently supports the BCM5411, BCM5421, BCM5461, BCM54616S, BCM5464,
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BCM5481 and BCM5482 PHYs.
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config BCM_CYGNUS_PHY
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tristate "Drivers for Broadcom Cygnus SoC internal PHY"
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depends on ARCH_BCM_CYGNUS || COMPILE_TEST
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depends on MDIO_BCM_IPROC
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select BCM_NET_PHYLIB
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---help---
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This PHY driver is for the 1G internal PHYs of the Broadcom
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Cygnus Family SoC.
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Currently supports internal PHY's used in the BCM11300,
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BCM11320, BCM11350, BCM11360, BCM58300, BCM58302,
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BCM58303 & BCM58305 Broadcom Cygnus SoCs.
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config BCM63XX_PHY
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tristate "Drivers for Broadcom 63xx SOCs internal PHY"
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depends on BCM63XX
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@ -17,6 +17,7 @@ obj-$(CONFIG_BROADCOM_PHY) += broadcom.o
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obj-$(CONFIG_BCM63XX_PHY) += bcm63xx.o
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obj-$(CONFIG_BCM7XXX_PHY) += bcm7xxx.o
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obj-$(CONFIG_BCM87XX_PHY) += bcm87xx.o
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obj-$(CONFIG_BCM_CYGNUS_PHY) += bcm-cygnus.o
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obj-$(CONFIG_ICPLUS_PHY) += icplus.o
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obj-$(CONFIG_REALTEK_PHY) += realtek.o
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obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o
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158
drivers/net/phy/bcm-cygnus.c
Normal file
158
drivers/net/phy/bcm-cygnus.c
Normal file
@ -0,0 +1,158 @@
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/*
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* Copyright (C) 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Broadcom Cygnus SoC internal transceivers support. */
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#include "bcm-phy-lib.h"
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#include <linux/brcmphy.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/phy.h>
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/* Broadcom Cygnus Phy specific registers */
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#define MII_BCM_CYGNUS_AFE_VDAC_ICTRL_0 0x91E5 /* VDAL Control register */
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static int bcm_cygnus_afe_config(struct phy_device *phydev)
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{
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int rc;
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/* ensure smdspclk is enabled */
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rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, 0x0c30);
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if (rc < 0)
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return rc;
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/* AFE_VDAC_ICTRL_0 bit 7:4 Iq=1100 for 1g 10bt, normal modes */
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rc = bcm_phy_write_misc(phydev, 0x39, 0x01, 0xA7C8);
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if (rc < 0)
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return rc;
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/* AFE_HPF_TRIM_OTHERS bit11=1, short cascode enable for all modes*/
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rc = bcm_phy_write_misc(phydev, 0x3A, 0x00, 0x0803);
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if (rc < 0)
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return rc;
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/* AFE_TX_CONFIG_1 bit 7:4 Iq=1100 for test modes */
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rc = bcm_phy_write_misc(phydev, 0x3A, 0x01, 0xA740);
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if (rc < 0)
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return rc;
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/* AFE TEMPSEN_OTHERS rcal_HT, rcal_LT 10000 */
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rc = bcm_phy_write_misc(phydev, 0x3A, 0x03, 0x8400);
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if (rc < 0)
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return rc;
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/* AFE_FUTURE_RSV bit 2:0 rccal <2:0>=100 */
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rc = bcm_phy_write_misc(phydev, 0x3B, 0x00, 0x0004);
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if (rc < 0)
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return rc;
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/* Adjust bias current trim to overcome digital offSet */
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rc = phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x02);
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if (rc < 0)
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return rc;
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/* make rcal=100, since rdb default is 000 */
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rc = bcm_phy_write_exp(phydev, MII_BRCM_CORE_EXPB1, 0x10);
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if (rc < 0)
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return rc;
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/* CORE_EXPB0, Reset R_CAL/RC_CAL Engine */
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rc = bcm_phy_write_exp(phydev, MII_BRCM_CORE_EXPB0, 0x10);
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if (rc < 0)
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return rc;
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/* CORE_EXPB0, Disable Reset R_CAL/RC_CAL Engine */
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rc = bcm_phy_write_exp(phydev, MII_BRCM_CORE_EXPB0, 0x00);
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return 0;
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}
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static int bcm_cygnus_config_init(struct phy_device *phydev)
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{
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int reg, rc;
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reg = phy_read(phydev, MII_BCM54XX_ECR);
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if (reg < 0)
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return reg;
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/* Mask interrupts globally. */
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reg |= MII_BCM54XX_ECR_IM;
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rc = phy_write(phydev, MII_BCM54XX_ECR, reg);
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if (rc)
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return rc;
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/* Unmask events of interest */
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reg = ~(MII_BCM54XX_INT_DUPLEX |
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MII_BCM54XX_INT_SPEED |
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MII_BCM54XX_INT_LINK);
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rc = phy_write(phydev, MII_BCM54XX_IMR, reg);
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if (rc)
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return rc;
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/* Apply AFE settings for the PHY */
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rc = bcm_cygnus_afe_config(phydev);
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if (rc)
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return rc;
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/* Advertise EEE */
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rc = bcm_phy_enable_eee(phydev);
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if (rc)
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return rc;
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/* Enable APD */
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return bcm_phy_enable_apd(phydev, false);
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}
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static int bcm_cygnus_resume(struct phy_device *phydev)
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{
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int rc;
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genphy_resume(phydev);
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/* Re-initialize the PHY to apply AFE work-arounds and
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* configurations when coming out of suspend.
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*/
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rc = bcm_cygnus_config_init(phydev);
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if (rc)
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return rc;
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/* restart auto negotiation with the new settings */
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return genphy_config_aneg(phydev);
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}
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static struct phy_driver bcm_cygnus_phy_driver[] = {
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{
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.phy_id = PHY_ID_BCM_CYGNUS,
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.phy_id_mask = 0xfffffff0,
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.name = "Broadcom Cygnus PHY",
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.features = PHY_GBIT_FEATURES |
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SUPPORTED_Pause | SUPPORTED_Asym_Pause,
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.config_init = bcm_cygnus_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = bcm_phy_ack_intr,
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.config_intr = bcm_phy_config_intr,
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.suspend = genphy_suspend,
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.resume = bcm_cygnus_resume,
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} };
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static struct mdio_device_id __maybe_unused bcm_cygnus_phy_tbl[] = {
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{ PHY_ID_BCM_CYGNUS, 0xfffffff0, },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, bcm_cygnus_phy_tbl);
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module_phy_driver(bcm_cygnus_phy_driver);
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MODULE_DESCRIPTION("Broadcom Cygnus internal PHY driver");
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Broadcom Corporation");
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@ -30,6 +30,8 @@
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#define PHY_ID_BCM7439_2 0xae025080
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#define PHY_ID_BCM7445 0x600d8510
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#define PHY_ID_BCM_CYGNUS 0xae025200
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#define PHY_BCM_OUI_MASK 0xfffffc00
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#define PHY_BCM_OUI_1 0x00206000
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#define PHY_BCM_OUI_2 0x0143bc00
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@ -216,4 +218,9 @@
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#define LPI_FEATURE_EN 0x8000
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#define LPI_FEATURE_EN_DIG1000X 0x4000
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/* Core register definitions*/
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#define MII_BRCM_CORE_BASE1E 0x1E
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#define MII_BRCM_CORE_EXPB0 0xB0
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#define MII_BRCM_CORE_EXPB1 0xB1
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#endif /* _LINUX_BRCMPHY_H */
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