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x86/speculation: Use ARCH_CAPABILITIES to skip L1D flush on vmentry
Bit 3 of ARCH_CAPABILITIES tells a hypervisor that L1D flush on vmentry is not needed. Add a new value to enum vmx_l1d_flush_state, which is used either if there is no L1TF bug at all, or if bit 3 is set in ARCH_CAPABILITIES. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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@ -70,6 +70,7 @@
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#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
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#define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */
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#define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */
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#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH (1 << 3) /* Skip L1D flush on vmentry */
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#define ARCH_CAP_SSB_NO (1 << 4) /*
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* Not susceptible to Speculative Store Bypass
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* attack, so no Speculative Store Bypass
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@ -582,6 +582,7 @@ enum vmx_l1d_flush_state {
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VMENTER_L1D_FLUSH_COND,
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VMENTER_L1D_FLUSH_ALWAYS,
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VMENTER_L1D_FLUSH_EPT_DISABLED,
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VMENTER_L1D_FLUSH_NOT_REQUIRED,
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};
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extern enum vmx_l1d_flush_state l1tf_vmx_mitigation;
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@ -755,6 +755,7 @@ static const char *l1tf_vmx_states[] = {
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[VMENTER_L1D_FLUSH_COND] = "conditional cache flushes",
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[VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes",
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[VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled",
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[VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary"
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};
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static ssize_t l1tf_show_state(char *buf)
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@ -218,6 +218,16 @@ static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
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return 0;
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}
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if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
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u64 msr;
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rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
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if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
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l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
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return 0;
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}
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}
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/* If set to auto use the default l1tf mitigation method */
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if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
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switch (l1tf_mitigation) {
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