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ASoC: AMD: Change MCLK to 48Mhz
[ Upstream commit a1b1e9880f
]
25Mhz MCLK which was earlier used was of spread type.
Thus, we were not getting accurate rate. The 48Mhz system
clk is of non-spread type and we are changing to it to get
accurate rate.
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -42,7 +42,7 @@
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#include "../codecs/da7219.h"
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#include "../codecs/da7219-aad.h"
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#define CZ_PLAT_CLK 25000000
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#define CZ_PLAT_CLK 48000000
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#define DUAL_CHANNEL 2
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static struct snd_soc_jack cz_jack;
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