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arm64: dts: freescale: add support for i.MX8DXL EVK board
This is to support the EVK (Evaluation Kit Board) for the i.MX8DXL. The patch has enabled the serial console, SD/EMMC interface, and the eqos and fec ethernet network. Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Shenwei Wang
Shawn Guo
parent
f537ee7f1e
commit
8dd495d123
@ -48,6 +48,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
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426
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
Normal file
426
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
Normal file
@ -0,0 +1,426 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019~2020, 2022 NXP
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*/
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/dts-v1/;
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#include "imx8dxl.dtsi"
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/ {
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model = "Freescale i.MX8DXL EVK";
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compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
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aliases {
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i2c2 = &i2c2;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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serial0 = &lpuart0;
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};
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chosen {
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stdout-path = &lpuart0;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0 0x40000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/*
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* Memory reserved for optee usage. Please do not use.
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* This will be automatically added to dtb if OP-TEE is installed.
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* optee@96000000 {
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* reg = <0 0x96000000 0 0x2000000>;
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* no-map;
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* };
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*/
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/* global autoconfigured region for contiguous allocations */
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0 0x14000000>;
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alloc-ranges = <0 0x98000000 0 0x14000000>;
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linux,cma-default;
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};
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};
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mux3_en: regulator-0 {
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compatible = "regulator-fixed";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "mux3_en";
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gpio = <&pca6416_2 8 GPIO_ACTIVE_LOW>;
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regulator-always-on;
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};
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reg_fec1_sel: regulator-1 {
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compatible = "regulator-fixed";
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regulator-name = "fec1_supply";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&pca6416_1 11 GPIO_ACTIVE_LOW>;
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regulator-always-on;
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status = "disabled";
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};
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reg_fec1_io: regulator-2 {
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compatible = "regulator-fixed";
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regulator-name = "fec1_io_supply";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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status = "disabled";
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};
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reg_usdhc2_vmmc: regulator-3 {
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compatible = "regulator-fixed";
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regulator-name = "SD1_SPWR";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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off-on-delay-us = <3480>;
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};
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};
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&eqos {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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nvmem-cells = <&fec_mac1>;
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nvmem-cell-names = "mac-address";
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snps,reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
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snps,reset-delays-us = <10 20 200000>;
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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eee-broken-1000t;
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qca,disable-smarteee;
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vddio-supply = <&vddio0>;
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vddio0: vddio-regulator {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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};
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};
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};
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/*
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* fec1 shares the some PINs with usdhc2.
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* by default usdhc2 is enabled in this dts.
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* Please disable usdhc2 to enable fec1
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*/
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-txid";
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phy-handle = <ðphy1>;
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fsl,magic-packet;
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rx-internal-delay-ps = <2000>;
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nvmem-cells = <&fec_mac0>;
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nvmem-cell-names = "mac-address";
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status = "disabled";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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qca,disable-smarteee;
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vddio-supply = <&vddio1>;
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vddio1: vddio-regulator {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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};
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};
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};
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&i2c2 {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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pca6416_1: gpio@20 {
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compatible = "ti,tca6416";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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pca6416_2: gpio@21 {
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compatible = "ti,tca6416";
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reg = <0x21>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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pca9548_1: i2c-mux@70 {
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x70>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0>;
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max7322: gpio@68 {
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compatible = "maxim,max7322";
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reg = <0x68>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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};
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i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x4>;
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};
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i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x5>;
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};
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i2c@6 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x6>;
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};
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};
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};
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&lpuart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart0>;
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status = "okay";
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};
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&lsio_gpio4 {
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status = "okay";
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};
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&lsio_gpio5 {
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status = "okay";
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};
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&thermal_zones {
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pmic-thermal0 {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
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trips {
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pmic_alert0: trip0 {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "passive";
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};
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pmic_crit0: trip1 {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&pmic_alert0>;
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cooling-device =
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<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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bus-width = <8>;
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no-sd;
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no-sdio;
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non-removable;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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bus-width = <4>;
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vmmc-supply = <®_usdhc2_vmmc>;
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cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
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wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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pinctrl_hog: hoggrp {
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fsl,pins = <
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IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
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IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0
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IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 0x0600004c
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IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c
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>;
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};
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pinctrl_usbotg1: usbotg1grp {
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fsl,pins = <
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IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021
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>;
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};
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pinctrl_usbotg2: usbotg2grp {
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fsl,pins = <
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IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR 0x00000021
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>;
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};
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pinctrl_eqos: eqosgrp {
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fsl,pins = <
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IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020
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IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020
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IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020
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IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020
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IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020
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IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020
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IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020
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IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020
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IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020
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IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020
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IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020
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IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020
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IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020
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IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
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IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
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IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020
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IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
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IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060
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IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060
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IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060
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IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060
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IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060
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IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060
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IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060
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IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060
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IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060
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IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060
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IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060
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IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060
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>;
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};
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pinctrl_lpspi3: lpspi3grp {
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fsl,pins = <
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IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x6000040
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IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x6000040
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IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x6000040
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IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x6000040
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021
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IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021
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>;
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};
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pinctrl_cm40_lpuart: cm40lpuartgrp {
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fsl,pins = <
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IMX8DXL_ADC_IN2_M40_UART0_RX 0x06000020
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IMX8DXL_ADC_IN3_M40_UART0_TX 0x06000020
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021
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IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021
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>;
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};
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pinctrl_lpuart0: lpuart0grp {
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fsl,pins = <
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IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020
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IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
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IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
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IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
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IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
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IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
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IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
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IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
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IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
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IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
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IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
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IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
|
||||
fsl,pins = <
|
||||
IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */
|
||||
IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */
|
||||
IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
|
||||
IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
|
||||
IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
|
||||
IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
|
||||
IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
|
||||
IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
|
||||
IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021
|
||||
>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user