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Merge tag 'drivers_soc_for_5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into arm/drivers
drivers: soc: TI SOC changes for 5.11 - ti_sci changes towards DMSS support - Static warning fixes - Kconfig update for Keystone ARM64 socs - AM64X SOC family support * tag 'drivers_soc_for_5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone: (23 commits) drivers: soc: ti: knav_qmss_queue: Fix error return code in knav_queue_probe soc: ti: Fix reference imbalance in knav_dma_probe soc: ti: pruss: Remove wrong check against *get_match_data return value soc: ti: Kconfig: Drop ARM64 SoC specific configs soc: ti: k3-ringacc: Provide documentation for 'k3_ring's 'state' soc: ti: wkup_m3_ipc: Document 'm3_ipc' parameter throughout soc: ti: pm33xx: Remove set but unused variable 'ret' soc: ti: knav_dma: Fix a kernel function doc formatting issue soc: ti: knav_qmss_queue: Fix a whole host of function documentation issues soc: ti: knav_qmss_queue: Remove set but unchecked variable 'ret' soc: ti: omap-prm: Do not check rstst bit on deassert if already deasserted soc: ti: knav_qmss: fix reference leak in knav_queue_probe soc: ti: k3-socinfo: Add entry for AM64X SoC family soc: ti: k3-ringacc: Use correct device for allocation in RING mode firmware: ti_sci: rm: Remove unused config() from ti_sci_rm_ringacc_ops soc: ti: k3-ringacc: Use the ti_sci set_cfg callback for ring configuration firmware: ti_sci: rm: Add new ops for ring configuration firmware: ti_sci: rm: Remove ring_get_config support firmware: ti_sci: rm: Add support for extended_ch_type for tx channel soc: ti: ti_sci_inta_msi: Add support for second range in resource ranges ... Link: https://lore.kernel.org/r/1606851405-26338-1-git-send-email-santosh.shilimkar@oracle.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
8dc0aac1cc
@ -1703,14 +1703,14 @@ fail:
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* @subtype: Resource assignment subtype that is being requested
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* from the given device.
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* @s_host: Host processor ID to which the resources are allocated
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* @range_start: Start index of the resource range
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* @range_num: Number of resources in the range
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* @desc: Pointer to ti_sci_resource_desc to be updated with the
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* resource range start index and number of resources
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*
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* Return: 0 if all went fine, else return appropriate error.
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*/
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static int ti_sci_get_resource_range(const struct ti_sci_handle *handle,
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u32 dev_id, u8 subtype, u8 s_host,
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u16 *range_start, u16 *range_num)
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struct ti_sci_resource_desc *desc)
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{
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struct ti_sci_msg_resp_get_resource_range *resp;
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struct ti_sci_msg_req_get_resource_range *req;
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@ -1721,7 +1721,7 @@ static int ti_sci_get_resource_range(const struct ti_sci_handle *handle,
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if (IS_ERR(handle))
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return PTR_ERR(handle);
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if (!handle)
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if (!handle || !desc)
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return -EINVAL;
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info = handle_to_ti_sci_info(handle);
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@ -1751,11 +1751,14 @@ static int ti_sci_get_resource_range(const struct ti_sci_handle *handle,
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if (!ti_sci_is_response_ack(resp)) {
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ret = -ENODEV;
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} else if (!resp->range_start && !resp->range_num) {
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} else if (!resp->range_num && !resp->range_num_sec) {
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/* Neither of the two resource range is valid */
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ret = -ENODEV;
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} else {
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*range_start = resp->range_start;
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*range_num = resp->range_num;
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desc->start = resp->range_start;
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desc->num = resp->range_num;
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desc->start_sec = resp->range_start_sec;
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desc->num_sec = resp->range_num_sec;
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};
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fail:
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@ -1771,18 +1774,18 @@ fail:
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* @dev_id: TISCI device ID.
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* @subtype: Resource assignment subtype that is being requested
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* from the given device.
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* @range_start: Start index of the resource range
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* @range_num: Number of resources in the range
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* @desc: Pointer to ti_sci_resource_desc to be updated with the
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* resource range start index and number of resources
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*
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* Return: 0 if all went fine, else return appropriate error.
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*/
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static int ti_sci_cmd_get_resource_range(const struct ti_sci_handle *handle,
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u32 dev_id, u8 subtype,
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u16 *range_start, u16 *range_num)
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struct ti_sci_resource_desc *desc)
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{
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return ti_sci_get_resource_range(handle, dev_id, subtype,
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TI_SCI_IRQ_SECONDARY_HOST_INVALID,
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range_start, range_num);
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desc);
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}
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/**
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@ -1793,18 +1796,17 @@ static int ti_sci_cmd_get_resource_range(const struct ti_sci_handle *handle,
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* @subtype: Resource assignment subtype that is being requested
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* from the given device.
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* @s_host: Host processor ID to which the resources are allocated
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* @range_start: Start index of the resource range
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* @range_num: Number of resources in the range
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* @desc: Pointer to ti_sci_resource_desc to be updated with the
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* resource range start index and number of resources
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*
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* Return: 0 if all went fine, else return appropriate error.
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*/
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static
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int ti_sci_cmd_get_resource_range_from_shost(const struct ti_sci_handle *handle,
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u32 dev_id, u8 subtype, u8 s_host,
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u16 *range_start, u16 *range_num)
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struct ti_sci_resource_desc *desc)
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{
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return ti_sci_get_resource_range(handle, dev_id, subtype, s_host,
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range_start, range_num);
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return ti_sci_get_resource_range(handle, dev_id, subtype, s_host, desc);
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}
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/**
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@ -2047,28 +2049,17 @@ static int ti_sci_cmd_free_event_map(const struct ti_sci_handle *handle,
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}
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/**
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* ti_sci_cmd_ring_config() - configure RA ring
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* @handle: Pointer to TI SCI handle.
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* @valid_params: Bitfield defining validity of ring configuration
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* parameters
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* @nav_id: Device ID of Navigator Subsystem from which the ring is
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* allocated
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* @index: Ring index
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* @addr_lo: The ring base address lo 32 bits
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* @addr_hi: The ring base address hi 32 bits
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* @count: Number of ring elements
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* @mode: The mode of the ring
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* @size: The ring element size.
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* @order_id: Specifies the ring's bus order ID
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* ti_sci_cmd_rm_ring_cfg() - Configure a NAVSS ring
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* @handle: Pointer to TI SCI handle.
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* @params: Pointer to ti_sci_msg_rm_ring_cfg ring config structure
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*
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* Return: 0 if all went well, else returns appropriate error value.
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*
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* See @ti_sci_msg_rm_ring_cfg_req for more info.
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* See @ti_sci_msg_rm_ring_cfg and @ti_sci_msg_rm_ring_cfg_req for
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* more info.
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*/
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static int ti_sci_cmd_ring_config(const struct ti_sci_handle *handle,
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u32 valid_params, u16 nav_id, u16 index,
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u32 addr_lo, u32 addr_hi, u32 count,
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u8 mode, u8 size, u8 order_id)
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static int ti_sci_cmd_rm_ring_cfg(const struct ti_sci_handle *handle,
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const struct ti_sci_msg_rm_ring_cfg *params)
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{
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struct ti_sci_msg_rm_ring_cfg_req *req;
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struct ti_sci_msg_hdr *resp;
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@ -2092,15 +2083,17 @@ static int ti_sci_cmd_ring_config(const struct ti_sci_handle *handle,
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return ret;
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}
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req = (struct ti_sci_msg_rm_ring_cfg_req *)xfer->xfer_buf;
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req->valid_params = valid_params;
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req->nav_id = nav_id;
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req->index = index;
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req->addr_lo = addr_lo;
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req->addr_hi = addr_hi;
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req->count = count;
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req->mode = mode;
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req->size = size;
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req->order_id = order_id;
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req->valid_params = params->valid_params;
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req->nav_id = params->nav_id;
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req->index = params->index;
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req->addr_lo = params->addr_lo;
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req->addr_hi = params->addr_hi;
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req->count = params->count;
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req->mode = params->mode;
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req->size = params->size;
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req->order_id = params->order_id;
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req->virtid = params->virtid;
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req->asel = params->asel;
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ret = ti_sci_do_xfer(info, xfer);
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if (ret) {
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@ -2109,90 +2102,11 @@ static int ti_sci_cmd_ring_config(const struct ti_sci_handle *handle,
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}
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resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf;
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ret = ti_sci_is_response_ack(resp) ? 0 : -ENODEV;
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ret = ti_sci_is_response_ack(resp) ? 0 : -EINVAL;
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fail:
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ti_sci_put_one_xfer(&info->minfo, xfer);
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dev_dbg(dev, "RM_RA:config ring %u ret:%d\n", index, ret);
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return ret;
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}
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/**
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* ti_sci_cmd_ring_get_config() - get RA ring configuration
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* @handle: Pointer to TI SCI handle.
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* @nav_id: Device ID of Navigator Subsystem from which the ring is
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* allocated
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* @index: Ring index
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* @addr_lo: Returns ring's base address lo 32 bits
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* @addr_hi: Returns ring's base address hi 32 bits
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* @count: Returns number of ring elements
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* @mode: Returns mode of the ring
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* @size: Returns ring element size
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* @order_id: Returns ring's bus order ID
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*
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* Return: 0 if all went well, else returns appropriate error value.
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*
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* See @ti_sci_msg_rm_ring_get_cfg_req for more info.
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*/
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static int ti_sci_cmd_ring_get_config(const struct ti_sci_handle *handle,
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u32 nav_id, u32 index, u8 *mode,
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u32 *addr_lo, u32 *addr_hi,
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u32 *count, u8 *size, u8 *order_id)
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{
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struct ti_sci_msg_rm_ring_get_cfg_resp *resp;
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struct ti_sci_msg_rm_ring_get_cfg_req *req;
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struct ti_sci_xfer *xfer;
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struct ti_sci_info *info;
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struct device *dev;
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int ret = 0;
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if (IS_ERR_OR_NULL(handle))
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return -EINVAL;
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info = handle_to_ti_sci_info(handle);
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dev = info->dev;
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xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_RM_RING_GET_CFG,
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TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
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sizeof(*req), sizeof(*resp));
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if (IS_ERR(xfer)) {
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ret = PTR_ERR(xfer);
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dev_err(dev,
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"RM_RA:Message get config failed(%d)\n", ret);
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return ret;
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}
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req = (struct ti_sci_msg_rm_ring_get_cfg_req *)xfer->xfer_buf;
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req->nav_id = nav_id;
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req->index = index;
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ret = ti_sci_do_xfer(info, xfer);
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if (ret) {
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dev_err(dev, "RM_RA:Mbox get config send fail %d\n", ret);
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goto fail;
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}
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resp = (struct ti_sci_msg_rm_ring_get_cfg_resp *)xfer->xfer_buf;
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if (!ti_sci_is_response_ack(resp)) {
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ret = -ENODEV;
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} else {
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if (mode)
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*mode = resp->mode;
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if (addr_lo)
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*addr_lo = resp->addr_lo;
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if (addr_hi)
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*addr_hi = resp->addr_hi;
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if (count)
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*count = resp->count;
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if (size)
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*size = resp->size;
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if (order_id)
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*order_id = resp->order_id;
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};
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fail:
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ti_sci_put_one_xfer(&info->minfo, xfer);
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dev_dbg(dev, "RM_RA:get config ring %u ret:%d\n", index, ret);
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dev_dbg(dev, "RM_RA:config ring %u ret:%d\n", params->index, ret);
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return ret;
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}
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@ -2362,6 +2276,8 @@ static int ti_sci_cmd_rm_udmap_tx_ch_cfg(const struct ti_sci_handle *handle,
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req->fdepth = params->fdepth;
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req->tx_sched_priority = params->tx_sched_priority;
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req->tx_burst_size = params->tx_burst_size;
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req->tx_tdtype = params->tx_tdtype;
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req->extended_ch_type = params->extended_ch_type;
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ret = ti_sci_do_xfer(info, xfer);
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if (ret) {
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@ -2921,8 +2837,7 @@ static void ti_sci_setup_ops(struct ti_sci_info *info)
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iops->free_irq = ti_sci_cmd_free_irq;
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iops->free_event_map = ti_sci_cmd_free_event_map;
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rops->config = ti_sci_cmd_ring_config;
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rops->get_config = ti_sci_cmd_ring_get_config;
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rops->set_cfg = ti_sci_cmd_rm_ring_cfg;
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psilops->pair = ti_sci_cmd_rm_psil_pair;
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psilops->unpair = ti_sci_cmd_rm_psil_unpair;
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@ -3157,12 +3072,18 @@ u16 ti_sci_get_free_resource(struct ti_sci_resource *res)
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raw_spin_lock_irqsave(&res->lock, flags);
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for (set = 0; set < res->sets; set++) {
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free_bit = find_first_zero_bit(res->desc[set].res_map,
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res->desc[set].num);
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if (free_bit != res->desc[set].num) {
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set_bit(free_bit, res->desc[set].res_map);
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struct ti_sci_resource_desc *desc = &res->desc[set];
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int res_count = desc->num + desc->num_sec;
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free_bit = find_first_zero_bit(desc->res_map, res_count);
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if (free_bit != res_count) {
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set_bit(free_bit, desc->res_map);
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raw_spin_unlock_irqrestore(&res->lock, flags);
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return res->desc[set].start + free_bit;
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if (desc->num && free_bit < desc->num)
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return desc->start + free_bit;
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else
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return desc->start_sec + free_bit;
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}
|
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}
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raw_spin_unlock_irqrestore(&res->lock, flags);
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@ -3183,10 +3104,14 @@ void ti_sci_release_resource(struct ti_sci_resource *res, u16 id)
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|
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raw_spin_lock_irqsave(&res->lock, flags);
|
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for (set = 0; set < res->sets; set++) {
|
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if (res->desc[set].start <= id &&
|
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(res->desc[set].num + res->desc[set].start) > id)
|
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clear_bit(id - res->desc[set].start,
|
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res->desc[set].res_map);
|
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struct ti_sci_resource_desc *desc = &res->desc[set];
|
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|
||||
if (desc->num && desc->start <= id &&
|
||||
(desc->start + desc->num) > id)
|
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clear_bit(id - desc->start, desc->res_map);
|
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else if (desc->num_sec && desc->start_sec <= id &&
|
||||
(desc->start_sec + desc->num_sec) > id)
|
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clear_bit(id - desc->start_sec, desc->res_map);
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}
|
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raw_spin_unlock_irqrestore(&res->lock, flags);
|
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}
|
||||
@ -3203,7 +3128,7 @@ u32 ti_sci_get_num_resources(struct ti_sci_resource *res)
|
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u32 set, count = 0;
|
||||
|
||||
for (set = 0; set < res->sets; set++)
|
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count += res->desc[set].num;
|
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count += res->desc[set].num + res->desc[set].num_sec;
|
||||
|
||||
return count;
|
||||
}
|
||||
@ -3227,7 +3152,7 @@ devm_ti_sci_get_resource_sets(const struct ti_sci_handle *handle,
|
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{
|
||||
struct ti_sci_resource *res;
|
||||
bool valid_set = false;
|
||||
int i, ret;
|
||||
int i, ret, res_count;
|
||||
|
||||
res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
|
||||
if (!res)
|
||||
@ -3242,23 +3167,23 @@ devm_ti_sci_get_resource_sets(const struct ti_sci_handle *handle,
|
||||
for (i = 0; i < res->sets; i++) {
|
||||
ret = handle->ops.rm_core_ops.get_range(handle, dev_id,
|
||||
sub_types[i],
|
||||
&res->desc[i].start,
|
||||
&res->desc[i].num);
|
||||
&res->desc[i]);
|
||||
if (ret) {
|
||||
dev_dbg(dev, "dev = %d subtype %d not allocated for this host\n",
|
||||
dev_id, sub_types[i]);
|
||||
res->desc[i].start = 0;
|
||||
res->desc[i].num = 0;
|
||||
memset(&res->desc[i], 0, sizeof(res->desc[i]));
|
||||
continue;
|
||||
}
|
||||
|
||||
dev_dbg(dev, "dev = %d, subtype = %d, start = %d, num = %d\n",
|
||||
dev_dbg(dev, "dev/sub_type: %d/%d, start/num: %d/%d | %d/%d\n",
|
||||
dev_id, sub_types[i], res->desc[i].start,
|
||||
res->desc[i].num);
|
||||
res->desc[i].num, res->desc[i].start_sec,
|
||||
res->desc[i].num_sec);
|
||||
|
||||
valid_set = true;
|
||||
res_count = res->desc[i].num + res->desc[i].num_sec;
|
||||
res->desc[i].res_map =
|
||||
devm_kzalloc(dev, BITS_TO_LONGS(res->desc[i].num) *
|
||||
devm_kzalloc(dev, BITS_TO_LONGS(res_count) *
|
||||
sizeof(*res->desc[i].res_map), GFP_KERNEL);
|
||||
if (!res->desc[i].res_map)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
@ -49,7 +49,6 @@
|
||||
#define TI_SCI_MSG_RM_RING_RECONFIG 0x1102
|
||||
#define TI_SCI_MSG_RM_RING_RESET 0x1103
|
||||
#define TI_SCI_MSG_RM_RING_CFG 0x1110
|
||||
#define TI_SCI_MSG_RM_RING_GET_CFG 0x1111
|
||||
|
||||
/* PSI-L requests */
|
||||
#define TI_SCI_MSG_RM_PSIL_PAIR 0x1280
|
||||
@ -574,8 +573,10 @@ struct ti_sci_msg_req_get_resource_range {
|
||||
/**
|
||||
* struct ti_sci_msg_resp_get_resource_range - Response to resource get range.
|
||||
* @hdr: Generic Header
|
||||
* @range_start: Start index of the resource range.
|
||||
* @range_num: Number of resources in the range.
|
||||
* @range_start: Start index of the first resource range.
|
||||
* @range_num: Number of resources in the first range.
|
||||
* @range_start_sec: Start index of the second resource range.
|
||||
* @range_num_sec: Number of resources in the second range.
|
||||
*
|
||||
* Response to request TI_SCI_MSG_GET_RESOURCE_RANGE.
|
||||
*/
|
||||
@ -583,6 +584,8 @@ struct ti_sci_msg_resp_get_resource_range {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
u16 range_start;
|
||||
u16 range_num;
|
||||
u16 range_start_sec;
|
||||
u16 range_num_sec;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
@ -656,6 +659,8 @@ struct ti_sci_msg_req_manage_irq {
|
||||
* 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode
|
||||
* 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size
|
||||
* 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id
|
||||
* 6 - Valid bit for @tisci_msg_rm_ring_cfg_req virtid
|
||||
* 7 - Valid bit for @tisci_msg_rm_ring_cfg_req ASEL
|
||||
* @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
|
||||
* @index: ring index to be configured.
|
||||
* @addr_lo: 32 LSBs of ring base address to be programmed into the ring's
|
||||
@ -669,6 +674,9 @@ struct ti_sci_msg_req_manage_irq {
|
||||
* the formula (log2(size_bytes) - 2), where size_bytes cannot be
|
||||
* greater than 256.
|
||||
* @order_id: Specifies the ring's bus order ID.
|
||||
* @virtid: Ring virt ID value
|
||||
* @asel: Ring ASEL (address select) value to be set into the ASEL field of the
|
||||
* ring's RING_BA_HI register.
|
||||
*/
|
||||
struct ti_sci_msg_rm_ring_cfg_req {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
@ -681,49 +689,8 @@ struct ti_sci_msg_rm_ring_cfg_req {
|
||||
u8 mode;
|
||||
u8 size;
|
||||
u8 order_id;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_rm_ring_get_cfg_req - Get RA ring's configuration
|
||||
*
|
||||
* Gets the configuration of the non-real-time register fields of a ring. The
|
||||
* host, or a supervisor of the host, who owns the ring must be the requesting
|
||||
* host. The values of the non-real-time registers are returned in
|
||||
* @ti_sci_msg_rm_ring_get_cfg_resp.
|
||||
*
|
||||
* @hdr: Generic Header
|
||||
* @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
|
||||
* @index: ring index.
|
||||
*/
|
||||
struct ti_sci_msg_rm_ring_get_cfg_req {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
u16 nav_id;
|
||||
u16 index;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_rm_ring_get_cfg_resp - Ring get configuration response
|
||||
*
|
||||
* Response received by host processor after RM has handled
|
||||
* @ti_sci_msg_rm_ring_get_cfg_req. The response contains the ring's
|
||||
* non-real-time register values.
|
||||
*
|
||||
* @hdr: Generic Header
|
||||
* @addr_lo: Ring 32 LSBs of base address
|
||||
* @addr_hi: Ring 16 MSBs of base address.
|
||||
* @count: Ring number of elements.
|
||||
* @mode: Ring mode.
|
||||
* @size: encoded Ring element size
|
||||
* @order_id: ing order ID.
|
||||
*/
|
||||
struct ti_sci_msg_rm_ring_get_cfg_resp {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
u32 addr_lo;
|
||||
u32 addr_hi;
|
||||
u32 count;
|
||||
u8 mode;
|
||||
u8 size;
|
||||
u8 order_id;
|
||||
u16 virtid;
|
||||
u8 asel;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
@ -910,6 +877,8 @@ struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg {
|
||||
* 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count
|
||||
* 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth
|
||||
* 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size
|
||||
* 15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype
|
||||
* 16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type
|
||||
*
|
||||
* @nav_id: SoC device ID of Navigator Subsystem where tx channel is located
|
||||
*
|
||||
@ -973,6 +942,15 @@ struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg {
|
||||
*
|
||||
* @tx_burst_size: UDMAP transmit channel burst size configuration to be
|
||||
* programmed into the tx_burst_size field of the TCHAN_TCFG register.
|
||||
*
|
||||
* @tx_tdtype: UDMAP transmit channel teardown type configuration to be
|
||||
* programmed into the tdtype field of the TCHAN_TCFG register:
|
||||
* 0 - Return immediately
|
||||
* 1 - Wait for completion message from remote peer
|
||||
*
|
||||
* @extended_ch_type: Valid for BCDMA.
|
||||
* 0 - the channel is split tx channel (tchan)
|
||||
* 1 - the channel is block copy channel (bchan)
|
||||
*/
|
||||
struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
@ -994,6 +972,8 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
|
||||
u16 fdepth;
|
||||
u8 tx_sched_priority;
|
||||
u8 tx_burst_size;
|
||||
u8 tx_tdtype;
|
||||
u8 extended_ch_type;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
|
||||
@ -1,22 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
# 64-bit ARM SoCs from TI
|
||||
if ARM64
|
||||
|
||||
if ARCH_K3
|
||||
|
||||
config ARCH_K3_AM6_SOC
|
||||
bool "K3 AM6 SoC"
|
||||
help
|
||||
Enable support for TI's AM6 SoC Family support
|
||||
|
||||
config ARCH_K3_J721E_SOC
|
||||
bool "K3 J721E SoC"
|
||||
help
|
||||
Enable support for TI's J721E SoC Family support
|
||||
|
||||
endif
|
||||
|
||||
endif
|
||||
|
||||
#
|
||||
# TI SOC drivers
|
||||
|
||||
@ -137,10 +137,12 @@ struct k3_ring_state {
|
||||
* @elm_size: Size of the ring element
|
||||
* @mode: Ring mode
|
||||
* @flags: flags
|
||||
* @state: Ring state
|
||||
* @ring_id: Ring Id
|
||||
* @parent: Pointer on struct @k3_ringacc
|
||||
* @use_count: Use count for shared rings
|
||||
* @proxy_id: RA Ring Proxy Id (only if @K3_RINGACC_RING_USE_PROXY)
|
||||
* @dma_dev: device to be used for DMA API (allocation, mapping)
|
||||
*/
|
||||
struct k3_ring {
|
||||
struct k3_ring_rt_regs __iomem *rt;
|
||||
@ -160,6 +162,7 @@ struct k3_ring {
|
||||
struct k3_ringacc *parent;
|
||||
u32 use_count;
|
||||
int proxy_id;
|
||||
struct device *dma_dev;
|
||||
};
|
||||
|
||||
struct k3_ringacc_ops {
|
||||
@ -365,20 +368,16 @@ EXPORT_SYMBOL_GPL(k3_ringacc_request_rings_pair);
|
||||
|
||||
static void k3_ringacc_ring_reset_sci(struct k3_ring *ring)
|
||||
{
|
||||
struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
|
||||
struct k3_ringacc *ringacc = ring->parent;
|
||||
int ret;
|
||||
|
||||
ret = ringacc->tisci_ring_ops->config(
|
||||
ringacc->tisci,
|
||||
TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID,
|
||||
ringacc->tisci_dev_id,
|
||||
ring->ring_id,
|
||||
0,
|
||||
0,
|
||||
ring->size,
|
||||
0,
|
||||
0,
|
||||
0);
|
||||
ring_cfg.nav_id = ringacc->tisci_dev_id;
|
||||
ring_cfg.index = ring->ring_id;
|
||||
ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID;
|
||||
ring_cfg.count = ring->size;
|
||||
|
||||
ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
|
||||
if (ret)
|
||||
dev_err(ringacc->dev, "TISCI reset ring fail (%d) ring_idx %d\n",
|
||||
ret, ring->ring_id);
|
||||
@ -398,20 +397,16 @@ EXPORT_SYMBOL_GPL(k3_ringacc_ring_reset);
|
||||
static void k3_ringacc_ring_reconfig_qmode_sci(struct k3_ring *ring,
|
||||
enum k3_ring_mode mode)
|
||||
{
|
||||
struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
|
||||
struct k3_ringacc *ringacc = ring->parent;
|
||||
int ret;
|
||||
|
||||
ret = ringacc->tisci_ring_ops->config(
|
||||
ringacc->tisci,
|
||||
TI_SCI_MSG_VALUE_RM_RING_MODE_VALID,
|
||||
ringacc->tisci_dev_id,
|
||||
ring->ring_id,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
mode,
|
||||
0,
|
||||
0);
|
||||
ring_cfg.nav_id = ringacc->tisci_dev_id;
|
||||
ring_cfg.index = ring->ring_id;
|
||||
ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_RING_MODE_VALID;
|
||||
ring_cfg.mode = mode;
|
||||
|
||||
ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
|
||||
if (ret)
|
||||
dev_err(ringacc->dev, "TISCI reconf qmode fail (%d) ring_idx %d\n",
|
||||
ret, ring->ring_id);
|
||||
@ -478,20 +473,15 @@ EXPORT_SYMBOL_GPL(k3_ringacc_ring_reset_dma);
|
||||
|
||||
static void k3_ringacc_ring_free_sci(struct k3_ring *ring)
|
||||
{
|
||||
struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
|
||||
struct k3_ringacc *ringacc = ring->parent;
|
||||
int ret;
|
||||
|
||||
ret = ringacc->tisci_ring_ops->config(
|
||||
ringacc->tisci,
|
||||
TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER,
|
||||
ringacc->tisci_dev_id,
|
||||
ring->ring_id,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0);
|
||||
ring_cfg.nav_id = ringacc->tisci_dev_id;
|
||||
ring_cfg.index = ring->ring_id;
|
||||
ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER;
|
||||
|
||||
ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
|
||||
if (ret)
|
||||
dev_err(ringacc->dev, "TISCI ring free fail (%d) ring_idx %d\n",
|
||||
ret, ring->ring_id);
|
||||
@ -521,11 +511,12 @@ int k3_ringacc_ring_free(struct k3_ring *ring)
|
||||
|
||||
k3_ringacc_ring_free_sci(ring);
|
||||
|
||||
dma_free_coherent(ringacc->dev,
|
||||
dma_free_coherent(ring->dma_dev,
|
||||
ring->size * (4 << ring->elm_size),
|
||||
ring->ring_mem_virt, ring->ring_mem_dma);
|
||||
ring->flags = 0;
|
||||
ring->ops = NULL;
|
||||
ring->dma_dev = NULL;
|
||||
if (ring->proxy_id != K3_RINGACC_PROXY_NOT_USED) {
|
||||
clear_bit(ring->proxy_id, ringacc->proxy_inuse);
|
||||
ring->proxy = NULL;
|
||||
@ -575,28 +566,26 @@ EXPORT_SYMBOL_GPL(k3_ringacc_get_ring_irq_num);
|
||||
|
||||
static int k3_ringacc_ring_cfg_sci(struct k3_ring *ring)
|
||||
{
|
||||
struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
|
||||
struct k3_ringacc *ringacc = ring->parent;
|
||||
u32 ring_idx;
|
||||
int ret;
|
||||
|
||||
if (!ringacc->tisci)
|
||||
return -EINVAL;
|
||||
|
||||
ring_idx = ring->ring_id;
|
||||
ret = ringacc->tisci_ring_ops->config(
|
||||
ringacc->tisci,
|
||||
TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER,
|
||||
ringacc->tisci_dev_id,
|
||||
ring_idx,
|
||||
lower_32_bits(ring->ring_mem_dma),
|
||||
upper_32_bits(ring->ring_mem_dma),
|
||||
ring->size,
|
||||
ring->mode,
|
||||
ring->elm_size,
|
||||
0);
|
||||
ring_cfg.nav_id = ringacc->tisci_dev_id;
|
||||
ring_cfg.index = ring->ring_id;
|
||||
ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER;
|
||||
ring_cfg.addr_lo = lower_32_bits(ring->ring_mem_dma);
|
||||
ring_cfg.addr_hi = upper_32_bits(ring->ring_mem_dma);
|
||||
ring_cfg.count = ring->size;
|
||||
ring_cfg.mode = ring->mode;
|
||||
ring_cfg.size = ring->elm_size;
|
||||
|
||||
ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
|
||||
if (ret)
|
||||
dev_err(ringacc->dev, "TISCI config ring fail (%d) ring_idx %d\n",
|
||||
ret, ring_idx);
|
||||
ret, ring->ring_id);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -648,8 +637,12 @@ int k3_ringacc_ring_cfg(struct k3_ring *ring, struct k3_ring_cfg *cfg)
|
||||
switch (ring->mode) {
|
||||
case K3_RINGACC_RING_MODE_RING:
|
||||
ring->ops = &k3_ring_mode_ring_ops;
|
||||
ring->dma_dev = cfg->dma_dev;
|
||||
if (!ring->dma_dev)
|
||||
ring->dma_dev = ringacc->dev;
|
||||
break;
|
||||
case K3_RINGACC_RING_MODE_MESSAGE:
|
||||
ring->dma_dev = ringacc->dev;
|
||||
if (ring->proxy)
|
||||
ring->ops = &k3_ring_mode_proxy_ops;
|
||||
else
|
||||
@ -661,9 +654,9 @@ int k3_ringacc_ring_cfg(struct k3_ring *ring, struct k3_ring_cfg *cfg)
|
||||
goto err_free_proxy;
|
||||
}
|
||||
|
||||
ring->ring_mem_virt = dma_alloc_coherent(ringacc->dev,
|
||||
ring->size * (4 << ring->elm_size),
|
||||
&ring->ring_mem_dma, GFP_KERNEL);
|
||||
ring->ring_mem_virt = dma_alloc_coherent(ring->dma_dev,
|
||||
ring->size * (4 << ring->elm_size),
|
||||
&ring->ring_mem_dma, GFP_KERNEL);
|
||||
if (!ring->ring_mem_virt) {
|
||||
dev_err(ringacc->dev, "Failed to alloc ring mem\n");
|
||||
ret = -ENOMEM;
|
||||
@ -684,12 +677,13 @@ int k3_ringacc_ring_cfg(struct k3_ring *ring, struct k3_ring_cfg *cfg)
|
||||
return 0;
|
||||
|
||||
err_free_mem:
|
||||
dma_free_coherent(ringacc->dev,
|
||||
dma_free_coherent(ring->dma_dev,
|
||||
ring->size * (4 << ring->elm_size),
|
||||
ring->ring_mem_virt,
|
||||
ring->ring_mem_dma);
|
||||
err_free_ops:
|
||||
ring->ops = NULL;
|
||||
ring->dma_dev = NULL;
|
||||
err_free_proxy:
|
||||
ring->proxy = NULL;
|
||||
return ret;
|
||||
|
||||
@ -40,6 +40,7 @@ static const struct k3_soc_id {
|
||||
{ 0xBB5A, "AM65X" },
|
||||
{ 0xBB64, "J721E" },
|
||||
{ 0xBB6D, "J7200" },
|
||||
{ 0xBB38, "AM64X" }
|
||||
};
|
||||
|
||||
static int
|
||||
|
||||
@ -500,7 +500,7 @@ EXPORT_SYMBOL_GPL(knav_dma_open_channel);
|
||||
/**
|
||||
* knav_dma_close_channel() - Destroy a dma channel
|
||||
*
|
||||
* channel: dma channel handle
|
||||
* @channel: dma channel handle
|
||||
*
|
||||
*/
|
||||
void knav_dma_close_channel(void *channel)
|
||||
@ -749,8 +749,9 @@ static int knav_dma_probe(struct platform_device *pdev)
|
||||
pm_runtime_enable(kdev->dev);
|
||||
ret = pm_runtime_get_sync(kdev->dev);
|
||||
if (ret < 0) {
|
||||
pm_runtime_put_noidle(kdev->dev);
|
||||
dev_err(kdev->dev, "unable to enable pktdma, err %d\n", ret);
|
||||
return ret;
|
||||
goto err_pm_disable;
|
||||
}
|
||||
|
||||
/* Initialise all packet dmas */
|
||||
@ -764,7 +765,8 @@ static int knav_dma_probe(struct platform_device *pdev)
|
||||
|
||||
if (list_empty(&kdev->list)) {
|
||||
dev_err(dev, "no valid dma instance\n");
|
||||
return -ENODEV;
|
||||
ret = -ENODEV;
|
||||
goto err_put_sync;
|
||||
}
|
||||
|
||||
debugfs_create_file("knav_dma", S_IFREG | S_IRUGO, NULL, NULL,
|
||||
@ -772,6 +774,13 @@ static int knav_dma_probe(struct platform_device *pdev)
|
||||
|
||||
device_ready = true;
|
||||
return ret;
|
||||
|
||||
err_put_sync:
|
||||
pm_runtime_put_sync(kdev->dev);
|
||||
err_pm_disable:
|
||||
pm_runtime_disable(kdev->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int knav_dma_remove(struct platform_device *pdev)
|
||||
|
||||
@ -79,7 +79,7 @@ EXPORT_SYMBOL_GPL(knav_qmss_device_ready);
|
||||
/**
|
||||
* knav_queue_notify: qmss queue notfier call
|
||||
*
|
||||
* @inst: qmss queue instance like accumulator
|
||||
* @inst: - qmss queue instance like accumulator
|
||||
*/
|
||||
void knav_queue_notify(struct knav_queue_inst *inst)
|
||||
{
|
||||
@ -511,10 +511,10 @@ static int knav_queue_flush(struct knav_queue *qh)
|
||||
|
||||
/**
|
||||
* knav_queue_open() - open a hardware queue
|
||||
* @name - name to give the queue handle
|
||||
* @id - desired queue number if any or specifes the type
|
||||
* @name: - name to give the queue handle
|
||||
* @id: - desired queue number if any or specifes the type
|
||||
* of queue
|
||||
* @flags - the following flags are applicable to queues:
|
||||
* @flags: - the following flags are applicable to queues:
|
||||
* KNAV_QUEUE_SHARED - allow the queue to be shared. Queues are
|
||||
* exclusive by default.
|
||||
* Subsequent attempts to open a shared queue should
|
||||
@ -545,7 +545,7 @@ EXPORT_SYMBOL_GPL(knav_queue_open);
|
||||
|
||||
/**
|
||||
* knav_queue_close() - close a hardware queue handle
|
||||
* @qh - handle to close
|
||||
* @qhandle: - handle to close
|
||||
*/
|
||||
void knav_queue_close(void *qhandle)
|
||||
{
|
||||
@ -572,9 +572,9 @@ EXPORT_SYMBOL_GPL(knav_queue_close);
|
||||
|
||||
/**
|
||||
* knav_queue_device_control() - Perform control operations on a queue
|
||||
* @qh - queue handle
|
||||
* @cmd - control commands
|
||||
* @arg - command argument
|
||||
* @qhandle: - queue handle
|
||||
* @cmd: - control commands
|
||||
* @arg: - command argument
|
||||
*
|
||||
* Returns 0 on success, errno otherwise.
|
||||
*/
|
||||
@ -623,10 +623,10 @@ EXPORT_SYMBOL_GPL(knav_queue_device_control);
|
||||
|
||||
/**
|
||||
* knav_queue_push() - push data (or descriptor) to the tail of a queue
|
||||
* @qh - hardware queue handle
|
||||
* @data - data to push
|
||||
* @size - size of data to push
|
||||
* @flags - can be used to pass additional information
|
||||
* @qhandle: - hardware queue handle
|
||||
* @dma: - DMA data to push
|
||||
* @size: - size of data to push
|
||||
* @flags: - can be used to pass additional information
|
||||
*
|
||||
* Returns 0 on success, errno otherwise.
|
||||
*/
|
||||
@ -646,8 +646,8 @@ EXPORT_SYMBOL_GPL(knav_queue_push);
|
||||
|
||||
/**
|
||||
* knav_queue_pop() - pop data (or descriptor) from the head of a queue
|
||||
* @qh - hardware queue handle
|
||||
* @size - (optional) size of the data pop'ed.
|
||||
* @qhandle: - hardware queue handle
|
||||
* @size: - (optional) size of the data pop'ed.
|
||||
*
|
||||
* Returns a DMA address on success, 0 on failure.
|
||||
*/
|
||||
@ -746,9 +746,9 @@ EXPORT_SYMBOL_GPL(knav_pool_desc_dma_to_virt);
|
||||
|
||||
/**
|
||||
* knav_pool_create() - Create a pool of descriptors
|
||||
* @name - name to give the pool handle
|
||||
* @num_desc - numbers of descriptors in the pool
|
||||
* @region_id - QMSS region id from which the descriptors are to be
|
||||
* @name: - name to give the pool handle
|
||||
* @num_desc: - numbers of descriptors in the pool
|
||||
* @region_id: - QMSS region id from which the descriptors are to be
|
||||
* allocated.
|
||||
*
|
||||
* Returns a pool handle on success.
|
||||
@ -856,7 +856,7 @@ EXPORT_SYMBOL_GPL(knav_pool_create);
|
||||
|
||||
/**
|
||||
* knav_pool_destroy() - Free a pool of descriptors
|
||||
* @pool - pool handle
|
||||
* @ph: - pool handle
|
||||
*/
|
||||
void knav_pool_destroy(void *ph)
|
||||
{
|
||||
@ -884,7 +884,7 @@ EXPORT_SYMBOL_GPL(knav_pool_destroy);
|
||||
|
||||
/**
|
||||
* knav_pool_desc_get() - Get a descriptor from the pool
|
||||
* @pool - pool handle
|
||||
* @ph: - pool handle
|
||||
*
|
||||
* Returns descriptor from the pool.
|
||||
*/
|
||||
@ -905,7 +905,8 @@ EXPORT_SYMBOL_GPL(knav_pool_desc_get);
|
||||
|
||||
/**
|
||||
* knav_pool_desc_put() - return a descriptor to the pool
|
||||
* @pool - pool handle
|
||||
* @ph: - pool handle
|
||||
* @desc: - virtual address
|
||||
*/
|
||||
void knav_pool_desc_put(void *ph, void *desc)
|
||||
{
|
||||
@ -918,11 +919,11 @@ EXPORT_SYMBOL_GPL(knav_pool_desc_put);
|
||||
|
||||
/**
|
||||
* knav_pool_desc_map() - Map descriptor for DMA transfer
|
||||
* @pool - pool handle
|
||||
* @desc - address of descriptor to map
|
||||
* @size - size of descriptor to map
|
||||
* @dma - DMA address return pointer
|
||||
* @dma_sz - adjusted return pointer
|
||||
* @ph: - pool handle
|
||||
* @desc: - address of descriptor to map
|
||||
* @size: - size of descriptor to map
|
||||
* @dma: - DMA address return pointer
|
||||
* @dma_sz: - adjusted return pointer
|
||||
*
|
||||
* Returns 0 on success, errno otherwise.
|
||||
*/
|
||||
@ -945,9 +946,9 @@ EXPORT_SYMBOL_GPL(knav_pool_desc_map);
|
||||
|
||||
/**
|
||||
* knav_pool_desc_unmap() - Unmap descriptor after DMA transfer
|
||||
* @pool - pool handle
|
||||
* @dma - DMA address of descriptor to unmap
|
||||
* @dma_sz - size of descriptor to unmap
|
||||
* @ph: - pool handle
|
||||
* @dma: - DMA address of descriptor to unmap
|
||||
* @dma_sz: - size of descriptor to unmap
|
||||
*
|
||||
* Returns descriptor address on success, Use IS_ERR_OR_NULL() to identify
|
||||
* error values on return.
|
||||
@ -968,7 +969,7 @@ EXPORT_SYMBOL_GPL(knav_pool_desc_unmap);
|
||||
|
||||
/**
|
||||
* knav_pool_count() - Get the number of descriptors in pool.
|
||||
* @pool - pool handle
|
||||
* @ph: - pool handle
|
||||
* Returns number of elements in the pool.
|
||||
*/
|
||||
int knav_pool_count(void *ph)
|
||||
@ -1307,12 +1308,11 @@ static int knav_setup_queue_pools(struct knav_device *kdev,
|
||||
struct device_node *queue_pools)
|
||||
{
|
||||
struct device_node *type, *range;
|
||||
int ret;
|
||||
|
||||
for_each_child_of_node(queue_pools, type) {
|
||||
for_each_child_of_node(type, range) {
|
||||
ret = knav_setup_queue_range(kdev, range);
|
||||
/* return value ignored, we init the rest... */
|
||||
knav_setup_queue_range(kdev, range);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1784,6 +1784,7 @@ static int knav_queue_probe(struct platform_device *pdev)
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
ret = pm_runtime_get_sync(&pdev->dev);
|
||||
if (ret < 0) {
|
||||
pm_runtime_put_noidle(&pdev->dev);
|
||||
dev_err(dev, "Failed to enable QMSS\n");
|
||||
return ret;
|
||||
}
|
||||
@ -1851,9 +1852,10 @@ static int knav_queue_probe(struct platform_device *pdev)
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
regions = of_get_child_by_name(node, "descriptor-regions");
|
||||
regions = of_get_child_by_name(node, "descriptor-regions");
|
||||
if (!regions) {
|
||||
dev_err(dev, "descriptor-regions not specified\n");
|
||||
ret = -ENODEV;
|
||||
goto err;
|
||||
}
|
||||
ret = knav_queue_setup_regions(kdev, regions);
|
||||
|
||||
@ -136,13 +136,11 @@ static int am33xx_push_sram_idle(void)
|
||||
|
||||
static int am33xx_do_sram_idle(u32 wfi_flags)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (!m3_ipc || !pm_ops)
|
||||
return 0;
|
||||
|
||||
if (wfi_flags & WFI_FLAG_WAKE_M3)
|
||||
ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_IDLE);
|
||||
m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_IDLE);
|
||||
|
||||
return pm_ops->cpu_suspend(am33xx_do_wfi_sram, wfi_flags);
|
||||
}
|
||||
|
||||
@ -126,8 +126,6 @@ static int pruss_clk_init(struct pruss *pruss, struct device_node *cfg_node)
|
||||
int ret = 0;
|
||||
|
||||
data = of_device_get_match_data(dev);
|
||||
if (IS_ERR(data))
|
||||
return -ENODEV;
|
||||
|
||||
clks_np = of_get_child_by_name(cfg_node, "clocks");
|
||||
if (!clks_np) {
|
||||
@ -175,10 +173,6 @@ static int pruss_probe(struct platform_device *pdev)
|
||||
const char *mem_names[PRUSS_MEM_MAX] = { "dram0", "dram1", "shrdram2" };
|
||||
|
||||
data = of_device_get_match_data(&pdev->dev);
|
||||
if (IS_ERR(data)) {
|
||||
dev_err(dev, "missing private data\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
|
||||
if (ret) {
|
||||
|
||||
@ -89,6 +89,18 @@ static int ti_sci_inta_msi_alloc_descs(struct device *dev,
|
||||
list_add_tail(&msi_desc->list, dev_to_msi_list(dev));
|
||||
count++;
|
||||
}
|
||||
for (i = 0; i < res->desc[set].num_sec; i++) {
|
||||
msi_desc = alloc_msi_entry(dev, 1, NULL);
|
||||
if (!msi_desc) {
|
||||
ti_sci_inta_msi_free_descs(dev);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
msi_desc->inta.dev_index = res->desc[set].start_sec + i;
|
||||
INIT_LIST_HEAD(&msi_desc->list);
|
||||
list_add_tail(&msi_desc->list, dev_to_msi_list(dev));
|
||||
count++;
|
||||
}
|
||||
}
|
||||
|
||||
return count;
|
||||
|
||||
@ -218,6 +218,7 @@ static int wkup_m3_is_available(struct wkup_m3_ipc *m3_ipc)
|
||||
/* Public functions */
|
||||
/**
|
||||
* wkup_m3_set_mem_type - Pass wkup_m3 which type of memory is in use
|
||||
* @m3_ipc: Pointer to wkup_m3_ipc context
|
||||
* @mem_type: memory type value read directly from emif
|
||||
*
|
||||
* wkup_m3 must know what memory type is in use to properly suspend
|
||||
@ -230,6 +231,7 @@ static void wkup_m3_set_mem_type(struct wkup_m3_ipc *m3_ipc, int mem_type)
|
||||
|
||||
/**
|
||||
* wkup_m3_set_resume_address - Pass wkup_m3 resume address
|
||||
* @m3_ipc: Pointer to wkup_m3_ipc context
|
||||
* @addr: Physical address from which resume code should execute
|
||||
*/
|
||||
static void wkup_m3_set_resume_address(struct wkup_m3_ipc *m3_ipc, void *addr)
|
||||
@ -239,6 +241,7 @@ static void wkup_m3_set_resume_address(struct wkup_m3_ipc *m3_ipc, void *addr)
|
||||
|
||||
/**
|
||||
* wkup_m3_request_pm_status - Retrieve wkup_m3 status code after suspend
|
||||
* @m3_ipc: Pointer to wkup_m3_ipc context
|
||||
*
|
||||
* Returns code representing the status of a low power mode transition.
|
||||
* 0 - Successful transition
|
||||
@ -260,6 +263,7 @@ static int wkup_m3_request_pm_status(struct wkup_m3_ipc *m3_ipc)
|
||||
/**
|
||||
* wkup_m3_prepare_low_power - Request preparation for transition to
|
||||
* low power state
|
||||
* @m3_ipc: Pointer to wkup_m3_ipc context
|
||||
* @state: A kernel suspend state to enter, either MEM or STANDBY
|
||||
*
|
||||
* Returns 0 if preparation was successful, otherwise returns error code
|
||||
@ -315,6 +319,7 @@ static int wkup_m3_prepare_low_power(struct wkup_m3_ipc *m3_ipc, int state)
|
||||
|
||||
/**
|
||||
* wkup_m3_finish_low_power - Return m3 to reset state
|
||||
* @m3_ipc: Pointer to wkup_m3_ipc context
|
||||
*
|
||||
* Returns 0 if reset was successful, otherwise returns error code
|
||||
*/
|
||||
@ -362,8 +367,7 @@ static const char *wkup_m3_request_wake_src(struct wkup_m3_ipc *m3_ipc)
|
||||
|
||||
/**
|
||||
* wkup_m3_set_rtc_only - Set the rtc_only flag
|
||||
* @wkup_m3_wakeup: struct wkup_m3_wakeup_src * gets assigned the
|
||||
* wakeup src value
|
||||
* @m3_ipc: Pointer to wkup_m3_ipc context
|
||||
*/
|
||||
static void wkup_m3_set_rtc_only(struct wkup_m3_ipc *m3_ipc)
|
||||
{
|
||||
|
||||
@ -67,6 +67,9 @@ struct k3_ring;
|
||||
* few times. It's usable when the same ring is used as Free Host PD ring
|
||||
* for different flows, for example.
|
||||
* Note: Locking should be done by consumer if required
|
||||
* @dma_dev: Master device which is using and accessing to the ring
|
||||
* memory when the mode is K3_RINGACC_RING_MODE_RING. Memory allocations
|
||||
* should be done using this device.
|
||||
*/
|
||||
struct k3_ring_cfg {
|
||||
u32 size;
|
||||
@ -74,6 +77,8 @@ struct k3_ring_cfg {
|
||||
enum k3_ring_mode mode;
|
||||
#define K3_RINGACC_RING_SHARED BIT(1)
|
||||
u32 flags;
|
||||
|
||||
struct device *dma_dev;
|
||||
};
|
||||
|
||||
#define K3_RINGACC_RING_ID_ANY (-1)
|
||||
|
||||
@ -195,6 +195,22 @@ struct ti_sci_clk_ops {
|
||||
u64 *current_freq);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ti_sci_resource_desc - Description of TI SCI resource instance range.
|
||||
* @start: Start index of the first resource range.
|
||||
* @num: Number of resources in the first range.
|
||||
* @start_sec: Start index of the second resource range.
|
||||
* @num_sec: Number of resources in the second range.
|
||||
* @res_map: Bitmap to manage the allocation of these resources.
|
||||
*/
|
||||
struct ti_sci_resource_desc {
|
||||
u16 start;
|
||||
u16 num;
|
||||
u16 start_sec;
|
||||
u16 num_sec;
|
||||
unsigned long *res_map;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ti_sci_rm_core_ops - Resource management core operations
|
||||
* @get_range: Get a range of resources belonging to ti sci host.
|
||||
@ -209,15 +225,15 @@ struct ti_sci_clk_ops {
|
||||
* - dev_id: TISCI device ID.
|
||||
* - subtype: Resource assignment subtype that is being requested
|
||||
* from the given device.
|
||||
* - range_start: Start index of the resource range
|
||||
* - range_end: Number of resources in the range
|
||||
* - desc: Pointer to ti_sci_resource_desc to be updated with the resource
|
||||
* range start index and number of resources
|
||||
*/
|
||||
struct ti_sci_rm_core_ops {
|
||||
int (*get_range)(const struct ti_sci_handle *handle, u32 dev_id,
|
||||
u8 subtype, u16 *range_start, u16 *range_num);
|
||||
u8 subtype, struct ti_sci_resource_desc *desc);
|
||||
int (*get_range_from_shost)(const struct ti_sci_handle *handle,
|
||||
u32 dev_id, u8 subtype, u8 s_host,
|
||||
u16 *range_start, u16 *range_num);
|
||||
struct ti_sci_resource_desc *desc);
|
||||
};
|
||||
|
||||
#define TI_SCI_RESASG_SUBTYPE_IR_OUTPUT 0
|
||||
@ -259,30 +275,46 @@ struct ti_sci_rm_irq_ops {
|
||||
#define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID BIT(4)
|
||||
/* RA config.order_id parameter is valid for RM ring configure TISCI message */
|
||||
#define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5)
|
||||
/* RA config.virtid parameter is valid for RM ring configure TISCI message */
|
||||
#define TI_SCI_MSG_VALUE_RM_RING_VIRTID_VALID BIT(6)
|
||||
/* RA config.asel parameter is valid for RM ring configure TISCI message */
|
||||
#define TI_SCI_MSG_VALUE_RM_RING_ASEL_VALID BIT(7)
|
||||
|
||||
#define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \
|
||||
(TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \
|
||||
TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \
|
||||
TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \
|
||||
TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \
|
||||
TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID)
|
||||
TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID | \
|
||||
TI_SCI_MSG_VALUE_RM_RING_ASEL_VALID)
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_rm_ring_cfg - Ring configuration
|
||||
*
|
||||
* Parameters for Navigator Subsystem ring configuration
|
||||
* See @ti_sci_msg_rm_ring_cfg_req
|
||||
*/
|
||||
struct ti_sci_msg_rm_ring_cfg {
|
||||
u32 valid_params;
|
||||
u16 nav_id;
|
||||
u16 index;
|
||||
u32 addr_lo;
|
||||
u32 addr_hi;
|
||||
u32 count;
|
||||
u8 mode;
|
||||
u8 size;
|
||||
u8 order_id;
|
||||
u16 virtid;
|
||||
u8 asel;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations
|
||||
* @config: configure the SoC Navigator Subsystem Ring Accelerator ring
|
||||
* @get_config: get the SoC Navigator Subsystem Ring Accelerator ring
|
||||
* configuration
|
||||
* @set_cfg: configure the SoC Navigator Subsystem Ring Accelerator ring
|
||||
*/
|
||||
struct ti_sci_rm_ringacc_ops {
|
||||
int (*config)(const struct ti_sci_handle *handle,
|
||||
u32 valid_params, u16 nav_id, u16 index,
|
||||
u32 addr_lo, u32 addr_hi, u32 count, u8 mode,
|
||||
u8 size, u8 order_id
|
||||
);
|
||||
int (*get_config)(const struct ti_sci_handle *handle,
|
||||
u32 nav_id, u32 index, u8 *mode,
|
||||
u32 *addr_lo, u32 *addr_hi, u32 *count,
|
||||
u8 *size, u8 *order_id);
|
||||
int (*set_cfg)(const struct ti_sci_handle *handle,
|
||||
const struct ti_sci_msg_rm_ring_cfg *params);
|
||||
};
|
||||
|
||||
/**
|
||||
@ -320,6 +352,9 @@ struct ti_sci_rm_psil_ops {
|
||||
#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES 2
|
||||
#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES 3
|
||||
|
||||
#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_TCHAN 0
|
||||
#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN 1
|
||||
|
||||
/* UDMAP TX/RX channel valid_params common declarations */
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1)
|
||||
@ -345,6 +380,8 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg {
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID BIT(15)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID BIT(16)
|
||||
u16 nav_id;
|
||||
u16 index;
|
||||
u8 tx_pause_on_err;
|
||||
@ -362,6 +399,8 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg {
|
||||
u16 fdepth;
|
||||
u8 tx_sched_priority;
|
||||
u8 tx_burst_size;
|
||||
u8 tx_tdtype;
|
||||
u8 extended_ch_type;
|
||||
};
|
||||
|
||||
/**
|
||||
@ -520,18 +559,6 @@ struct ti_sci_handle {
|
||||
|
||||
#define TI_SCI_RESOURCE_NULL 0xffff
|
||||
|
||||
/**
|
||||
* struct ti_sci_resource_desc - Description of TI SCI resource instance range.
|
||||
* @start: Start index of the resource.
|
||||
* @num: Number of resources.
|
||||
* @res_map: Bitmap to manage the allocation of these resources.
|
||||
*/
|
||||
struct ti_sci_resource_desc {
|
||||
u16 start;
|
||||
u16 num;
|
||||
unsigned long *res_map;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ti_sci_resource - Structure representing a resource assigned
|
||||
* to a device.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user