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arm64: dts: phygate-tauri-l: add overlays for RS232 and RS485

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UART2 and UART4 can used in following combination,

2 x RS232:
- UART2 and UART4 without flow control
- MUX selection GPIO3_20 must be held low

1 x RS232 + 1 x RS485:
- UART2 - RS232
- UART4 - RS485
- MUX selection GPIO3_20 must be held high
- RE/DE for RS485 controlled with GPIO3_25

1 x RS232 with flow control:
- UART2 - RS232
- MUX selection GPIO3_20 must be held low

Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Parthiban Nallathambi 2024-05-25 22:48:54 +05:30 committed by Shawn Guo
parent 0ce551af51
commit 8d97083c0b
4 changed files with 197 additions and 0 deletions
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8
arch/arm64/boot/dts/freescale/Makefile
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@ -266,6 +266,14 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs485.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-imx219.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-rpidsi.dtb
imx8mm-phygate-tauri-l-rs232-rs232-dtbs := imx8mm-phygate-tauri-l.dtb imx8mm-phygate-tauri-l-rs232-rs232.dtbo
imx8mm-phygate-tauri-l-rs232-cts-rts-dtbs := imx8mm-phygate-tauri-l.dtb imx8mm-phygate-tauri-l-rs232-rts-cts.dtbo
imx8mm-phygate-tauri-l-rs232-rs485-dtbs := imx8mm-phygate-tauri-l.dtb imx8mm-phygate-tauri-l-rs232-rs485.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l-rs232-rs232.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l-rs232-cts-rts.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l-rs232-rs485.dtb
dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb
dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb
dtb-$(CONFIG_ARCH_S32) += s32g399a-rdb3.dtb

72
arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs232.dtso Normal file
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@ -0,0 +1,72 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2021 PHYTEC Messtechnik GmbH
* Author: Jens Lang <j.lang@phytec.de>
*
* Tauri-L 2 x RS232:
* - GPIO3_20 uart4_rs485_en needs to be driven low (inactive)
*/
#include <dt-bindings/clock/imx8mm-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include "imx8mm-pinfunc.h"
/dts-v1/;
/plugin/;
&{/} {
compatible = "phytec,imx8mm-phygate-tauri-l";
};
&gpio3 {
pinctrl-names = "default";
pinctrcl-0 = <&pinctrl_gpio3_hog>;
uart4_rs485_en {
gpio-hog;
gpios = <20 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "uart4_rs485_en";
};
};
/* UART2 - RS232 */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MM_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
status = "okay";
};
/* UART4 - RS232 */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
assigned-clocks = <&clk IMX8MM_CLK_UART4>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
status = "okay";
};
&iomuxc {
pinctrl_gpio3_hog: gpio3hoggrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x49
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49
MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49
>;
};
};

76
arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs485.dtso Normal file
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@ -0,0 +1,76 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2021 PHYTEC Messtechnik GmbH
* Author: Jens Lang <j.lang@phytec.de>
*
* Tauri-L RS232 + RS485:
* - GPIO3_20 uart4_rs485_en needs to be driven high (active)
* - GPIO3_25 RS485_DE Driver enable
*/
#include <dt-bindings/clock/imx8mm-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include "imx8mm-pinfunc.h"
/dts-v1/;
/plugin/;
&{/} {
compatible = "phytec,imx8mm-phygate-tauri-l";
};
&gpio3 {
pinctrl-names = "default";
pinctrcl-0 = <&pinctrl_gpio3_hog>;
uart4_rs485_en {
gpio-hog;
gpios = <20 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "uart4_rs485_en";
};
};
/* UART2 - RS232 */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MM_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
status = "okay";
};
/* UART4 - RS485 */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
assigned-clocks = <&clk IMX8MM_CLK_UART4>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
rts-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>;
linux,rs485-enabled-at-boot-time;
status = "okay";
};
&iomuxc {
pinctrl_gpio3_hog: gpio3hoggrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x49
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49
MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49
MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x49
>;
};
};

41
arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rts-cts.dtso Normal file
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@ -0,0 +1,41 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 PHYTEC Messtechnik GmbH
* Author: Jens Lang <j.lang@phytec.de>
*
* Tauri-L RS232 with RTS/CTS hardware flow control:
* - UART4_TX becomes RTS
* - UART4_RX becomes CTS
*/
#include <dt-bindings/clock/imx8mm-clock.h>
#include "imx8mm-pinfunc.h"
/dts-v1/;
/plugin/;
&{/} {
compatible = "phytec,imx8mm-phygate-tauri-l";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MM_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
&iomuxc {
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00
MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x00
MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x00
>;
};
};