ARM i.MX5: Add system reset controller (SRC) to i.MX51 and i.MX53 device tree

Also, link SRC to IPU via phandle.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Philipp Zabel 2013-03-28 17:35:23 +01:00 committed by Shawn Guo
parent 09ebf36659
commit 8d84c3740f
2 changed files with 14 additions and 0 deletions

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@ -70,6 +70,7 @@
interrupts = <11 10>; interrupts = <11 10>;
clocks = <&clks 59>, <&clks 110>, <&clks 61>; clocks = <&clks 59>, <&clks 110>, <&clks 61>;
clock-names = "bus", "di0", "di1"; clock-names = "bus", "di0", "di1";
resets = <&src 2>;
}; };
aips@70000000 { /* AIPS1 */ aips@70000000 { /* AIPS1 */
@ -529,6 +530,12 @@
status = "disabled"; status = "disabled";
}; };
src: src@73fd0000 {
compatible = "fsl,imx51-src";
reg = <0x73fd0000 0x4000>;
#reset-cells = <1>;
};
clks: ccm@73fd4000{ clks: ccm@73fd4000{
compatible = "fsl,imx51-ccm"; compatible = "fsl,imx51-ccm";
reg = <0x73fd4000 0x4000>; reg = <0x73fd4000 0x4000>;

View File

@ -75,6 +75,7 @@
interrupts = <11 10>; interrupts = <11 10>;
clocks = <&clks 59>, <&clks 110>, <&clks 61>; clocks = <&clks 59>, <&clks 110>, <&clks 61>;
clock-names = "bus", "di0", "di1"; clock-names = "bus", "di0", "di1";
resets = <&src 2>;
}; };
aips@50000000 { /* AIPS1 */ aips@50000000 { /* AIPS1 */
@ -601,6 +602,12 @@
status = "disabled"; status = "disabled";
}; };
src: src@53fd0000 {
compatible = "fsl,imx53-src", "fsl,imx51-src";
reg = <0x53fd0000 0x4000>;
#reset-cells = <1>;
};
clks: ccm@53fd4000{ clks: ccm@53fd4000{
compatible = "fsl,imx53-ccm"; compatible = "fsl,imx53-ccm";
reg = <0x53fd4000 0x4000>; reg = <0x53fd4000 0x4000>;