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ARM i.MX5: Add system reset controller (SRC) to i.MX51 and i.MX53 device tree
Also, link SRC to IPU via phandle. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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@ -70,6 +70,7 @@
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interrupts = <11 10>;
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interrupts = <11 10>;
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clocks = <&clks 59>, <&clks 110>, <&clks 61>;
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clocks = <&clks 59>, <&clks 110>, <&clks 61>;
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clock-names = "bus", "di0", "di1";
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clock-names = "bus", "di0", "di1";
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resets = <&src 2>;
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};
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};
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aips@70000000 { /* AIPS1 */
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aips@70000000 { /* AIPS1 */
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@ -529,6 +530,12 @@
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status = "disabled";
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status = "disabled";
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};
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};
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src: src@73fd0000 {
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compatible = "fsl,imx51-src";
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reg = <0x73fd0000 0x4000>;
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#reset-cells = <1>;
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};
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clks: ccm@73fd4000{
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clks: ccm@73fd4000{
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compatible = "fsl,imx51-ccm";
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compatible = "fsl,imx51-ccm";
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reg = <0x73fd4000 0x4000>;
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reg = <0x73fd4000 0x4000>;
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@ -75,6 +75,7 @@
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interrupts = <11 10>;
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interrupts = <11 10>;
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clocks = <&clks 59>, <&clks 110>, <&clks 61>;
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clocks = <&clks 59>, <&clks 110>, <&clks 61>;
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clock-names = "bus", "di0", "di1";
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clock-names = "bus", "di0", "di1";
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resets = <&src 2>;
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};
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};
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aips@50000000 { /* AIPS1 */
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aips@50000000 { /* AIPS1 */
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@ -601,6 +602,12 @@
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status = "disabled";
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status = "disabled";
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};
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};
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src: src@53fd0000 {
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compatible = "fsl,imx53-src", "fsl,imx51-src";
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reg = <0x53fd0000 0x4000>;
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#reset-cells = <1>;
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};
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clks: ccm@53fd4000{
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clks: ccm@53fd4000{
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compatible = "fsl,imx53-ccm";
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compatible = "fsl,imx53-ccm";
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reg = <0x53fd4000 0x4000>;
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reg = <0x53fd4000 0x4000>;
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