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arm64: dts: ti: k3-am64: Add phase tags marking

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bootph-all as phase tag was added to dt-schema
(dtschema/schemas/bootph.yaml) to describe various node usage during
boot phases with DT.

On TI K3 AM642 SoC, only esm nodes are exclusively used by R5
bootloader, rest of the dts nodes with bootph-* are used by later boot
stages also.

Add bootph-all for all other nodes that are used in the bootloader on
K3 AM642 SoC, and bootph-pre-ram is not needed specifically for any
other node in kernel dts.

Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230911172902.1057417-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Nishanth Menon 2023-09-11 12:29:00 -05:00 committed by Vignesh Raghavendra
parent c412c2f26e
commit 8d5bfa637f
3 changed files with 15 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
arch/arm64/boot/dts/ti/k3-am64-main.dtsi
View File

@ -38,6 +38,7 @@
};
main_conf: syscon@43000000 {
bootph-all;
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
reg = <0x0 0x43000000 0x0 0x20000>;
#address-cells = <1>;
@ -45,6 +46,7 @@
ranges = <0x0 0x0 0x43000000 0x20000>;
chipid@14 {
bootph-all;
compatible = "ti,am654-chipid";
reg = <0x00000014 0x4>;
};
@ -96,6 +98,7 @@
};
dmss: bus@48000000 {
bootph-all;
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
@ -105,6 +108,7 @@
ti,sci-dev-id = <25>;
secure_proxy_main: mailbox@4d000000 {
bootph-all;
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
@ -188,6 +192,7 @@
};
dmsc: system-controller@44043000 {
bootph-all;
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
@ -197,22 +202,26 @@
reg = <0x00 0x44043000 0x00 0xfe0>;
k3_pds: power-controller {
bootph-all;
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clock-controller {
bootph-all;
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
k3_reset: reset-controller {
bootph-all;
compatible = "ti,sci-reset";
#reset-cells = <2>;
};
};
main_pmx0: pinctrl@f4000 {
bootph-all;
compatible = "pinctrl-single";
reg = <0x00 0xf4000 0x00 0x2d0>;
#pinctrl-cells = <1>;
@ -221,6 +230,7 @@
};
main_timer0: timer@2400000 {
bootph-all;
compatible = "ti,am654-timer";
reg = <0x00 0x2400000 0x00 0x400>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
@ -365,6 +375,7 @@
};
main_esm: esm@420000 {
bootph-pre-ram;
compatible = "ti,j721e-esm";
reg = <0x00 0x420000 0x00 0x1000>;
ti,esm-pins = <160>, <161>;

2
arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
View File

@ -146,6 +146,7 @@
};
mcu_pmx0: pinctrl@4084000 {
bootph-all;
compatible = "pinctrl-single";
reg = <0x00 0x4084000 0x00 0x84>;
#pinctrl-cells = <1>;
@ -154,6 +155,7 @@
};
mcu_esm: esm@4100000 {
bootph-pre-ram;
compatible = "ti,j721e-esm";
reg = <0x00 0x4100000 0x00 0x1000>;
ti,esm-pins = <0>, <1>;

2
arch/arm64/boot/dts/ti/k3-am64.dtsi
View File

@ -47,6 +47,7 @@
};
cbass_main: bus@f4000 {
bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@ -85,6 +86,7 @@
<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>;
cbass_mcu: bus@4000000 {
bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;