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amd/dc/dce100: On dce100, set clocks to 0 on suspend

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[Why]
When a dce100 asic was suspended, the clocks were not set to 0.
Upon resume, the new clock was compared to the existing clock,
they were found to be the same, and so the clock was not set.
This resulted in a pernicious blackscreen.

[How]
In atomic commit, check to see if there are any active pipes.
If no, set clocks to 0

Signed-off-by: David Francis <David.Francis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
David Francis 2018-07-12 10:07:49 -04:00 committed by Alex Deucher
parent d89d01f223
commit 8d4235f715
1 changed files with 16 additions and 3 deletions
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19
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
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@ -678,9 +678,22 @@ bool dce100_validate_bandwidth(
struct dc *dc, struct dc *dc,
struct dc_state *context) struct dc_state *context)
{ {
/* TODO implement when needed but for now hardcode max value*/ int i;
context->bw.dce.dispclk_khz = 681000; bool at_least_one_pipe = false;
context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
if (context->res_ctx.pipe_ctx[i].stream)
at_least_one_pipe = true;
}
if (at_least_one_pipe) {
/* TODO implement when needed but for now hardcode max value*/
context->bw.dce.dispclk_khz = 681000;
context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER;
} else {
context->bw.dce.dispclk_khz = 0;
context->bw.dce.yclk_khz = 0;
}
return true; return true;
} }