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PCI ASPM: cleanup initialization
Clean up ASPM initialization by refactoring some functionality, renaming functions, and moving things around. Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
This commit is contained in:
Kenji Kaneshige
Jesse Barnes
parent
5aa63583cb
commit
8d349ace9a
@ -126,7 +126,7 @@ static void pcie_set_clock_pm(struct pcie_link_state *link, int enable)
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link->clkpm_enabled = !!enable;
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}
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static void pcie_check_clock_pm(struct pcie_link_state *link, int blacklist)
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static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
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{
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int pos, capable = 1, enabled = 1;
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u32 reg32;
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@ -151,13 +151,7 @@ static void pcie_check_clock_pm(struct pcie_link_state *link, int blacklist)
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}
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link->clkpm_enabled = enabled;
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link->clkpm_default = enabled;
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if (!blacklist) {
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link->clkpm_capable = capable;
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pcie_set_clock_pm(link, policy_to_clkpm_state(link));
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} else {
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link->clkpm_capable = 0;
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pcie_set_clock_pm(link, 0);
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}
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link->clkpm_capable = (blacklist) ? 0 : capable;
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}
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static bool pcie_aspm_downstream_has_switch(struct pcie_link_state *link)
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@ -314,12 +308,23 @@ static void pcie_aspm_get_cap_device(struct pci_dev *pdev, u32 *state,
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*enabled = reg16 & (PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1);
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}
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static void pcie_aspm_cap_init(struct pcie_link_state *link)
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static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
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{
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u32 support, l0s, l1, enabled;
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struct pci_dev *child, *parent = link->pdev;
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struct pci_bus *linkbus = parent->subordinate;
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if (blacklist) {
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/* Set support state to 0, so we will disable ASPM later */
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link->aspm_support = 0;
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link->aspm_default = 0;
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link->aspm_enabled = PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1;
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return;
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}
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/* Configure common clock before checking latencies */
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pcie_aspm_configure_common_clock(link);
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/* upstream component states */
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pcie_aspm_get_cap_device(parent, &support, &l0s, &l1, &enabled);
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link->aspm_support = support;
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@ -590,6 +595,42 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
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return 0;
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}
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static struct pcie_link_state *pcie_aspm_setup_link_state(struct pci_dev *pdev)
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{
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struct pcie_link_state *link;
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int blacklist = !!pcie_aspm_sanity_check(pdev);
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link = kzalloc(sizeof(*link), GFP_KERNEL);
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if (!link)
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return NULL;
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INIT_LIST_HEAD(&link->sibling);
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INIT_LIST_HEAD(&link->children);
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INIT_LIST_HEAD(&link->link);
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link->pdev = pdev;
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link->has_switch = pcie_aspm_downstream_has_switch(link);
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if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) {
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struct pcie_link_state *parent;
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parent = pdev->bus->parent->self->link_state;
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if (!parent) {
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kfree(link);
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return NULL;
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}
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link->parent = parent;
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list_add(&link->link, &parent->children);
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}
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list_add(&link->sibling, &link_list);
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pdev->link_state = link;
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/* Check ASPM capability */
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pcie_aspm_cap_init(link, blacklist);
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/* Check Clock PM capability */
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pcie_clkpm_cap_init(link, blacklist);
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return link;
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}
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/*
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* pcie_aspm_init_link_state: Initiate PCI express link state.
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* It is called after the pcie and its children devices are scaned.
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@ -597,80 +638,47 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
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*/
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void pcie_aspm_init_link_state(struct pci_dev *pdev)
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{
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unsigned int state;
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struct pcie_link_state *link_state;
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int error = 0;
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int blacklist;
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u32 state;
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struct pcie_link_state *link;
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if (aspm_disabled || !pdev->is_pcie || pdev->link_state)
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return;
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if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
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pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
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pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
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return;
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/* VIA has a strange chipset, root port is under a bridge */
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if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT &&
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pdev->bus->self)
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pdev->bus->self)
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return;
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down_read(&pci_bus_sem);
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if (list_empty(&pdev->subordinate->devices))
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goto out;
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blacklist = !!pcie_aspm_sanity_check(pdev);
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mutex_lock(&aspm_lock);
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link_state = kzalloc(sizeof(*link_state), GFP_KERNEL);
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if (!link_state)
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goto unlock_out;
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INIT_LIST_HEAD(&link_state->children);
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INIT_LIST_HEAD(&link_state->link);
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if (pdev->bus->self) {/* this is a switch */
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struct pcie_link_state *parent_link_state;
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parent_link_state = pdev->bus->parent->self->link_state;
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if (!parent_link_state) {
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kfree(link_state);
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goto unlock_out;
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}
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list_add(&link_state->link, &parent_link_state->children);
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link_state->parent = parent_link_state;
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}
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link_state->pdev = pdev;
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link_state->has_switch = pcie_aspm_downstream_has_switch(link_state);
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pdev->link_state = link_state;
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if (!blacklist) {
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pcie_aspm_configure_common_clock(link_state);
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pcie_aspm_cap_init(link_state);
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link = pcie_aspm_setup_link_state(pdev);
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if (!link)
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goto unlock;
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/*
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* Setup initial ASPM state
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*
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* If link has switch, delay the link config. The leaf link
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* initialization will config the whole hierarchy. But we must
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* make sure BIOS doesn't set unsupported link state.
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*/
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if (link->has_switch) {
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state = pcie_aspm_check_state(link, link->aspm_default);
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__pcie_aspm_config_link(link, state);
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} else {
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link_state->aspm_enabled =
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(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
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link_state->aspm_default = 0;
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/* Set support state to 0, so we will disable ASPM later */
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link_state->aspm_support = 0;
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state = policy_to_aspm_state(link);
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__pcie_aspm_configure_link_state(link, state);
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}
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list_add(&link_state->sibling, &link_list);
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if (link_state->has_switch) {
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/*
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* If link has switch, delay the link config. The leaf link
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* initialization will config the whole hierarchy. but we must
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* make sure BIOS doesn't set unsupported link state
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**/
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state = pcie_aspm_check_state(link_state,
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link_state->aspm_default);
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__pcie_aspm_config_link(link_state, state);
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} else
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__pcie_aspm_configure_link_state(link_state,
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policy_to_aspm_state(link_state));
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pcie_check_clock_pm(link_state, blacklist);
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unlock_out:
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if (error)
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free_link_state(link_state);
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/* Setup initial Clock PM state */
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state = (link->clkpm_capable) ? policy_to_clkpm_state(link) : 0;
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pcie_set_clock_pm(link, state);
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unlock:
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mutex_unlock(&aspm_lock);
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out:
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up_read(&pci_bus_sem);
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