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sata_mv: leave SError bits untouched in mv_err_intr
Here it is again, minus the checkpatch.pl complaint: Rework mv_err_intr() to leave the SError bits as-is, so that libata-eh has a chance to see/use them. We originally thought that clearing them here was necessary before writing back to edma_err_cause (per the Marvell datasheets), but we will end up reseting the chip regardless in those cases. Signed-off-by: Mark Lord <mlord@pobox.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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@ -1523,13 +1523,11 @@ static void mv_unexpected_intr(struct ata_port *ap)
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/**
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* mv_err_intr - Handle error interrupts on the port
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* @ap: ATA channel to manipulate
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* @reset_allowed: bool: 0 == don't trigger from reset here
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* @qc: affected command (non-NCQ), or NULL
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*
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* In most cases, just clear the interrupt and move on. However,
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* some cases require an eDMA reset, which also performs a COMRESET.
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* The SERR case requires a clear of pending errors in the SATA
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* SERROR register. Finally, if the port disabled DMA,
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* update our cached copy to match.
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* Most cases require a full reset of the chip's state machine,
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* which also performs a COMRESET.
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* Also, if the port disabled DMA, update our cached copy to match.
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*
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* LOCKING:
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* Inherited from caller.
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@ -1540,21 +1538,18 @@ static void mv_err_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
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u32 edma_err_cause, eh_freeze_mask, serr = 0;
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struct mv_port_priv *pp = ap->private_data;
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struct mv_host_priv *hpriv = ap->host->private_data;
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unsigned int edma_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
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unsigned int action = 0, err_mask = 0;
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struct ata_eh_info *ehi = &ap->link.eh_info;
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ata_ehi_clear_desc(ehi);
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if (!edma_enabled) {
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/* just a guess: do we need to do this? should we
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* expand this, and do it in all cases?
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*/
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sata_scr_read(&ap->link, SCR_ERROR, &serr);
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sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
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}
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/*
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* Read and clear the err_cause bits. This won't actually
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* clear for some errors (eg. SError), but we will be doing
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* a hard reset in those cases regardless, which *will* clear it.
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*/
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edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
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writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
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ata_ehi_push_desc(ehi, "edma_err_cause=%08x", edma_err_cause);
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@ -1594,16 +1589,19 @@ static void mv_err_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
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ata_ehi_push_desc(ehi, "EDMA self-disable");
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}
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if (edma_err_cause & EDMA_ERR_SERR) {
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sata_scr_read(&ap->link, SCR_ERROR, &serr);
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sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
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err_mask = AC_ERR_ATA_BUS;
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/*
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* Ensure that we read our own SCR, not a pmp link SCR:
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*/
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ap->ops->scr_read(ap, SCR_ERROR, &serr);
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/*
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* Don't clear SError here; leave it for libata-eh:
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*/
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ata_ehi_push_desc(ehi, "SError=%08x", serr);
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err_mask |= AC_ERR_ATA_BUS;
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action |= ATA_EH_RESET;
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}
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}
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/* Clear EDMA now that SERR cleanup done */
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writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
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if (!err_mask) {
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err_mask = AC_ERR_OTHER;
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action |= ATA_EH_RESET;
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