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ath9k_hw: Fix PAPRD training
The PAPRD training control registers have to be programmed with values that depend on the chip. This patch ensures that the correct values are chosen for the chip in use. Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -204,7 +204,20 @@ static int ar9003_paprd_setup_single_table(struct ath_hw *ah)
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AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING, 28);
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REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
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AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE, 1);
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val = AR_SREV_9462(ah) ? 0x91 : 147;
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if (AR_SREV_9485(ah)) {
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val = 148;
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} else {
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if (IS_CHAN_2GHZ(ah->curchan)) {
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if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
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val = 145;
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else
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val = 147;
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} else {
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val = 137;
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}
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}
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REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL2,
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AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN, val);
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REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
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@ -215,15 +228,24 @@ static int ar9003_paprd_setup_single_table(struct ath_hw *ah)
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AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7);
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REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
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AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1);
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if (AR_SREV_9485(ah) || AR_SREV_9462(ah) || AR_SREV_9550(ah))
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if (AR_SREV_9485(ah) ||
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AR_SREV_9462(ah) ||
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AR_SREV_9565(ah) ||
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AR_SREV_9550(ah) ||
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AR_SREV_9330(ah) ||
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AR_SREV_9340(ah))
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REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
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AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP,
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-3);
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AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, -3);
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else
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REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
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AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP,
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-6);
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val = AR_SREV_9462(ah) ? -10 : -15;
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AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, -6);
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val = -10;
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if (IS_CHAN_2GHZ(ah->curchan) && !AR_SREV_9462(ah) && !AR_SREV_9565(ah))
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val = -15;
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REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
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AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE,
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val);
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